AU3570697A - Method and apparatus for optimization of standard cell libraries - Google Patents

Method and apparatus for optimization of standard cell libraries

Info

Publication number
AU3570697A
AU3570697A AU35706/97A AU3570697A AU3570697A AU 3570697 A AU3570697 A AU 3570697A AU 35706/97 A AU35706/97 A AU 35706/97A AU 3570697 A AU3570697 A AU 3570697A AU 3570697 A AU3570697 A AU 3570697A
Authority
AU
Australia
Prior art keywords
optimization
standard cell
cell libraries
libraries
standard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU35706/97A
Inventor
Louis C. Fisher
John S. Jensen
Thomas F. Rossman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cascade Design Automation Corp
Original Assignee
Cascade Design Automation Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cascade Design Automation Corp filed Critical Cascade Design Automation Corp
Publication of AU3570697A publication Critical patent/AU3570697A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AU35706/97A 1996-06-14 1997-06-13 Method and apparatus for optimization of standard cell libraries Abandoned AU3570697A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US1976796P 1996-06-14 1996-06-14
US60019767 1996-06-14
PCT/US1997/010305 WO1997048061A1 (en) 1996-06-14 1997-06-13 Method and apparatus for optimization of standard cell libraries

Publications (1)

Publication Number Publication Date
AU3570697A true AU3570697A (en) 1998-01-07

Family

ID=21794930

Family Applications (1)

Application Number Title Priority Date Filing Date
AU35706/97A Abandoned AU3570697A (en) 1996-06-14 1997-06-13 Method and apparatus for optimization of standard cell libraries

Country Status (5)

Country Link
EP (1) EP0852768A1 (en)
JP (1) JPH11511907A (en)
AU (1) AU3570697A (en)
CA (1) CA2229404A1 (en)
WO (1) WO1997048061A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4813499B2 (en) 2005-11-01 2011-11-09 富士通株式会社 Logic cell configuration processing method and program

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6124250A (en) * 1984-07-13 1986-02-01 Nippon Gakki Seizo Kk Semiconductor integrated circuit device
JPS63308343A (en) * 1987-06-10 1988-12-15 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit
US5031111C1 (en) * 1988-08-08 2001-03-27 Trw Inc Automated circuit design method
US5173864A (en) * 1988-08-20 1992-12-22 Kabushiki Kaisha Toshiba Standard cell and standard-cell-type integrated circuit
JP3017789B2 (en) * 1990-10-18 2000-03-13 三菱電機株式会社 Layout design method for semiconductor integrated circuit device
US5459673A (en) * 1990-10-29 1995-10-17 Ross Technology, Inc. Method and apparatus for optimizing electronic circuits
US5225991A (en) * 1991-04-11 1993-07-06 International Business Machines Corporation Optimized automated macro embedding for standard cell blocks
JPH05274390A (en) * 1992-03-30 1993-10-22 Matsushita Electric Ind Co Ltd Circuit element allocation method, delay optimization method and logic design system
US5487018A (en) * 1993-08-13 1996-01-23 Vlsi Technology, Inc. Electronic design automation apparatus and method utilizing a physical information database
US5563801A (en) * 1993-10-06 1996-10-08 Nsoft Systems, Inc. Process independent design for gate array devices

Also Published As

Publication number Publication date
CA2229404A1 (en) 1997-12-18
WO1997048061A1 (en) 1997-12-18
JPH11511907A (en) 1999-10-12
EP0852768A1 (en) 1998-07-15

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