JPH11511283A - 整合スペクトルヌルエンコーダ／デコーダ - Google Patents

整合スペクトルヌルエンコーダ／デコーダ

Info

Publication number
JPH11511283A
JPH11511283A JP9508574A JP50857497A JPH11511283A JP H11511283 A JPH11511283 A JP H11511283A JP 9508574 A JP9508574 A JP 9508574A JP 50857497 A JP50857497 A JP 50857497A JP H11511283 A JPH11511283 A JP H11511283A
Authority
JP
Japan
Prior art keywords
value
values
state
bit
coded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP9508574A
Other languages
English (en)
Japanese (ja)
Inventor
フレドリクソン，ライザ
Original Assignee
シーゲート テクノロジー，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シーゲート テクノロジー，インコーポレイテッド filed Critical シーゲート テクノロジー，インコーポレイテッド
Publication of JPH11511283A publication Critical patent/JPH11511283A/ja
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/497—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H03M5/145—Conversion to or from block codes or representations thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Error Detection And Correction (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
JP9508574A 1995-08-03 1996-08-02 整合スペクトルヌルエンコーダ／デコーダ Ceased JPH11511283A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US198695P 1995-08-03 1995-08-03
US60/001,986 1995-08-03
PCT/US1996/012680 WO1997006624A1 (en) 1995-08-03 1996-08-02 Matched spectral null encoder/decoder

Publications (1)

Publication Number Publication Date
JPH11511283A true JPH11511283A (ja) 1999-09-28

Family

ID=21698714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9508574A Ceased JPH11511283A (ja) 1995-08-03 1996-08-02 整合スペクトルヌルエンコーダ／デコーダ

Country Status (6)

Country Link
US (1) US5801649A (ko)
EP (1) EP0842577B1 (ko)
JP (1) JPH11511283A (ko)
KR (1) KR100406330B1 (ko)
DE (1) DE69628172T2 (ko)
WO (1) WO1997006624A1 (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6032284A (en) * 1997-03-12 2000-02-29 Cirrus Logic, Inc. Trellis coding system for disc storage systems
US6185173B1 (en) 1998-07-31 2001-02-06 Cirrus Logic, Inc. Sampled amplitude read channel employing a trellis sequence detector matched to a channel code constraint and a post processor for correcting errors in the detected binary sequence using the signal samples and an error syndrome
WO2000057559A1 (de) * 1999-03-18 2000-09-28 Siemens Aktiengesellschaft Verfahren und prozessoreinheit zur abbildung von informationen mit variablem wertebereich auf codewörter
JP4239314B2 (ja) * 1999-09-06 2009-03-18 ソニー株式会社 符号化装置および方法、復号装置および方法、および記録媒体
US6570509B2 (en) * 2000-03-03 2003-05-27 Motorola, Inc. Method and system for encoding to mitigate decoding errors in a receiver
CN1305220C (zh) * 2001-07-09 2007-03-14 希捷科技有限公司 用于抑制数字数据内低频含量的方法和装置
US6538586B1 (en) * 2002-01-30 2003-03-25 Intel Corporation Data encoding strategy to reduce selected frequency components in a serial bit stream
US7084789B2 (en) * 2003-11-17 2006-08-01 Seagate Technology Llc DC-free code having limited error propagation and limited complexity
US6989776B2 (en) * 2003-11-17 2006-01-24 Seagate Technology Llc Generation of interleaved parity code words having limited running digital sum values
US7002492B2 (en) * 2004-07-07 2006-02-21 Seagate Technology Llc High rate running digital sum-restricted code
US7460032B2 (en) * 2005-10-27 2008-12-02 Evault, Inc. Methods and apparatus for performing adaptive compression
US9031241B2 (en) * 2009-02-05 2015-05-12 D.E. Shaw Research, Llc Link and physical coding sub-layer protocols
KR20100136890A (ko) * 2009-06-19 2010-12-29 삼성전자주식회사 컨텍스트 기반의 산술 부호화 장치 및 방법과 산술 복호화 장치 및 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4486739A (en) * 1982-06-30 1984-12-04 International Business Machines Corporation Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code
NL8402445A (nl) * 1984-01-20 1985-08-16 Philips Nv Werkwijze voor het coderen van n-bits informatiewoorden naar m-bits codewoorden, inrichting voor het uitvoeren van die werkwijze, werkwijze voor het decoderen van m-bits codewoorden naar n-bits informatiewoorden en inrichting voor het uitvoeren van die werkwijze.
US4888779A (en) * 1988-03-18 1989-12-19 International Business Machines Corporation Matched spectral null trellis codes for partial response channels
JPH0362621A (ja) * 1989-07-31 1991-03-18 Ricoh Co Ltd データ変調方式
US5208834A (en) * 1991-03-15 1993-05-04 International Business Machines Corporation Lexicographical encoding and decoding of state-dependent codes
US5497384A (en) * 1993-12-29 1996-03-05 International Business Machines Corporation Permuted trellis codes for input restricted partial response channels
US5537424A (en) * 1994-08-12 1996-07-16 International Business Machines Corporation Matched spectral null codes with partitioned systolic trellis structures
US5608397A (en) * 1995-08-15 1997-03-04 Lucent Technologies Inc. Method and apparatus for generating DC-free sequences
US5731768A (en) * 1996-01-31 1998-03-24 Seagate Technology, Inc. Method and apparatus for implementing codes with maximum transition run length

Also Published As

Publication number Publication date
DE69628172T2 (de) 2004-04-01
EP0842577B1 (en) 2003-05-14
KR19990036097A (ko) 1999-05-25
DE69628172D1 (de) 2003-06-18
WO1997006624A1 (en) 1997-02-20
EP0842577A1 (en) 1998-05-20
US5801649A (en) 1998-09-01
KR100406330B1 (ko) 2005-05-09

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