JPH1140908A - Printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board which can position a printing mask to an opening, can form suitable height of soldering bump, and can prevent shape deformation of the opening for realizing suitable mounting of a semiconductor element, etc., even when a positional misalignment has taken place between an alignment mark and the opening of a solder resist layer. SOLUTION: A printed wiring board 5 includes individual substrates, which have respectively an alignment mark 13 for positioning of an IC chip and an alignment mark 130 for mounting of the board 5 to a in motherboard in the form of a semiconductor package. Provided on each substrate in its outer periphery are alignment marks 12 for positioning to a printing mask 1. The marks 12 are formed to openings 14B, from which only a surface of a conductive layer 120 from a solder resist layer 14 formed on the layer 120 is exposed. Further a rough layer 7 is provided on a surface of the conductive layer 120 which constitutes the alignment marks 13, 130 and 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board having an alignment mark, and more particularly, to a method for opening a printing mask even when a displacement occurs between each alignment mark and an opening of a solder resist layer. It is possible to form solder bumps of an appropriate height, and it is also possible to form a printed wiring board on which a semiconductor element is mounted and packaged by mounting the semiconductor element. The present invention relates to a printed wiring board in which an opening serving as an alignment mark is prevented from being lost due to peeling of a solder resist layer when being mounted on such another printed wiring board so that mounting is not possible.

[0002]

2. Description of the Related Art Conventionally, pads for mounting semiconductor elements (IC chips) on the surface of a printed wiring board have been so-called,
A group of solder bumps is formed, and the IC chip is mounted on a printed wiring board by heating the IC chip while placing the connection terminals on the solder bumps while positioning them.

Here, as a method of forming a solder bump on an IC chip mounting pad of a printed wiring board,
For example, an alignment mark for alignment is formed on both a printing mask such as a metal mask or a plastic mask and a printed wiring board, and the printing mask and the printed wiring board are aligned so that each alignment mark is aligned. After lamination, a method of printing cream solder on an IC chip mounting pad and performing a reflow process is adopted. At this time, the alignment mark formed on the printed wiring board is generally formed of a conductor layer smaller than the opening formed in the solder resist layer so as to expose the alignment mark. The mark will be completely exposed from the opening of the solder resist layer.

In addition, an alignment mark for positioning the IC chip and the solder bump formed on the pad for mounting the IC chip as described above when mounting the IC chip is provided on the printed wiring board. When mounting the packaged printed wiring board on the motherboard, alignment marks for aligning the package with the motherboard are also formed, and such alignment marks are used for alignment with the printing mask. Like the alignment mark used, the alignment mark is formed of a conductor layer smaller than the opening formed in the solder resist layer and is completely exposed from the opening of the solder resist layer.

However, as described above, the position of the printed wiring board and the printing mask, the mounting pad and the I
An alignment mark for positioning the C chip and I
The photosensitive mark is printed on the printed wiring board so that the alignment mark for positioning the printed wiring board packaged by mounting the C chip on another wiring board is completely exposed from the opening of the solder resist layer. When a photomask for forming an opening is placed after applying the resin, the photomask may be displaced from the alignment mark.

In this case, the alignment mark cannot be completely exposed from the opening. Even in such a case, when positioning the printing mask or the IC chip, the center of the conductor layer forming the alignment mark is the reference position for positioning. Therefore, when the cream solder is printed on the IC chip mounting pad via the printing mask, the amount of cream solder to be supplied to the pad is reduced due to the misalignment between the alignment mark and the opening. As a result, the height of the solder bump formed on the IC chip mounting pad is reduced. Also, in the case where the IC chip is mounted on the IC chip mounting pad, and in the case where the printed circuit board on which the IC chip is mounted and packaged is an alignment mark for mounting on another wiring board,
Similarly to the above, due to the misalignment between the alignment mark and the opening, the IC chip is mounted on the pad with the misalignment, or mounted on the motherboard with the misaligned package substrate. There is a possibility that a problem may occur in the connection strength between the IC chip and the pad, or an operation failure may occur.

In particular, when a conductor layer for an alignment mark is formed by a semi-additive method, the conductor is easily peeled off because the plating resist does not exist, and when the conductor layer is completely exposed from the opening, the conductor layer is peeled off. However, there was also a problem that it did not function as an alignment mark. To cope with such a problem, Japanese Patent Application Laid-Open No. 2-39485 discloses an alignment mark including a conductor layer for an eye mark and a solder resist layer having an opening exposing only the conductor layer.

This alignment mark is formed from an opening exposing only the conductor layer surface from the solder resist layer formed on the conductor layer, so that the alignment mark is positioned between each alignment mark and the opening of the solder resist layer. Even when misalignment occurs, the printing mask can be aligned with the opening, a solder bump having an appropriate height can be formed, and the semiconductor element can be aligned with each solder bump and the package can be adjusted. The substrate can be mounted on the motherboard, and the semiconductor element and the packaged printed wiring board can be mounted properly.

[0009]

However, such an alignment mark is used as an alignment mark because the solder resist layer near the opening is easily peeled off due to handling, moisture absorption, heat cycling, etc., and the shape of the opening is distorted. There was a problem that it could not be recognized and could not be aligned. An object of the present invention is to provide a printed wiring board that prevents deformation of an opening in a solder resist due to handling, moisture absorption, thermal cycling, and the like, and does not impair the alignment mark function.

[0010]

According to a first aspect of the present invention, there is provided a printed wiring board comprising: a conductor layer provided on a substrate; and a solder resist layer formed on the conductor layer. An opening is formed so as to expose only the conductor layer in the solder resist layer, and in the printed wiring board in which the opening is used as an alignment mark for positioning, a roughened layer is formed on the surface of the conductor layer. A printed wiring board characterized by the following.

In the printed wiring board according to the present invention, the alignment mark is formed from an opening exposing only the surface of the conductor layer from a solder resist layer formed on the conductor layer, and the center of the opening is positioned. Since the conductor layer surface is roughened, the solder resist and the conductor layer are completely adhered through the roughened layer, and the opening due to handling, moisture absorption, thermal cycling, etc. There is no deformation of the part. In addition, the conductor layer for the alignment mark has many independent forms that are not connected to the wiring pattern and is easily peeled, but the conductor layer is in close contact with the solder resist layer via the roughened layer, and the conductor layer is peeled off. Can be prevented.

In the printed wiring board of the present invention, the alignment mark is used as a reference for positioning the printed mask and the printed wiring board when cream solder is printed on a semiconductor element mounting pad via a printing mask. Is done. In this printed wiring board, the center of the opening is used as a reference position for alignment, and even if the position of the opening, which is an alignment mark, is shifted from the design position, the opening of the mounting pad portion is shifted in the same shift direction. Since the positions of the parts also shift, the solder paste can always be accurately printed in the openings of the mounting pads, and it is possible to form solder bumps of an appropriate height.

In the printed wiring board according to a third aspect of the present invention, the alignment mark is used for positioning the semiconductor element and a mounting pad provided on the printed wiring board when mounting the semiconductor element. In this printed wiring board,
The center of the opening can be used as a reference position for alignment, and even if the position of the opening, which is the alignment mark, deviates from the design position, the position of the opening of the mounting pad in the same displacement direction As a result, the IC chip can always be mounted accurately. In addition, since the roughened layer on the surface of the conductor layer is in close contact with the solder resist, the alignment mark can be accurately recognized without deformation of the opening shape.

In the printed wiring board according to the present invention, the alignment mark is used for positioning when the printed wiring board on which an IC chip is mounted and packaged is mounted on another printed wiring board such as a motherboard. . Since the conductor layer is in close contact with the solder resist due to the roughened layer on the surface, the solder resist near the opening does not peel off or lose due to handling, moisture absorption, thermal cycling, etc. The alignment mark can be recognized accurately without any problems, and the mounting accuracy is excellent.

In the printed wiring board of the present invention, a copper-nickel-phosphorus needle-like alloy is used as a roughened layer on the surface of the conductor layer. This is because the adhesiveness with the solder resist layer is excellent.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a printed wiring board according to the present invention will be described in detail with reference to the drawings based on an embodiment embodying the present invention. First, an external configuration of a printed wiring board according to the present embodiment will be described with reference to FIG. FIG. 1 is a plan view of a printed wiring board.

In FIG. 1, the printed wiring board 5 has a predetermined size (about 340 mm × 255 mm).
From the printed wiring board 5, for example, 30 individual substrates C (about 50 mm × 50 mm) can be formed. In each of the individual substrates C, mounting pads 11 (having a size of about 150 μm) to which IC chips such as flip chips and CPSs are connected and mounted at a predetermined pitch (about 0.3 mm) are provided at a central portion thereof. (About 1000). In addition, 2 outside the mounting pad 11
In some places, an alignment mark 13 used for alignment with the IC chip when mounting the IC chip, and an alignment mark 130 for mounting a printed wiring board packaged by mounting the IC chip.
Are formed, and alignment marks 12 used when performing alignment with a printing mask are formed at two positions outside each individual substrate C. FIG.
The middle area A indicates a product portion in which each individual substrate C is formed from the printed wiring board 5.

Next, a detailed configuration of the printed wiring board 5 and a method of forming solder bumps on the mounting pads 11 will be described with reference to FIG. FIG. 2 is an explanatory view continuously showing a series of methods for forming solder bumps on the mounting pad 11.

In the printed wiring board 5 shown in FIG. 2, a first conductor circuit 8 and an interlayer insulating layer (adhesive layer for electroless plating) 9 are formed on an insulating base material 6. 9, a plating resist layer (permanent resist layer) 1
0 is formed and the plating resist layer 10
Is formed with a mounting pad 11 (conductor pattern) which is a part of the second-layer conductive circuit. Further, alignment marks 13 and 130 are provided outside the mounting pad 11 and alignment marks 12 are provided outside the product part A. Further, on the plating resist layer 10, a solder resist layer 14 for protecting portions other than the alignment marks 13, 130, 12 and the mounting pads 11 at the time of the reflow process is formed. The solder resist layer 14 has openings 14 corresponding to the mounting pads 11.
An opening 14B is formed corresponding to A and each of the alignment marks 13, 130, 12.

Here, the first-layer conductor circuit 8 and the second-layer conductor circuit of the printed wiring board 5 are formed in multiple layers by a so-called build-up method. However, each conductor circuit need not be a multilayer, and may be a single layer. Examples of the insulating base material 6 include a resin substrate, a ceramic substrate, a glass substrate,
A thin film substrate or the like can be used. The thickness of the insulating base 6 is
Usually, it is preferable that it is about 0.1 mm to 2 mm.

Each alignment mark 13, 130, 12
As shown in FIG. 1, two are provided for each individual substrate C and for each printed wiring board 5, and the shape of the alignment marks 13 and 12 is not particularly limited. And a circle having a diameter of 0.5 to 1.5 mm is desirable. The alignment mark 130 preferably has a cross shape as shown in FIG.

Further, each of the alignment marks 13, 13
At 0 and 12, the pad area is formed larger than the opening area of the opening 14B of the solder resist layer 14, so that each of the alignment marks 13, 130,
The periphery of the 12 conductor layers overlaps with the solder resist layer 14, and only the conductor layers are exposed from the openings 14B of the solder resist layer 14.

Based on this, each alignment mark 1
3, 130 and 12 are formed by the openings 14B which expose only the surface of the conductor layer 120 from the solder resist layer 14 formed on the conductor layer 120, and the surface of the conductor layer has a roughened layer. 7 are formed. Advantages of such a configuration will be described with reference to FIGS. 3 and 4 taking the alignment mark 12 as an example.

In FIG. 3A, the alignment mark 1
Reference numeral 2 denotes an opening 14B that exposes only the surface of the conductor layer 120 from the solder resist layer 14 formed on the conductor layer 120. That is, as shown in FIG. 3D, the periphery of the conductor layer 120 overlaps with the solder resist layer 14, and the plating resist 1 around the conductor layer 120 extends from the opening 14 </ b> B of the solder resist layer 14.
0 and the interlayer insulating material layer 9 are not exposed, and only the conductor layer 120 is exposed.

In the case of such an alignment mark 12, positioning with respect to the printing mask is performed by recognizing the center of the opening 14B as the center of the mark. The opening 14B of the solder resist layer 14 forms a photosensitive resin layer,
Exposure and development are performed with a photomask covered. However, when a photomask is placed, a positional shift may occur.

If the position of the opening 14B of the solder resist layer 14 shifts as shown in FIG. 3B, the center of the opening 14B becomes the center of the alignment mark. The position of the alignment mark also shifts according to the shift amount of the position of the portion 14B, and as a result, the position of the printing mask also shifts following the shift of the opening position of the solder resist layer 14. Therefore, the printing mask can always be adjusted to the opening of the solder resist layer 14 regardless of the displacement of the opening position of the solder resist layer 14. For this reason, the printed amount of the cream solder is not reduced by the solder resist layer 14 as shown in FIG. 3C, and a certain height of the solder bump is ensured even when the solder bump is formed by heating and melting. it can.

However, when the conductor layer 120 is completely exposed from the solder resist layer as shown in FIGS. 4A and 4D, the conductor layer 120 itself becomes the alignment mark 12. The mark center of the alignment mark 12 is the center of the conductor layer 120. If the position of the opening 14B of the solder resist layer 14 is shifted as shown in FIG. 4B, the center of the conductor layer 120 becomes the center of the alignment mark. Even if the position is shifted, the position of the alignment mark 12 is not shifted.

Therefore, the printing mask is placed on the basis of the alignment mark 12, and as shown in FIG. 3 (c), a displacement occurs between the opening of the solder resist layer 14 and the opening of the printing mask. Even when the cream solder 15 is printed, the amount of printing is reduced by the solder resist layer 14, and when the solder bump is formed by heating and melting, the solder bump becomes low.

The alignment marks 13, 130,
Twelve conductor layers are provided with a roughened layer 7 on the surface thereof, and the adhesion to the solder resist layer 14 is increased at the peripheral edge of the conductor layer. Thereby, the solder resist layer 14 is prevented from peeling, the opening is prevented from being deformed, and the function of each of the alignment marks 13, 130, 12 can be reliably maintained. Therefore, the alignment mark 12 as shown in FIG. 3 is relatively advantageous.

The roughening layer 7 is desirably a needle-like alloy plating layer made of copper-nickel-phosphorus, and the roughening layer 7 is formed by electroless plating. The plating solution composition at this time includes copper ion concentration, nickel ion concentration,
The hypophosphite ion concentration is 2.2 × 10 ^-2 or less, respectively.
4.1 × 10 ⁻² mol / l, 2.2 × 10 ^{−3 to} 4.1 ×
It is preferably 10 ⁻³ mol / l and 0.20 to 0.25 mol / l. According to the plating solution having such a composition, the crystal structure of the deposited film has a needle-like structure, and it is considered that the anchoring effect is excellent. In addition, a complexing agent or an additive may be added to the electroless plating bath in addition to the above compounds.

The composition of the alloy layer deposited from the electroless plating solution as described above is 90 to 96% by weight, 1 to 5% by weight, and 0.5 to 2% by weight in terms of copper, nickel and phosphorus, respectively.
Is desirable. This is based on the fact that the alloy layer has a needle-like structure at such a composition ratio.

As shown in FIG. 5, the alignment marks 13, 130 and 12 can also be formed by a semi-additive method. Here, in the semi-additive method, an electroless plating film is formed on the surface of the roughened electroless plating adhesive layer, a resist is provided on the electroless plating film, electrolytic plating is performed, and then the plating resist is removed. This is a method of independently forming a conductor circuit by removing and etching the electroless plating film under the plating resist. According to the semi-additive method, the alignment marks 13, 130, 12 are composed of the electroless plating film 19 and the electrolytic plating film 18. When the roughened layer 7 is formed on the side surface and the upper surface, it is possible to prevent vertical cracks from being generated in the solder resist layer 14 and the like from the interface between the solder resist layer 14 and the alignment marks 13, 130, 12 during a heat cycle. Each alignment mark 13, 13
It is desirable that a metal layer 16 made of nickel-gold is further formed on the conductor layer exposed from the opening at 0 and 12 (preferably a roughened layer 7 is formed on the surface). . Here, since gold has a high reflectance, it is advantageous that gold is coated on the surfaces of the alignment marks 13, 130 and 12. The metal layer 16 made of nickel-gold can be formed by electroless plating. Metal layer 16
Is 5 μm, and may be flash gold plating with a gold thickness of 0.1 μm or thick gold plating with a gold thickness of 0.5 μm.

Since the first conductor circuit 8 normally acts as a power supply layer, a ground layer, and the like, it may be in a planar shape or a lattice shape. Further, as the interlayer insulating layer 9,
For example, an adhesive for electroless plating is used. Examples of such an adhesive for electroless plating include various resins having an insulating property. Representative examples of such resins include, for example, epoxy resins and polyimide resins. These resins have the property of being cured by a curing agent, and examples of such a curing agent include an imidazole-based curing agent and an acid anhydride-based curing agent.

It is preferable that heat-resistant resin particles soluble in an acid or an oxidizing agent are dispersed in the interlayer insulating layer 9.
When such heat-resistant resin particles are dispersed in the interlayer insulating layer 9, the surface of the interlayer insulating layer 9 can be roughened, and the adhesive strength between the plating resist 10 and the mounting pad 11 can be increased. Can be.

Examples of the heat-resistant resin particles include resin particles composed of an epoxy resin cured with an amine curing agent, and resin particles composed of an amino resin represented by a melamine resin, a urea resin, a guanamine resin and the like. Is raised.

The heat-resistant resin particles include, for example,
Heat-resistant resin particles having an average particle size of 10 μm or less, aggregated particles having an average particle size of 10 μm or less obtained by aggregating heat-resistant primary resin particles having an average particle size of 2 μm or less,
A mixture of 10 μm heat-resistant resin particles and heat-resistant resin particles having an average particle size of 2 μm or less, having an average particle size of 2 to 10 μm
Pseudo particles obtained by adhering at least one of heat-resistant resin particles having an average particle diameter of 2 μm or less and inorganic particles such as silica, alumina and calcium carbonate to the surface of the heat-resistant resin particles having an average particle diameter of 0.1 to Examples thereof include a mixture of 0.8 μm heat-resistant resin particles and heat-resistant resin particles having an average particle diameter of 0.8 to 2.0 μm. These resin particles exhibit a complicated anchor effect (anchoring effect) with respect to the plating resist 10 and the solder bump forming pad 11, and thus can be suitably used in the present invention.

It is desirable to use a photosensitive resin for the interlayer insulating material 9. When a photosensitive resin is used as described above, a hole for forming a via hole and the like can be easily formed by exposing and developing the photosensitive resin. A typical example of such a photosensitive resin is an epoxy acrylate resin.

The thickness of the interlayer insulating material 9 is not particularly limited, but is usually preferably about 5 to 100 μm.
The surface of the interlayer insulating material 9 is subjected to a surface roughening treatment using an acid, an oxidizing agent, or the like by a conventional method.

The plating resist 10 is not particularly limited as long as it is a commonly used one. The plating resist 10 includes, for example, a composition comprising an epoxy acrylate resin obtained by reacting an epoxy resin with acrylic acid, methacrylic acid and the like and an imidazole-based curing agent; epoxy acrylate resin, polyether sulfone, and imidazole-based Examples of the composition include a curing agent. The thickness of the plating resist 10 is not particularly limited.
It is preferably about 0 μm.

The mounting pad 11 forms a part of the second-layer conductor circuit by a via hole, and is formed by, for example, an electroless plating method. The pad diameter of the mounting pad 11 is set to be larger than the opening diameter of the opening 14A formed in the solder resist layer 14, and therefore, like the alignment marks 13, 130, and 12, the pad diameter of the mounting pad 11 is The periphery is solder resist layer 1.
4 and is covered with the solder resist layer 14. The mounting pad 11 is
For example, it has a shape such as a circle, an oval, and a rectangle, and is formed so that its width is larger than the width of the wiring.
Although the thickness of the mounting pad 11 is not particularly limited, it is usually 5 to 5.
It is preferably 40 μm.

As the solder resist layer 14, for example, a commercially available product can be used as it is. For example, it is preferable to use an acrylate or the like of an epoxy resin, and if necessary, a mixture of a dye or a pigment such as phthalocyanine green may be used. The thickness of the solder resist layer 14 is
Although not particularly limited, for example, it is preferably about 5 to 40 μm.

Next, a method of forming solder bumps on the mounting pads 11 of the printed wiring board 5 configured as described above will be described with reference to FIG. To form solder bumps on the mounting pads 11, first, the printing mask 1 is laminated on the printed wiring board 5. Here, the printing mask 1 will be described with reference to FIG. The printing mask 1 is formed from a metal substrate 2.
An opening (through hole) 3 for solder printing is formed at a position corresponding to each mounting pad 11 on the printed wiring board 5, and the printed wiring board 5 is aligned with the alignment mark 12 on the printed wiring board 5. Alignment marks 4 used for positioning are formed.

The printing mask 1 is not particularly limited, and a conventionally used mask can be used. As a material of the printing mask 1, for example, a nickel alloy,
Nickel-cobalt alloys, metals such as stainless steel; epoxy resins, resins such as polyimide resins, etc.
The present invention is not limited to only such examples. Among these, a nickel alloy, a nickel-cobalt alloy, or the like is preferable in terms of cost, durability, accuracy of the opening, and the like. The thickness of the printing mask 1 is not particularly limited, but is usually about 30 to 150 μm, preferably about 40 μm.
It is desirably about 80 μm. Further, the shape, size, and the like of the opening 3 of the printing mask 1 are not particularly limited and are arbitrary. As an example, for example, a diameter of 100
A circular shape of about 200 μm or the like can be given. The opening 3 of the printing mask 1 can be formed by, for example, an etching method, an additive method, a laser processing method, or the like. Among these methods, the opening 3
The additive method is particularly preferable from the viewpoint of the ability of the cream solder to come off due to the roughness of the cross-sectional shape.

The alignment mark 4 is used for positioning with the printed wiring board 5, and the metal substrate 2
Is usually provided at a position corresponding to the alignment mark 12 provided on the printed wiring board 5. The number of the alignment marks 4 is arbitrary, and the position thereof may be appropriately selected according to the alignment marks 12 of the printed wiring board 5. In the present embodiment, it is formed at a position corresponding to a portion near the outer periphery of the printed wiring board 5 where no conductor pattern is formed.

The alignment mark 4 needs to be a through hole. It is desirable to make the printing mask thinner in order to reduce the amount of solder, but if it is made thinner, it is difficult to half-etch and fill it with resin, and it is more advantageous to provide a through hole and use this as an alignment mark That's why. In the present invention, since the alignment mark 12 of the printed wiring board 5 is formed in a portion near the outer periphery of the printed wiring board and where the conductor pattern is not formed, the alignment mark 13 for mounting the IC chip, Alignment mark for mounting 1
The IC chip 30 can be mounted on an IC chip without being affected.

The through hole can be formed together with the opening 3 when forming the opening 3 in the metal substrate 2, for example. Although the size of the through hole is not particularly limited, for example, the diameter is preferably 0.5 to 1.5 mm, and particularly preferably 0.8 to 1.0 mm.

As described above, when laminating the printing mask 1 on the printed wiring board 5, the laminating method is not particularly limited. For example, as shown in FIG. Is arranged in a cream solder printing machine, the position of the alignment mark 4 formed on the printing mask 1 is recognized by using a CCD camera 20 or the like (FIG. 6A), and then above the printed wiring board 5. To C
The alignment mark 12 formed on the printed wiring board 5 is recognized using the CD camera 20 or the like (FIG. 6B), and the positional deviation between the printing mask 1 and the printed wiring board 5 is corrected. The printing mask 1 is laminated on the printed wiring board 5 so that the respective alignment marks 4 and 12 are aligned (FIG. 6C). In the case of this method, when recognizing the alignment marks 12 formed on the printed wiring board 5, it is desirable that the printed wiring board 5 be suctioned or clamped on a printing stage of a printing machine.

Next, a cream solder 15 is filled in the opening 3 provided in the printing mask 1 as shown in FIG. The cream solder 15 is not particularly limited as long as it is generally used. Representative examples of the cream solder 15 include, for example, Sn63Pb37,
Sn62Pb63Ag2, Sn96.5Ag3.5 and the like.

In the opening 3 provided in the printing mask 1,
After the cream solder 15 is filled, the printing mask 1 is detached from the printed wiring board 5 as shown in FIG.
5 can be printed. After printing is completed,
As shown in (e), the printed cream solder 15 is subjected to a reflow process to form solder bumps 17. Thus, the solder bumps 17 can be formed on the mounting pads 11 of the printed wiring board 5. After the solder bumps 17 are formed in this way, the alignment marks 12 provided on the outer peripheral portion of the printed wiring board where the conductor pattern is not formed are cut and removed by post-processing, and the product portion of the printed wiring board 5 is removed. A is cut into individual substrates C.
Then, a new printed wiring board 5 is set in the cream solder printing machine, and solder bumps 17 are sequentially formed on the mounting pads 11 of the printed wiring board 5 sequentially.

As described above in detail, in the printed wiring board 5 according to the present embodiment, the alignment mark 13 formed for each individual substrate C on the printed wiring board 5 and used for alignment with the IC chip, and The alignment marks 12 formed outside the individual substrates C and used for alignment with the printing mask 1 are moved from the solder resist layer 14 formed on the conductor layer 120 to the conductor layer 1.
When the cream solder 15 is printed on the mounting pad 11 through the printing mask 1, the opening 14 </ b> B exposing only the surface of the mounting pad 20.
In any case where an IC chip is mounted on the opening 14B, the center of the opening 14B may be used as a reference position for positioning.
The solder bumps 17 of an appropriate height can be formed by positioning the IC chip, and the IC chips can be aligned with the solder bumps 17 by the IC chip.
The chip can be appropriately mounted on each individual substrate C.

In the printed wiring board 5, the conductor layers 120 forming the alignment marks 13, 130, 12 are formed.
Since the roughened layer 7 is provided on the surface of the substrate, the adhesion between the alignment marks 13, 130, and 12 and the solder resist layer 14 can be significantly improved.

(Example 1) Next, cream solder was printed on the printed wiring board 5 using the printing mask 1 according to the method shown in FIG. That is, in FIG. 2A, as a printing mask, a metal substrate 2 (340 mm × 255 mm) made of a nickel-cobalt alloy and having a thickness of 50 μm is disposed at a position corresponding to the alignment mark 12 of the printed wiring board 5. A through hole having a diameter of 0.1 mm and a depth of 50 μm was formed, and an opening 3 having a circular shape with a diameter of 100 μm was formed at a position corresponding to the solder bump forming pad 11 of the printed wiring board 5.

The printed wiring board 5 used was a printed wiring board 5 (340 mm × 255 mm) having 30 individual boards C (50 mm × 50 mm) in which conductor circuits were formed in multiple layers by a build-up method. The printed wiring board 5 specifically has the following configuration.
That is, a 20 μm-thick first conductive layer circuit 8 and an interlayer insulating layer 9 having a thickness of 20 μm, which are power supply layers, are formed on an insulating base material 6 made of a bismaleide triazine resin substrate having a thickness of 1 mm.

The interlayer insulating layer 9 is composed of particles 3 having an average particle diameter of 5.5 μm in 70 parts by weight of an epoxy acrylate resin.
It is made of an electroless plating adhesive having a thickness of 50 μm in which epoxy resin particles obtained by mixing 5 parts by weight and 5 parts by weight of particles having an average particle diameter of 0.5 μm are dispersed. It has been removed and roughened. A plating resist 10 made of epoxy acrylate resin and having a thickness of 20 μm is formed on the interlayer insulating layer 9, and a portion where the plating resist is not formed has a diameter of 150 μm which is a part of the second conductive circuit and is connected to an inner layer. Via holes (pads 11 for forming solder bumps), alignment marks 12 for alignment with a printing mask 1 having a thickness of 20 μm and a diameter of 0.1 mm, alignment for alignment between an IC chip and mounting pads A mark 13 and an alignment mark 130 for mounting a printed wiring board packaged by mounting an IC chip on a motherboard are formed by electroless plating.
The top is similarly electrolessly nickel-gold plated.

For the roughened layer 7, an acicular alloy made of copper-nickel-phosphorus is used. As a forming method, copper sulfate 8 g / l, nickel sulfate 0.6 g / l, citric acid 15 g
/ L, sodium hypophosphite 29g / l, boric acid 31g
/ L, a surfactant of 0.1 g / l, and immersed in an electroless plating solution having a pH of 9 to deposit about 3 μm in thickness on alignment marks and the surface of a conductor circuit. The nickel-gold layer was immersed in an electroless nickel plating solution having a pH of 5 consisting of 30 g / l of nickel chloride, 10 g / l of sodium hypophosphite, and 10 g / l of sodium citrate for 20 minutes. A nickel plating layer having a thickness of 5 μm is formed on the substrate.
immersion in an electroless plating solution consisting of 75 g / l of ammonium chloride, 75 g / l of sodium citrate, and 10 g / l of sodium hypophosphite at 93 ° C. for 23 seconds to form a film having a thickness of 0.1 g on the nickel plating layer. A gold plating layer of 03 μm was formed. Further, a solder resist layer 14 having a thickness of 20 μm is formed on the plating resist layer in order to protect portions other than the alignment marks 12 and the pads 11 for forming solder bumps. The alignment marks 12 are provided at two locations 5 mm inward from both ends of one diagonal line of the printed wiring board 5.
1000 pieces are formed on the printed wiring board 5 at an interval of mm. The IC chip mounting alignment marks 13 are provided at two locations 70 mm inward from both ends of the diagonal line for each individual substrate C, and the package mounting alignment marks 130 are provided.
Is 2 mm within 75 mm from both ends of the diagonal line for each individual substrate C.
It is provided in the place.

Next, the printing mask 1 and the printed wiring board 5 are provided in a printing machine, and the alignment marks 4 formed on the printing mask 1 and the alignment marks 12 formed on the printed wiring board 5 are respectively provided. Is recognized using the CCD camera 20, the positions of the printing mask 1 and the printed wiring board 5 are adjusted, and the printed wiring board 5 is aligned so that the alignment marks 4 and 12 thereof are aligned.
After the printing mask 1 is laminated on the opening, as shown in FIG. 2B, the portion after the cream solder is filled in the opening 3 of the printing mask 1, and as shown in FIG. Was separated from the printed wiring board 5 to print the cream solder 15 on the printed wiring board 5.

After the printing was completed, the solder paste was heated at 230 ° C. to make the solder paste 15 into the solder bump 17. The substrate was cut into individual substrates C and subjected to powder removal and cleaning to obtain a semiconductor package substrate (product) of 50 mm × 50 mm.

(Example 2) The product prepared in Example 1
Mount the C chip. The IC chip and the product were mounted on the mounting machine, the alignment mark 13 for mounting the product was read by the CCD camera, and the position coordinates of the center point of the alignment mark were calculated. Next, the alignment mark of the IC chip was read by a CCD camera, and the position coordinates were calculated.
The position of the IC chip and the product was adjusted so that the position coordinates of both alignment marks matched, and the IC chip was mounted, heated, and mounted to form a semiconductor package.

Embodiment 3 A semiconductor package on which an IC chip is mounted is mounted on a motherboard. The semiconductor package and the motherboard of the second embodiment are arranged on a mounting machine, and C
The alignment mark 130 for mounting the product was read by a CD camera, and the position coordinates of the center point of the alignment mark were calculated. Then, align the alignment mark on the motherboard with CC
It was read by a D camera and its position coordinates were calculated. The positions of the motherboard and the package were adjusted so that the position coordinates of both alignment marks matched, and the semiconductor package was mounted, heated, and mounted.

[0060]

As described above, according to the present invention, even when a misalignment occurs between each alignment mark and the opening of the solder resist layer, the printing mask can be aligned with the opening so that it can be properly adjusted. It is possible to form solder bumps of various heights, and the roughening layer can prevent the solder resist from peeling off due to heating or the like. The printed wiring board can be mounted appropriately.

[Brief description of the drawings]

FIG. 1 is a plan view of a printed wiring board.

FIG. 2 is an explanatory diagram continuously showing a series of methods for forming a solder bump on a mounting pad.

FIG. 3 is a cross-sectional view of an alignment mark used for positioning with a printing mask.

FIG. 4 is a cross-sectional view of an alignment mark used for positioning with a printing mask.

FIG. 5 is a cross-sectional view of a printed wiring board prepared by a semi-additive method.

FIG. 6 is a process chart for aligning a printing mask and a printed wiring board;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Printing mask 2 Metal substrate 3 Opening 4 Alignment mark (Printing mask) 5 Printed wiring board 6 Insulating base material 7 Roughened layer 8 First conductive circuit 9 Interlayer insulating layer 10 Plating resist 11 Mounting pad 12, 13 Alignment mark 130 Alignment mark 14 Solder resist layer 15 Cream solder 17 Solder bump 14B Opening

Claims (5)

[Claims] 1. A conductor layer is provided on a substrate, a solder resist layer is formed on the conductor layer, and an opening is formed in the solder resist layer so as to expose only the conductor layer. A printed wiring board in which a portion is used as an alignment mark for positioning, wherein a roughened layer is formed on a surface of the conductor layer. 2. The printed wiring board according to claim 1, wherein the alignment mark is used for alignment with a printing mask. 3. The printed wiring board according to claim 1, wherein the alignment mark is used for positioning the semiconductor element and a mounting pad provided on the printed wiring board when mounting the semiconductor element. 4. The printed wiring board according to claim 1, wherein the alignment mark is used for positioning when a printed wiring board on which the semiconductor element is mounted is mounted on another printed wiring board. 5. The printed wiring board according to claim 1, wherein the roughened layer is made of a copper-nickel-phosphorus needle-like alloy.