JPH11355369A - Demodulation circuit for phase-modulated signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the constitution and to reduce the scale of a phase demodulation circuit prepared for a phase-modulated signal by generating a window signal of prescribed pulse width including the timing corresponding to a fixed cycle of the binary data and performing the level shifting of a demodulated signal when the level transition timing of the phase-modulated signal does not exist in a period when the window signal is generated. SOLUTION: The rise of a two-phase PSK signal B which is produced from the command data is detected by a comparator 101 and a rise pulse generation part 102, and the signal B is turned into a pulse signal G. A clock C of the frequency that is 16 times as much as the repetitive frequency of the signal B is inputted to the part 102. A fall pulse generation part 103 outputs a pulse signal E. The clock C and the signal G are inputted to a rise window generation part 104 where a rise window signal H is generated to show the estimated position of the next rise pulse signal. In the same way, a fall window signal F is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase modulation signal demodulation circuit, and more particularly to a phase modulation (Phase Shift K) circuit.
eying (hereinafter abbreviated as PSK).

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 6, a demodulation circuit of this type includes a band-pass filter 6b for removing noise of a two-phase PSK signal 6a, and an AD converter circuit for converting an analog signal to a digital signal. 6f, a phase-following sampling and holding circuit 6g for outputting 0-degree, 90-degree, 180-degree, and 270-degree signals of the input two-phase PSK signal to the AD converter circuit 6f, and an output from the AD converter circuit 6f. And an arithmetic circuit 6d for calculating the signal and inverting the output signal level by comparing the signal with a reference value. The two-phase PSK signal 6a is a command echo signal obtained by turning a command signal output from a base station to an artificial satellite in the base station.

The operation of the demodulation circuit having such a configuration will be described with reference to FIG. First, the two-phase PSK signal 6
The two-phase PSK signal 6a is input to the band-pass filter 6b in order to remove noise such as a ranging signal component included in a. The signal 6c from which the high-frequency component and the low-frequency component have been removed by the band-pass filter 6b
Input to f. Each point of the signal 6c is a sampling point.

[0006] The reference level (0 V) is set by the AD converter circuit 6 f and the phase tracking sampling and holding circuit 6 g.
0, 90, 180 of the digital signal 6h
Control is performed so as to perform AD conversion for the phase of 270 degrees. Digital data sampled at 0 degrees, 90 degrees, 180 degrees, and 270 degrees of the digital signal 6h output from the AD converter circuit 6f is sequentially input to the arithmetic circuit 6d and operated. When the operation value of the operation circuit 6d exceeds a preset reference value (the value fluctuates according to the level of the two-phase PSK signal and the subcarrier / bit rate ratio), it is considered that the phase has been reversed, and the output signal level Is inverted, and PCM (Pulse Code Modulat
ion), which outputs a two-phase PSK signal 6e.

Further, another conventional demodulation circuit is disclosed in
No. 79050. As shown in FIG. 8, the demodulation circuit described in the publication includes a comparator 2 that converts an input signal 1 that is a two-phase PSK (Binary PSK; hereinafter abbreviated as BPSK) signal into a rectangular wave, A full-wave rectifier circuit 4 and a comparator 6 for demodulating a clock signal 5 from an input signal 1; a 4-bit shift register 8 for reading an output signal 3 of the comparator 2 with an output signal 7 of the comparator 6; (Binary Coded Decimal)
Decoder 10 which receives output signal 9 and converts it to hexadecimal number
And the output signals 11 and 12 of the decoder 10
And a flip-flop 14 for demodulating the CM signal 15.

The operation of the conventional demodulation circuit having such a configuration will be described with reference to FIG. The input signal 1 (FIG. 9B) for the data (FIG. 9A) is
And output as a rectangular wave output signal 3 (c in FIG. 9). The input signal 1 (b in FIG. 9), which is a BPSK signal, passes through the full-wave rectifier circuit 4 that outputs a full-wave rectified signal (d in FIG. 9) and the comparator 6, and becomes a clock signal 7 (e in FIG. 9). Output. Output signal 3 (c in FIG. 9)
Is input to the 4-bit shift register 8 together with the clock signal 7 (e in FIG. 9) and output in hexadecimal 9 (f in FIG. 9).
Is output. When a phase transition point appears in this output signal 9 (f in FIG. 9), "B" (HEX) or "4" (HE
X) is input to the decoder 10 and extracted as an output signal 11 (h in FIG. 9) and an output signal 12 (g in FIG. 9). The output signal 11 (h in FIG. 9) and the output signal 12 (g in FIG. 9) are input to the flip-flop 14 and output as a demodulated signal 15 (i in FIG. 9).

[0007]

Among the above-mentioned prior arts, the former demodulation circuit requires a phase control and an arithmetic operation in a data processing step for demodulating a two-phase PSK modulation signal, so that the circuit is complicated. And there is a disadvantage that the circuit scale becomes large.

Further, the latter demodulation circuit described in the publication requires a full-wave rectification circuit and a comparator for extracting a clock signal, and has a drawback that the circuit scale is increased accordingly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a phase modulation signal demodulation circuit having a simple configuration and without increasing the circuit scale.

[0010]

According to the phase modulation signal demodulation circuit of the present invention, when the data value of the binary data does not change, the pulse changes at a constant cycle, and the phase of the pulse is inverted at a change timing when the data value changes. A phase modulation signal demodulation circuit for demodulating a phase modulation signal for transmitting the binary data and outputting the demodulated signal as a demodulated signal by associating a timing with a window signal having a predetermined pulse width including a timing corresponding to the fixed period. It is characterized by including a window signal generating means for generating, and a demodulating means for performing level transition of the demodulated signal when there is no level transition timing of the phase modulation signal during a period in which the window signal is generated.

In short, the phase modulation signal demodulation circuit generates a window signal having a predetermined pulse width including a timing corresponding to a fixed period of the binary data, and the level transition of the phase modulation signal during a period during which the window signal is generated. When there is no timing, the level of the demodulated signal is shifted.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same reference numerals are given to the same parts as those in the other drawings.

FIG. 1 is a block diagram showing an embodiment of a phase modulation signal demodulation circuit according to the present invention. In the figure, a phase modulation signal demodulation circuit according to the present embodiment has a two-phase P
A comparator 101 provided to obtain a rectangular wave output by comparing the SK signal B with a predetermined reference voltage level, and a D-type flip-flop (DF
F) includes a rising pulse generator 102 for detecting a rising edge, and a falling pulse generator 103 having a circuit 103A and an inverter 103B similar to the rising pulse generator 102.

The rising pulse generator 102 includes DFFs 102A to 102C connected in three stages and a DFF in the second stage.
The NAND circuit 102D receives the output of the DFF 102C and the inverted output of the DFF 102C at the third stage as inputs.

In FIG. 1, the circuit includes a rising window generator 104 for generating a rising window used for detecting a rising timing, and a falling window for generating a falling window used for detecting a falling timing. A window generating unit 105; a rising window generating unit 104 and a falling window generating unit 105;
And a phase detection unit 109 that receives the output of the switching unit 106 as an input and outputs the demodulated signal K.

The rising window generating section 104
When the enable input (ENB) is at low level, DFF
DFF circuit 104A that performs the operation of
16A, a 16-counter 104B that is enabled in response to the output of the selector 04A, a selector 104C whose selected output content is controlled by the output count value, and an output S0 of the 16 outputs S0 to S15 of the selector 104C. , S14, and S15 are output when output. Falling window generator 105 is rising window generator 1
It is assumed that the circuit configuration is the same as that of the circuit 04.

The operation of the rising window generator 104 is shown in FIG. In the figure, the first transition point (transition point) of the pulse signal G output from the rising pulse generator 102 is detected by the DFF circuit 104A, and the 16 counter 104B is operated based on this transition point. Therefore, the output count value of the 16 counter 104 is
"0", "1", ... "14", "15", "0",
"1" is repeated. This output count value is input to the selector 104C. The selector 104C outputs the output terminals S0, S14, S out of the output terminals S0 to S15.
15 is connected to the NOR circuit 104D, so that the rising window signal (@WIN becomes low) only when the output to the connected output terminals is valid.
DOW) is generated. That is, the rising window signal is generated every 16 clocks by the selector 104C.

The phase detecting section 109 is connected to the pulse signal G output from the rising pulse generating section 102 and the switching section 10.
6 and an OR circuit 108 which receives the pulse signal E output from the rising pulse generator 103 and one of the outputs of the switching unit 106 as inputs.
A DFF circuit 109A which is enabled when the signal I output from the OR circuit 107 is at a low level;
A DFF circuit 109B that is enabled when the signal J output from the OR circuit 108 is at a low level;
Output L of F circuit 109A and output M of DFF circuit 109B
, And a T-type flip-flop (TFF) 109D which receives the output N of the AND circuit 109C as an input.

The operation of the phase detector 109 is shown in FIG. In the figure, the output L of the DFF circuit 109A is
Goes high when the signal I is low. Further, the output M of the DFF circuit 109B goes high when the signal J is low. Therefore, only when both the signal I and the signal J are at the low level, the AND circuit 109
The output N of C becomes high level. When the output N goes high, the output level of the TFF 109D is inverted, and the output level of the demodulated signal K is inverted. That is, when a pulse appears in both the signal I and the signal J, the level of the demodulated signal K is inverted assuming that the phase has changed. In addition,
When the output N goes high, the DFF circuits 109A and 109B enter a clear state.

Next, the operation of each unit in FIG. 1 will be described with reference to the time chart in FIG. In the figure, a two-phase PSK signal B generated from command data A becomes a rectangular wave output D by a comparator 101. The square wave output D is input to the rising pulse generator 102, where the rising is detected, and becomes a pulse signal G.

The rising pulse generator 102 has a two-phase PS
A clock C having a repetition frequency 16 times the repetition frequency of the K signal B is input. This clock C is a reference clock used when the command signal output device outputs the two-phase PSK signal B by itself. The rising pulse generator 102 outputs a pulse signal G. Falling pulse generator 103 includes a circuit 103A similar to rising pulse generator 102, and an inverter 1 provided on the input side thereof.
03B. The falling pulse generator 103 outputs a pulse signal E.

The clock C and the pulse signal G are input to the rising window generating section 104, and a rising window signal (@WINDO) indicating a predicted position of the next rising pulse signal is provided.
W) Generate H. Similarly, the falling window generating section 105 to which the clock C and the pulse signal E are input also generates a falling window signal (↓ WINDOW) F indicating the predicted position of the falling pulse signal.

The signal output from the rising window generating section 104 passes through the switching section 106, and initially the OR circuit 10 in the phase detecting section 109 together with the pulse signal G as the signal H.
7 is input. On the other hand, falling window generating section 105
Is output from the phase detector 109 together with the pulse signal E as the signal F at first.
The signal is input to the R circuit 108. The signal I output from the OR circuit 107 and the signal J output from the OR circuit 108 are input to the phase detector 109.

When the pulse signal G is masked in the rising window signal H, the signal I
Is not output. When the pulse signal E is masked in the falling window signal F, the OR circuit 108
Does not output the signal J.

The falling window signal F and the pulse signal E
However, if the pulse signal G is not masked by the rising window signal H (X and Y in the figure), the signal J and the signal I
Become low level sequentially, and the demodulated signal K makes a level transition as the output level of the TFF 109D changes.

As described above, the phase detector 109 performs level transition of the demodulated signal K assuming that the phase has changed when a pulse appears in the signal I and the signal J, and outputs the signal. In response to the level transition of demodulated signal K, switching section 106 switches the connection source between rising window signal H and falling window signal F as indicated by the arrow in FIG.

By the way, the command signal output device outputs a command signal for artificial satellite (control signal for artificial satellite).
A function of performing two-phase PSK modulation on a PCM signal and outputting the result;
It has the function of extracting the PCM signal before the two-phase PSK modulation, comparing and comparing the two-phase PCM-PSK signal with the loopback signal obtained by folding the output two-phase PCM-PSK signal at the antenna end of the ground station. ing. In other words, 2
Since this is a system for inputting and demodulating a loopback signal of a phase PSK signal, there is no need to extract a clock signal from the input two-phase PSK signal, and an internal clock signal possessed by itself is used.

In the phase modulation signal demodulation circuit according to the present embodiment, utilizing the fact that the PSK signal is a signal output by itself, the level of the input two-phase PSK signal is determined by using a reference clock in the device. A change point is predicted, and a two-phase P is calculated using the rule that the next predicted point appears at the predicted point.
The SK signal is demodulated. That is, as shown in FIG. 5, the transition of the level of the command signal always occurs at the timing of the reference signal “1”. That is, since the reference signal is the same and the bit rate is known, the level change point of the two-phase PSK signal can be predicted.

As described above, if the level transition timing can be predicted, the present circuit can be used. For example, the present circuit can be used for a signal passing through a device that does not perform retiming, such as a cable or a buffer amplifier.

In the prior art, the level of a two-phase PSK signal is calculated, the calculated value is accumulated, and a point exceeding a certain reference value is indirectly extracted as a phase change point. This is effective for absorbing a false phase change point due to a fluctuating level and extracting a correct phase change point when the SN ratio (Signal / Noise) of the input signal is poor.

On the other hand, in this circuit, since the two-phase PSK signal input to the command signal generator has a high SN ratio and it is not necessary to absorb the false phase change point in the prior art, the phase change point is directly determined. The method of extraction is used. Two-phase P
Focusing on the rising portion and the falling portion of the SK signal, the next falling portion is at a predictable position with respect to one rising portion, and the rising portion exists at the predicted position after the phase has changed. The same applies to the rising portion. For this reason, this principle is used.

In the above example, the next change point appears every 16 clocks, so the 16 counter is used. However, if the number of clocks is different, the counter corresponding to the number is used. good.

[0033]

As described above, according to the present invention, a two-phase PSK modulation signal transmitted using a transmission line having a high SN ratio is targeted, and a level transition of a demodulated signal is performed while predicting a phase change point. Accordingly, there is an effect that a phase modulation signal demodulation circuit having a simple configuration and without increasing the circuit scale can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a phase modulation signal demodulation circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing an operation of a rising window generator in FIG. 1;

FIG. 3 is a time chart illustrating an operation of a phase detection unit in FIG. 1;

FIG. 4 is a time chart illustrating an operation of the phase modulation signal demodulation circuit of FIG. 1;

FIG. 5 is a diagram showing a relationship between a command signal and a reference signal.

FIG. 6 is a block diagram showing a configuration of a conventional phase modulation signal demodulation circuit.

FIG. 7 is a time chart illustrating the operation of the circuit of FIG. 6;

FIG. 8 is a block diagram showing a configuration of another conventional phase modulation signal demodulation circuit.

FIG. 9 is a time chart illustrating the operation of the circuit of FIG. 8;

[Explanation of symbols]

 Reference Signs List 101 comparator 102 rising pulse generator 103 falling pulse generator 104 rising window generator 105 falling window generator 106 switching unit 107, 108 OR circuit 109 phase detector

Claims (6)

[Claims] When a data value of binary data does not change, a pulse changes in a fixed cycle, and a phase of transmitting the binary data by associating a phase inversion timing of the pulse with a change timing at which the data value changes. A phase modulation signal demodulation circuit for demodulating a modulation signal and outputting the demodulated signal as a demodulated signal, wherein the window signal generation means generates a window signal having a predetermined pulse width including timing corresponding to the predetermined period, and the window signal is generated. And a demodulating means for performing a level transition of the demodulated signal when there is no level transition timing of the phase modulated signal during a period of time. 2. The window signal generating means generates a rising window signal and a falling window signal corresponding to a rising transition and a falling transition of the phase modulation signal, respectively, and the demodulation means generates the rising window signal. When the level transition timing of the phase modulation signal does not exist during the period, the demodulation signal rises and transitions, and when the level transition timing of the phase modulation signal does not exist during the period when the falling window signal is generated, the demodulation signal is generated. 2. A falling transition is performed.
The phase modulation signal demodulation circuit according to any one of the preceding claims. 3. A comparison circuit for comparing the phase modulation signal with a predetermined reference level, a rising detection pulse generating circuit for generating a rising detection pulse corresponding to a rising transition timing of the comparison output, A rising window signal generation circuit for generating the rising window signal after a preset time from the level transition timing of the rising detection pulse, and a falling detection for generating a falling detection pulse corresponding to the falling transition timing of the comparison output 3. The pulse generating circuit according to claim 1, further comprising: a pulse generating circuit; and a falling window signal generating circuit that generates the falling window signal after a preset time from the level transition timing of the falling detection pulse. Phase modulation signal demodulation circuit. 4. The rising window signal generation circuit,
A rising counter for performing a count operation for the preset time in response to a level transition timing of the rising detection pulse, and a circuit for outputting the rising window signal during a period when the count value is a predetermined value A falling counter for performing a count operation for the preset time in response to a level transition timing of the falling detection pulse; and a falling window for a period in which the count value is a predetermined value. 4. The phase modulation signal demodulation circuit according to claim 3, further comprising a circuit for outputting a signal. 5. A rising mask circuit for masking the rising detection pulse using the rising window signal, and a falling mask circuit for masking the falling detection pulse using the falling window signal. 5. The phase modulation signal demodulation circuit according to claim 2, further comprising: a signal transition circuit that transitions the demodulated signal in accordance with an output of the rising mask circuit and an output of the falling mask circuit. 6. A switching circuit for switching between an output destination of the rising window signal generation circuit and an output destination of the falling window signal generation circuit in response to a level transition of the demodulated signal. Item 6. A phase modulation signal demodulation circuit according to any one of Items 1 to 5.