JPH0697971A - Delay detection demodulator - Google Patents

Abstract

PURPOSE:To miniaturize a delay detection demodulator, to lower the power consumption of the delay detection demodulator and to perform more accurate phase discrimination to reception signals relating to the delay detection demodulator used in a mobile radio communication system, for instance. CONSTITUTION:In the delay detection demodulator provided with a delay detection part 1 and a data discrimination part 2 for discriminating a difference part and outputting demodulated data, a frequency conversion means 3a for multiplying the local signals of an (n) phase generated by using the local signals of a frequency fL to be impressed and the reception signals of the frequency fIF and taking out the frequency conversion signals of the (n) phase by the frequency (fL-fIF) to be outputted is provided. Phase numbers are assigned beforehand to all states which the output of the frequency conversion means 3a can obtain and a phase discrimination means 4 for outputting the corresponding phase number as the phase data of the reception signals of the frequency fIF to the delay detection part is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential detection demodulator used in a mobile communication system, for example.

[0002] Fig. 10 is an example of a receiver configuration diagram for a mobile communication system. As shown in the figure, a received signal input through an antenna is amplified and frequency converted by a high frequency section 51 to obtain an intermediate frequency band ( Hereinafter, after being converted into a reception signal of the IF band), the IF band amplification section 52 further applies amplification / limitation to the baseband section (demodulator) 53.

A demodulator 53 demodulates an input received signal to extract a baseband signal and delays it using a signal delayed by one symbol and a signal not delayed by using a reproduction clock applied in a delay detection section (not shown). After detection, determination is made and demodulated data is extracted.

The bit timing recovery (BTR) 54
Is to extract the reproduction clock from the differentially detected signal and add it to the above-mentioned differential detection part. Here, in mobile communication systems, the power consumption of mobile station equipment is being reduced, but in response to this, it is necessary to reduce the size and power consumption of the differential detection demodulator (the demodulator part in Fig. 10) as well. There is.

[0005]

2. Description of the Related Art FIG. 11 is an explanatory diagram of a conventional phase difference detection method.
(a) is the first detection method, and (2) is the second detection method.

Generally, in a mobile communication system, in order to compensate for a drop in incoming call level due to fading,
As described above, the received signal in the IF band may be subjected to a limiter to form a constant envelope. Since the constant enveloped IF band received signal can be treated as binary data, digital processing can be performed in a stage subsequent to the limiter.

Now, in FIG. 11 (a), an exclusive OR of the IF band received signal and a clock having a frequency substantially equal to the frequency of the IF band received signal is used to obtain the IF band received signal and the clock. Phase information is extracted by detecting the phase difference component and counting the value of this phase difference component with a counter (not shown).

Further, in FIG. 11 (b), a counter (not shown) starts counting operation from the initial state at the rising edge of the IF band received signal and counts the number of high speed pulses, but when the rising edge of the reproduction clock is applied, The count value at this point is latched. As a result, the phase difference between the IF band received signal and the recovered clock can be known.

[0009]

Generally, on the transmitting side, a band limiting filter is used to limit the spread of the spectrum, but the phase characteristic of this filter changes as the distance from the center frequency increases. Phases other than () are not guaranteed.

That is, as shown in FIGS. 11 (a) and 11 (b), counting a certain time width means judging by looking at the change in the time direction of data having a certain width, and the received signal There are more errors than when the phase is determined at one point.

On the other hand, if the IF band frequency is increased, the time width required for data determination is shortened and the amount of error is reduced, but the sampling clock becomes faster and power consumption increases.

In other words, a counter and a power source portion having a large power supply are required, which makes it difficult to reduce the size and power consumption. Further, there are two problems that an error becomes large when the phase of the received signal is judged.

An object of the present invention is to reduce the size and power consumption of a differential detection demodulator and to enable more accurate phase determination for a received signal.

[0014]

FIG. 1 is a block diagram showing the principle of the first and second aspects of the present invention. In the figure, 1 is a differential detection portion for obtaining the difference between the input phase data and the phase data one symbol before, 2 is a data discrimination portion for discriminating the difference and outputting demodulation data, 3a is a local oscillation signal of frequency f _L A frequency conversion means for frequency-converting a reception signal of frequency f _IF using an n-phase local oscillation signal generated by using, and extracting and outputting an n-phase frequency conversion signal at frequency (f _L −f _IF ). Is.

[0015] 3b by using the local oscillation signal of the n / 2 phase generated by using the local oscillation signal of a frequency f _L, and frequency conversion of the received signal in the frequency f _IF, the frequency - in (f _L f _IF) It is a frequency conversion means for extracting and outputting the normal output and the inverted output of the frequency converted signal of the n / 2 phase.

Reference numeral 4 designates a phase number in advance for all possible states of the output of the frequency conversion means, and when the output of the frequency conversion means is applied, the corresponding phase number is assigned to the received signal of the frequency f _IF . The phase determining means outputs the phase data to the differential detection section.

[0017]

In the first aspect of the present invention, the frequency converting means generates the n-phase local oscillator signal by using the applied local oscillator signal of the frequency f _L. Then, when the n-phase local oscillator signal and the received signal of frequency f _IF are multiplied, a multiplied signal of cos (2π f _IF + φ) × cos [2π f _L + K (2π / n)] is obtained. Is passed through a low-pass filter that passes the frequency difference component, the harmonic component is cut off, and a frequency-converted signal of cos [2π (f _L −f _IF ) + φ + K (2π / n)] is obtained. Note that f _IF is the center frequency of the intermediate frequency band.

Therefore, as shown below, a number (this is called a phase number) is given to the phase conversion for this frequency conversion signal.

[0019]

[Table 1] Here, since the outputs of 0 to K to (n-1) have the same frequency and are only out of phase, it is possible to select only one that becomes positive → negative near the data point. Now, if the selected phase number is K, cos [2π (f _L − f _IF ) ＋ φ−K (2π / n)] = 0 at the data point, and φ at this time is φ = K (2π / n) + Π / 2−2π (f _L −f _IF ) = K (2π / n) + a.

Here, a = π / 2−2π (f _L −f _IF ), but since it is a constant value and is considered as an offset value, the received signal of the frequency f _IF when the resolution of one cycle is n It becomes the phase itself. Therefore, the demodulated data can be obtained by the differential detection unit and the data determination unit using the phase number.

The second aspect of the present invention is different from the first aspect of the present invention.
An n / 2 phase local oscillator signal is generated using the applied local oscillator signal of frequency f _L. Then, in the same manner as above, a frequency-converted signal is obtained by multiplying the n / 2-phase (n is an even number at this time) local oscillation signal and the reception signal of frequency f _IF and passing through the low-pass filter. However, a phase number is given to this signal as follows.

[0022]

[Table 2] Now, the phase number at which the output changes from positive to negative near the data point is
If K, then φ = K (2π / n) + a.

Since the signal is looking at the sign of the frequency-converted signal, the duty ratio is 50%, and when the output changes from negative to positive at a point near the data, the phase shifts by π. Therefore, φ = K (2π / n) + π + a. The phase number at this time is K + n / 2.

In the third aspect of the present invention, since the output of the limiter can be treated as a binary value, if a digitized local oscillator signal is prepared as the local oscillator signal, it can be realized by exclusive OR instead of multiplication.

According to the fourth aspect of the present invention, if a digital filter having the same cutoff frequency is used as the low-pass filter for passing the frequency difference component in the frequency-converted signal, it can be entirely constructed by a digital circuit.

That is, since the phase number closest to the change point of the recovered clock is determined as the phase of the received signal of the frequency f _IF , that is, the phase is determined by the data of one point, the determination error is reduced and the counter etc. Since it is unnecessary, the size and power consumption can be reduced.

[0027]

2 is a block diagram of a first embodiment of the present invention (frequency conversion means: analog processing, phase determination means: ROM), FIG. 3 is an explanatory view of the frequency conversion means of FIG. 2, FIG. 2 is a diagram for explaining the operation of FIG. 2, FIG. 5 is an example of the all-digital configuration diagram of FIG. 2, FIG. 6 is a diagram for explaining the operation of FIG. 5, and FIG. 7 is a diagram of the configuration of the second embodiment of the present invention (frequency conversion means: (Analog processing, phase determination means: in the case of ROM), FIG. 8 is a block diagram when the filter part in FIG. 7 is replaced by a digital filter, and FIG. 9 is a block diagram of an all digitalized differential detection demodulator to which the present invention is applied. Is an example.

The reference numerals on the left side of FIG. 3 are the same as those on the first line of FIG. 4, and the reference numerals on the digital filter output side and the AND gate output side in FIG. 5 are the first row in FIG. Is the same as the code. In addition, the same reference numerals denote the same objects throughout the drawings. Hereinafter, assuming that n = 8, the operation of FIG. 2 will be described with reference to FIGS. 3 and 4.

The phase shifter 31 of FIG. 2 is composed of, for example, seven delay elements connected in series, and the applied frequency
The local oscillator signal of f _L is (360 /
8) Frequency converter 320 with corresponding phase shift
Added to ~ 327. The received signal of frequency f _IF is also input to the corresponding frequency converter.

Therefore, since the frequency conversion signals having the frequencies such as the sum and difference of the frequencies f _L and f _IF from the frequency converters 320 to 327 are added to the corresponding low-pass filters 330 to 337, the frequency conversion signals from these filters are transmitted. Only the component (f _L −f _IF ) is taken out and added to the ROM in the phase determination means 4 as an address.

Here, the "f _IF received signal" in FIG. 3 is a binarized received signal because the limiter is applied as described above. Further, as shown in FIG. 4, since the codes of the outputs of the low-pass filters 330 to 337 are applied as addresses to the ROM, the phase numbers corresponding to all the applied addresses are stored as a table. .

Therefore, the output of the low-pass filter (that is,
When the ROM address is "00011110" (marked with * in Fig. 4), the ROM outputs the phase number of "5" to flip-flop-1 (
Hereafter, it will be abbreviated as FF ₁ ), so if the recovered clock is input while this phase number is being applied, the phase number of "5" will be fetched into FF ₁ . That is, when the reproduced clock is input to FF ₁ , the applied phase number is captured as the phase number closest to the change point of the reproduced clock.

Next, the operation of FIG. 5 will be described with reference to FIG. 6. In FIG. 5, the frequency conversion means and the phase determination means shown in FIG. 2 are all digitalized and have the same function. The phase shifter 34 in FIG. 5 is composed of, for example, a 7-stage shift register, and the applied local oscillator signal (pulse train) of the frequency f _L is an 8-phase local oscillator signal (the amount of phase shift is the same as in FIG. 2). ) And send it to exclusive OR gates (hereinafter abbreviated as EX-OR gates) 350 to 357.

Since the received signal of the frequency f _IF is also added to this gate, these signals are subjected to exclusive OR by the corresponding EX-OR gates, and then the difference component is taken out by the digital filter. At this time, as shown in the line marked with * in "Frequency conversion part" of FIG.
For example, assume that "00011110" is output from the 367 (same as in FIG. 2).

Then, as shown in FIG. 5, the logical product of the output of the adjacent digital filters and the output of the digital filters is obtained by exclusive-ORing the outputs of the adjacent digital filters with EX-OR gates 410-417. Taken at ~ 427, "0010000" is obtained as shown in "AND gate output" in the line marked with * in FIG.

Further, the logical sum of these AND gate outputs is
When taken by the OR gates 431 to 433, "101" (5 in decimal) is applied to FF ₂ as shown in "OR gate output" in the line marked with * in FIG. At this time, it is taken in by the added reproduction clock.

Here, the phase determination means in FIG. 6 is constructed so as to completely match the function of the ROM in FIG. Further, although the digital filter is used to extract the difference component in FIG. 5, the same result can be obtained by using the analog filters having the same characteristics.

Further, the phase shifter 34 of FIG. 7 has three delay elements, and the phase is shifted by (360/8) degrees each time the local oscillation signal of the frequency f _L passes through one delay element. It is converted to a 4-phase local oscillator signal and added to the corresponding frequency converters 350 to 353.

On the other hand, since the received signal of the frequency f _IF is also added to the corresponding frequency converters 350 to 353, the four-phase frequency converted signals are obtained, and the corresponding low pass filters are obtained.
The frequency (f _L − f _IF ) component is extracted from 360 to 363.
(Corresponding to LPF output 0 to 3 in Fig. 2).

Here, the four-phase frequency-converted signals are phase-shifted by π in the corresponding inverters INV ₁ to INV ₄ and the frequency (f _L −f _IF ) is generated in the corresponding low-pass filters 364 to 367.
Of the LPF output 4-7 of FIG.
It corresponds to. After that, the address is
Added to ROM.

Further, FIG. 8 is a diagram in which the low-pass filter of FIG. 7 is constituted by digital filters 370 to 377, and the function is the same as that of FIG. FIG. 9 is a block diagram of a fully digitalized differential detection demodulator, which comprises a frequency conversion means 3a, a phase determination means 4, a differential detection portion 1 and a data determination portion 2, but the frequency conversion means and the phase determination means. Since the operation of is described in detail above, the description thereof will be omitted, and the operation of the rest will be described. Note that n = 8.

3-bit phase data is applied to the corresponding FF ₂ (there are 3) from the OR gate of the phase determination means, but the phase when the rising point of the recovered clock from the bit timing recovery (BTR) is added The number, eg "101", is captured in FF ₂ .

Then, "101" is applied to the subtraction part 12 in the differential detection part 1, and the phase number one time slot before, for example, "100", is also applied to this part via the FF 12. Therefore, the subtraction result of "010" is added to the data discriminating portion 2. Therefore, the data discrimination part is
10 "is discriminated and the corresponding data is sent as demodulation data.

[0044]

As described in detail above, according to the present invention, it is possible to reduce the size and power consumption of a differential detection demodulator and to make more accurate phase determination for a received signal. There is an effect to say.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of first and second aspects of the present invention.

FIG. 2 is a configuration diagram of a first embodiment of the present invention (frequency conversion means: analog processing, phase determination means: ROM).

FIG. 3 is an operation explanatory diagram of the frequency conversion unit in FIG.

FIG. 4 is an operation explanatory diagram of FIG. 2;

FIG. 5 is an example of an all-digital structure diagram of FIG.

FIG. 6 is an operation explanatory diagram of FIG. 5;

FIG. 7 is a configuration diagram of a second embodiment of the present invention (in the case of frequency conversion means: analog processing, phase determination means: ROM).

FIG. 8 is a configuration diagram when the filter portion in FIG. 7 is replaced with a digital filter.

FIG. 9 is an example of a configuration diagram of an all-digitalized differential detection demodulator to which the present invention is applied.

FIG. 10 is an example of a receiver configuration diagram for a mobile communication system.

FIG. 11 is an explanatory diagram of a conventional phase difference detection method, in which (a) is a first detection method and (2) is a second detection method.

[Explanation of symbols]

1 Delay detection part 2 Data determination part 3a, 3b Frequency conversion means 4 Phase determination means

Claims (4)

[Claims] 1. A delay having a differential detection portion (1) for obtaining a difference between input phase data and phase data one symbol before, and a data discrimination portion (2) for discriminating the difference and outputting demodulated data. in detection demodulator (n is a positive integer) n phase generated by using the local oscillation signal of frequency f _L with local oscillation signal of, by frequency converting the received signal frequency f _IF, the frequency (f _L -F _IF ), the frequency conversion means (3a) for extracting and outputting the n-phase frequency conversion signal and all the states that the output of the frequency conversion means can have are assigned phase numbers in advance, A differential detection demodulator, characterized in that, when the output of the conversion means is applied, a phase determination means (4) for outputting the corresponding phase number as phase data of the received signal of frequency f _{IF to} the differential detection part is provided. 2. In the differential detection demodulator, the received signal of frequency f _IF is frequency-converted by using the local oscillation signal of n / 2 phase generated by using the local oscillation signal of frequency f _L , and the frequency ( f _L −f _IF ), the frequency conversion means (3b) for extracting and outputting the normal output and the inverted output of the frequency conversion signal of the n / 2 phase and the phase determination means (4) are provided. Differential detection demodulator. 3. The differential detection demodulator according to claim 1, wherein a digital signal having a frequency f _L is used as the local oscillation signal, and frequency conversion is performed using an exclusive OR portion. 4. The differential detection demodulator according to claim 1 or 2, wherein a digital filter is used when an n-phase frequency conversion signal is taken out at the frequency (f _L −f _IF ).