JP2520495B2 - Demodulator - Google Patents

Description

TECHNICAL FIELD The present invention relates to a demodulator for demodulating an FSK (frequency shift) modulated signal, and more particularly to a demodulator of a differential detection type by digital signal processing. .

[Prior Art] Conventionally, a differential detection method is known as one of methods for performing demodulation processing of an FSK-modulated signal by digital signal processing. This method will be described below using mathematical expressions.

When the input signal is A · cos (ωt), the signal delayed by T seconds can be expressed by the following equation (1).

A · cos {ω (t−T)} (1) Multiplying these two signals gives the following.

Here, the first term is a function that is uniquely determined by the delay amount T and the angular frequency ω, and the second term is 2 of the angular frequency of the input signal.
It is a function of double the angular frequency.

Here, if the signal of the second term of the equation (2) is removed by the low-pass filter, the equation (2) can be regarded as a function of only ωT shown in the first term. Therefore, as shown in FIG. 4, an intermediate frequency f ₀ between the _two frequencies f ₁ and f ₂ to be determined.
If the value of the first term is set to 0, the function F of the first term is a function of only the angular frequency ω, and therefore the determination can be made only by determining the sign of the output signal of the low pass filter. Easy to do.

FIG. 5 shows the configuration of a demodulation circuit based on the differential detection method described above.

The FSK modulation signal input to the input terminal 1 of the demodulator is A
The data is converted into digital data by the / D converter 2 at regular time intervals (τ seconds). FS converted to the digital data
The K-modulated signal is directly input to one input terminal of the multiplier 3 and, after being delayed by the delay buffer 4 having an appropriate delay amount T that is an integral multiple of τ seconds, is input to the other input of the multiplier 3. Entered on the edge. The multiplier 3 multiplies the FSK modulated signal converted into the digital data by the signal delayed by T seconds in the delay buffer 4. The output signal of the multiplier 3 is input to the low-pass filter 5, the second term component of the above-described equation (2) is removed, and then input to the determiner 6.
Here, the delay amount T of the delay buffer 4 is determined so that the output signal of the low-pass filter 5 becomes zero at the intermediate frequency between the two carrier frequencies of FSK modulation. Therefore, the decision unit 6 extracts the code of the output signal of the low-pass filter 5 and outputs it as the demodulation result to the output terminal 7.

[Problems to be Solved by the Invention] By the way, in a modulation / demodulation device in which one modulation / demodulation device has a plurality of data transfer rates, one demodulation process is often performed by one digital signal processing LSI for cost reduction. Things have been done.

In such a case, the timing clock given to the digital signal LSI is often set in accordance with the fastest modulation / demodulation processing. In this case, the A / D conversion process is performed according to such a high-speed timing clock.

However, in the FSK demodulator using the differential detection method described above, the delay amount T of the delay buffer is set by the timing clock. Therefore, when the timing clock is determined only in terms of the data transfer rate, it is optimal. There is a problem that the delay amount T does not become an integral multiple of the A / D conversion rate and cannot be applied to demodulation processing of various speeds.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a differential detection type demodulation device capable of performing demodulation processing at various speeds regardless of the frequency of the timing clock. .

[Means for Solving the Problem] A demodulator according to the present invention is a demodulator that demodulates a signal that has been frequency-shift-modulated by digital signal processing.
An A / D converter that converts an input analog signal into digital data, a plurality of delay buffers that delay the digital data output from this A / D converter with mutually different delay amounts, and output data of the plurality of delay buffers A plurality of multipliers that perform multiplication with digital data output from the A / D converter, a plurality of low-pass filters that extract low-frequency components from the multiplication results of the plurality of multipliers, and a plurality of the low-pass filters And a determination means for determining and outputting a demodulated signal based on the output data of.

[Operation] According to the present invention, demodulation is performed by multiplying outputs from a plurality of delay buffers having different delay amounts or different delay outputs from a shift buffer with digital modulation data, and determining low frequency components thereof. Since the result is obtained, the correct demodulation result can be obtained by referring to the plurality of calculation results even if the optimum delay amount cannot be set due to the timing clock.

Embodiments Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an FSK demodulator of the differential detection system according to an embodiment of the present invention.

The FSK modulation signal input from the input terminal 11 is input to the A / D converter 12 and converted into digital data here. This digital data is input to the plurality of multipliers 14a, 14b, 14c, and also to the shift buffer 13 that performs a shift process every τ seconds. Here, the buffers 13a, 13b, 13c, and 13d are τ, 7τ, 18τ, and 36τ, respectively.
Outputs digital data delayed by seconds. Multiplier 14a
Multiplies the FSK modulation signal converted into the digital data by the output data of the buffer 13b delayed by 7τ seconds by the shift buffer 13. The multiplier 14b converts the FSK modulation signal converted into the digital data and the shift buffer 13 into 18
The output data of the buffer 13c delayed by τ seconds is multiplied. Further, the multiplier 14c multiplies the FSK modulated signal converted into the digital data by the output data of the buffer 13d delayed by 36τ seconds in the shift buffer 13.

The output data of the multipliers 14a, 14b, 14c are input to the low pass filters 15a, 15b, 15c, respectively, and the high frequency components are removed. The output data of these low-pass filters 15a, 15b, 15c are input to the determiner 16. The judgment device 16 inputs 3
A code is extracted from one piece of data, and the result determined by the combination thereof is output as demodulated data to the output terminal 17.

Next, the operation of the demodulation device according to this embodiment having the above configuration will be described with reference to FIG.

Here, τ second is set to 1/7200 seconds, the signal frequencies f ₁ and f ₂ to be detected are 1650 Hz and 1850 Hz, respectively, and the intermediate frequency f _0.
Will be described as an example when the frequency is set to 1800 Hz.

Fig. 2 shows the delay amount of the input signal in three ways T ₁ (36 × 1/7200
Second), T ₂ (18 × 1/7200 seconds), T ₃ (7 × / 7200 seconds) delayed input signals are multiplied by the undelayed input signal, and low-pass filters 15a, 15b, 15c FIG. 7 is a graph diagram showing output signals passing through as frequency functions Fa, Fb, and Fc.

Here, the signal frequencies f ₁ (1650 Hz) and f ₂ (18
The function that the output signal of the low-pass filters 15a, 15b, 15c becomes 0 at the signal frequency f ₀ (1800Hz) just in the middle of 50Hz is F
a (delay amount T ₁ ; 36 × 1/7200 seconds) only, but in the case of the function Fa, the signal frequencies f ₁ (1650 Hz) and f ₂ (1850H) to be detected
Also in z), the output signal of the low-pass filter 15a becomes 0, so it is impossible to determine f ₁ and f ₂ only by the function Fa.

Therefore, the determiner 16 uses the function Fb (delay amount T ₂ ; 18 × 1/7200
Second) and function Fc (delay amount T ₃ ; 7 × 7200 seconds) are added, and the following determination is made based on the combination of the signs of the function values of the functions Fa, Fb, and Fc.

When the function values of the functions Fb and Fc are positive, it is determined that the input signal is a signal having the f ₁ frequency.

When the function values of the functions Fb and Fc are negative, it is determined that the input signal has the f ₂ frequency.

If the function value of the function Fb is negative and the function value of the function Fc is positive, if the function value of the function Fa is negative, it is determined that the input signal is a signal having the f ₁ frequency, and it is positive. For example, the input signal is determined to be a signal having the f ₂ frequency.

When the function value of the function Fb is positive and the function value of the function Fc is negative, it is determined that the input signal is a signal having the f ₂ frequency.

By making such a determination, an accurate demodulation result can be obtained even when the optimum delay amount cannot be obtained by the timing clock.

FIG. 3 is a block diagram showing an example of the decision unit 16 that performs the above-described decision processing.

Function values Fa, Fb, Fc from the low pass filters 15a, 15b, 15c
Are stored in buffers 21, 22 and 23 respectively, and their sign bit 2
4,25,26 are taken out respectively. Sign bit 24 is AND gate 31
And NAND gates 32 are input to one of the input terminals, and the sign bits 25 and 26 are AND gates 28 and 30 and NAND gates 27 and 29, respectively.
Has been entered in. The output of the AND gate 30 is input to the other input terminal of the AND gate 31 and the NAND gate 32. AND
The outputs of the gates 28 and 31 are input to the OR gate 33, and the output thereof is output to the output terminal 17. Also, NAND gate
The outputs of 27, 29, 32 are input to the OR gate 34.

The determination operation described above is performed by the determiner 16, and a demodulation output can be obtained at the output terminal 17 and an inverted demodulation output can be obtained at the output terminal 17a.

In the above embodiment, a plurality of delay outputs are taken out from one shift buffer, but a plurality of delay outputs may be taken out from a plurality of delay buffers having different delay amounts.

Further, in the determination by the combination of the codes of the determiner, if the delay amount of the delay buffer changes, the waveform of the function of FIG. 2 also changes,
As a result, the combination of codes may change, but even in that case, it is clear that the effect of the present invention can be obtained by making an appropriate determination.

[Effects of the Invention] As described above, according to the present invention, even when an appropriate delay amount cannot be obtained due to the timing clock, the determination is performed based on a plurality of delay outputs, so that an accurate result can be obtained. A demodulation output can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an FSK demodulator according to an embodiment of the present invention, FIG. 2 is a graph of frequency vs. output value of a low-pass filter in the same, and FIG. 3 is a detailed block diagram of a decision unit in the same Figures and 4 show the conventional FSK of the differential detection system.
FIG. 5 is a graph for explaining the operation of the demodulator, and FIG. 5 is a block diagram of the demodulator. 1,11; Input terminal, 2,12; A / D converter, 3,14a, 14b, 14c;
Multiplier, 4; delay buffer, 5, 15a, 15b, 15c; low-pass filter, 6, 16; decision device, 7, 17; output terminal, 13; shift buffer, 13a, 13b, 13c, 13d; buffer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Momose 1-403-3, Kosugi-cho, Nakahara-ku, Kawasaki City, Kanagawa Prefecture NEC IC Microcomputer System Co., Ltd. (56) Reference JP-A-56-140706 (JP, A) JP-A-61-39753 (JP, A)

Claims (3)

(57) [Claims] Claim: What is claimed is: 1. A demodulator for demodulating a signal subjected to frequency shift modulation by digital signal processing, comprising: an A / D converter for converting an input analog signal into digital data; and digital data output from the A / D converter. Multiple delay buffers that delay with different delays,
A plurality of multipliers for multiplying the output data of the plurality of delay buffers and the digital data output from the A / D converter, and a plurality of low-pass components that respectively extract low-frequency components from the multiplication results of the plurality of multipliers. A demodulation device comprising: a filter; and a determination unit that determines and outputs a demodulation signal based on output data of the plurality of low-pass filters. 2. A demodulator for demodulating a signal that has undergone frequency shift modulation by digital signal processing, wherein an A / D converter for converting an input analog signal into digital data and digital data output from this A / D converter are provided. A shift buffer for sequentially delaying, a plurality of multipliers for multiplying a plurality of delayed output data from the shift buffer and digital data output from the A / D converter, and a multiplication result of the plurality of multipliers, respectively. A demodulation device comprising: a plurality of low-pass filters for extracting low-frequency components; and a determination means for determining and outputting a demodulated signal based on output data of the plurality of low-pass filters. 3. The determination means comprises a gate circuit that determines the demodulated signal based on the signs of the outputs of the plurality of low pass filters.
Or the demodulation device according to 2.