JPH0621983A - Fsk demodulation circuit - Google Patents

Abstract

PURPOSE:To reduce the distortion of a waveform detected by a band-pass filter or the like and to remarkably reduce the processing amount by executing the delay detection without the frequency shift of an input FSK signal. CONSTITUTION:The input FSK signal F is inputted to multiplier circuits 3 and 6 and to a delay circuit 1. The output of the delay circuit 1 is inputted to a multiplier circuit 4 and to a delay circuit 2. Further, the output of the delay circuit 2 is inputted to a multiplier circuit 5. Coefficients 8-10 are inputted to the other input of the multiplier circuits 3-5, and the results of the multiplication are inputted in an adder circuit 7. The adder circuit 7 adds the multiplication result of the multiplier circuits 3-5 and inputs an addition signal A being the result of the addition to the other input of the circuit 6. The multiplier circuit 6 executes the multiplication for the delay detection between the input FSK signal F and the addition signal A, that is, the detection multiplication, outputting a detection output D. A low-pass filter 11 eliminates the frequency component which is the double of the input FSK signal F by the detection multiplication included in the detection output D and outputs it as demodulation output OD.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FSK demodulation circuit,
In particular, it relates to an FSK demodulation circuit using digital signal processing of an analog line modem.

[0002]

2. Description of the Related Art Conventionally, a differential detection system has been widely used as an FSK demodulation circuit. In the differential detection method, an input signal and a delayed signal obtained by delaying the input signal for a predetermined time are multiplied, and a low-pass filter removes a frequency component that is twice the frequency of the delayed signal, thereby performing FFSK demodulation.

Assuming that the input signal is A.sin2.pi.ft and the delay time is T, the result of the multiplication is a component that does not change with time and a signal component that is twice the input signal, as shown in the following equation. Become.

[0004]

Of these, the second term is removed by the low-pass filter, so that the output finally becomes the following expression.

[0006]

Here, the delay time T is set to 1/4 cycle of the center frequency f0 of FSK, and the frequency is f0 and this f0.
If the input frequency is less than f0, the output will be positive, and if it exceeds f0, the output will be negative. Can be demodulated.

[0008]

Conventionally, the FSK demodulation circuit using the differential detection method using digital signal processing is limited to an integral multiple of the sampling period because the delay time that can be realized by the digital signal processing is limited to the following method. Delay detection was performed. First, the frequency of the input signal is shifted by multiplying the input signal by a sine wave having an appropriate frequency and removing unnecessary frequency components by a bandpass filter. Then, the center frequency of the FSK is input to the input. In this case, the quarter cycle of the frequency after the shift corresponds to an integral multiple of the sampling cycle.

A conventional FS for performing the differential detection as described above.
As shown in FIG. 2, the K demodulation circuit includes a multiplication circuit 3, a sine wave generator 14, a bandpass filter 15, a delay circuit 1 for delaying one sampling, and a multiplication circuit 6.
And a low-pass filter 11.

Next, the operation of the conventional FSK demodulation circuit will be described.

First, the input FSK signal F is multiplied by the sine wave S generated by the sine wave generator 14 by the multiplication circuit 3. As a result of this multiplication, the input FSK is output to the output of the multiplication circuit 3.
The frequency component fD of the difference between the frequency of the signal F and the frequency of the sine wave S and the frequency component fA of the sum are output. In the sine wave generator 14, the input FSK signal F has a center frequency f of FSK.
When 0 is input, frequency component fD and frequency component f
A sine wave whose frequency is equal to the delay time of the delay circuit 1 is generated in a quarter of one of the periods A. Next, the band pass filter 15 extracts only the necessary frequency component, and the delay circuit 1, the multiplication circuit 6, and the low pass filter 11 perform the above-mentioned differential detection.

[0013]

DISCLOSURE OF THE INVENTION The conventional FSK described above
Since the demodulation circuit shifts the frequency of the input signal to a frequency suitable for differential detection, the input signal is multiplied by a sine wave and unnecessary frequency components are removed by a bandpass filter. There are drawbacks in that distortion due to the characteristics of the bandpass filter is received and the processing amount increases.

[0014]

In the FSK demodulation circuit of the present invention, the output after differential detection is set to 0 at the center frequency of the FSK filter coefficient, and the output is output at a frequency lower than the center frequency and a frequency higher than the center frequency. Is provided with a finite impulse response filter whose sign is different from each other and whose absolute values are the same and whose gain is set to 1 at the center frequency.

[0015]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the FSK demodulation circuit of the present invention.

As shown in FIG. 1, the FSK demodulation circuit of this embodiment includes delay circuits 1 and 2 for delaying an input signal by one sampling, multiplication circuits 3 to 6, and multiplication circuits 3 to 6, respectively. Adder circuit 7 for adding outputs, and multiplier circuit 3
.About.6 for each coefficient 8-10 and low pass filter 1
1 and 1.

Next, the operation of this embodiment will be described.

First, the input FSK signal F is supplied to the multiplication circuit 3,
6 and the delay circuit 1 respectively. Also,
The output of the delay circuit 1 is input to the multiplication circuit 4 and the delay circuit 2, respectively. Further, the output of the delay circuit 2 is input to the multiplication circuit 5. Coefficients 8 to 10 are input to the other inputs of the multiplication circuits 3 to 5, and the multiplication results are input to the addition circuit 7. The addition circuit 7 adds the multiplication results of the multiplication circuits 3 to 5 and inputs the addition signal A, which is the addition result, to the other input of the multiplication circuit 6. The multiplication circuit 6 executes multiplication for differential detection of the input FSK signal F and the addition signal A, that is, detection multiplication, and outputs a detection output D. The low-pass filter 11 removes the frequency component of the input FSK signal F doubled by the detection multiplication included in the detection output D, and outputs it as a demodulation output OD.

Here, the delay circuits 1 and 2, the multiplication circuits 3 to 5, the addition circuit 7, and the coefficients 8 to 10 constitute a well-known finite impulse response (FIR) filter. The method of determining the coefficients 8 to 10 will be described below.

The input FSK signal F is given by A · sin2πft,
When the sampling period is T and the values of the coefficients 8 to 10 are a, b, and c, the demodulation output OD is given by the following equation.

[0022]

The condition under which the normal operation of the differential detection is possible is that the demodulation output OD is 0 at the center frequency f0 of FSK.
That is, the sign (polarity) is different on the frequency f1 side lower than the center frequency f0 and on the high frequency f1 side, and the absolute values are the same. Furthermore, at the center frequency f0, F
When the gain of the IR filter is set to 1, the simultaneous linear equations shown in the following equation (4) are obtained.

[0024]

The simultaneous equations of the equation (4) can be easily solved, and the differential detection can be performed by setting the solution to each value of the coefficients 8 to 10.

[0026]

As described above, since the FSK demodulation circuit of the present invention can perform the differential detection without shifting the frequency of the input FSK signal, the distortion of the detected waveform due to the bandpass filter or the like can be reduced and processed. This has the effect of significantly reducing the amount.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an FSK demodulation circuit of the present invention.

FIG. 2 is a block diagram showing an example of a conventional FSK demodulation circuit.

[Explanation of symbols]

 1, 2 delay circuit 3-6 multiplication circuit 8-10 coefficient 11 low-pass filter 14 sine wave generator 15 band-pass filter

Claims (2)

[Claims] 1. A filter coefficient is set such that the output after differential detection is 0 at the center frequency of FSK, and the outputs have mutually different signs and have the same absolute value at a frequency lower than the center frequency and a frequency higher than the center frequency. And a delay circuit having a finite impulse response filter set such that the gain is 1 at the center frequency. 2. The finite impulse response filter is first
The second input is delayed by 1 sampling to the input signal of
A first delay circuit for outputting a signal; and a second delay circuit for delaying the second input signal by one sampling.
A second delay circuit that outputs three input signals; a first delay circuit that forms the first input signal and the filter coefficient
Multiply with the coefficient of and output the first multiplication result
And a second input signal forming the second input signal and the filter coefficient.
The second multiplication result and the second multiplication result are output
A third multiplier forming the third input signal and the filter coefficient
Multiply with the coefficient of and output the third multiplication result
And the first to third multiplication results are added, and the addition result is output.
The FS according to claim 1, further comprising an adder.
K demodulation circuit.