JPH05183593A - Delay detection circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for a delay element and to reduce power consumption by using a sample-and-hold circuit so as to detect a phase difference between two adjacent symbols thereby applying delay detection. CONSTITUTION:An intermediate frequency signal of a received biphase PSK modulation wave is converted into a square signal by a limiter amplifier 4 and fed to an edge detection section 5. A 1st sample-and-hold circuit 8 samples and holds a sawtooth wave signal of the same period as that of the intermediate frequency signal generated by a sawtooth wave generator 6 to detect a phase of the reception signal. A 2nd sample-and-hold circuit 9 samples and holds the detected signal based on a symbol timing signal SCK delayed by one symbol. A subtractor circuit 10 subtracts output signals of the circuits 8, 9 to detect a phase difference of two adjacent symbols. An identification circuit 12 identifies an output signal of the subtractor circuit 10 by using the symbol timing signal SCK to output reproduced data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential detection circuit, and more particularly to a differential detection circuit used in a two-phase PSK demodulator.

With the diversification of information services in recent years, digitization of communication has become indispensable, and this tendency also extends to the field of mobile communication. In digital mobile communication,
Since it is necessary to function normally even in a poor propagation environment with fading and the like, it is required to develop a technology suitable for mobile communication.

2 which is one of the modulation methods of digital communication
As a demodulation method corresponding to the phase PSK modulation method, synchronous detection is used in fixed station communication such as satellite communication. Synchronous detection is excellent in static characteristics (when there is no fading), but in an environment where reception is intermittently interrupted by high-speed fading, carrier recovery becomes difficult and demodulation characteristics deteriorate significantly, so mobile communication Not suitable for. Therefore, as a PSK demodulation method, differential detection that does not require carrier recovery is considered to be promising.

[0004]

2. Description of the Related Art FIG. 6 shows a conventional differential detection circuit. The operation principle of this circuit will be described below in the case of two-phase PSK.

First, on the modulation side (not shown), the data string X _i to be sent is differentially encoded (the data before 1 bit is summed to obtain a transmission bit), and the converted data string is Y.
_{If i} , then Y _i = Y _i-1 + X _i (1). Using Y _i as a modulation signal, the phase of the carrier wave is set to “0”, corresponding to “0” and “1” of Y _i .
The signal is transmitted by changing it to "π". This modulated wave is expressed by the following equation.

R (t) = COS (ω _C t + Y _i π) (2) where ω _C is the carrier frequency.

Then, the modulated wave is received by the antenna 1.
The local frequency ω of the local oscillator 3 _LAnd the multiplier (Miki
Output from the multiplier 2
Intermediate frequency (hereinafter also referred to as IF) signal after frequency conversion
No. is L (t) = COS {(ω_C−ω_L) T + Y_iπ)} (3). The formula (3) is converted into one symbol of the data by the delay element 21.
The signal delayed by the time T is as follows.

L (t−T) = COS {(ω _C −ω _L ) (t−T) + Y _i−1 π)} (4)

Therefore, when the equations (3) and (4) are multiplied by the multiplier 22 and the low frequency component is extracted by the low pass filter 23, D = L (t) × L (t−T) = 1 / _{2 × COS {(ω C -ω} L) T + (Y i -Y i-1) π} = 1/2 × COS {(ω C -ω L) T + X i π} (5) is obtained.

Here, if ω _L and one symbol time T are set by the timing reproduction circuit 24 so as to satisfy (ω _C −ω _L ) T = 2nπ (n is a natural number) (6), the equation (5) becomes D = 1/2 × COS (X _i π) (7) The output signal of the low-pass filter 23 is identified for each symbol by the timing signal of the equation (7).
By determining positive as “1” and negative as “0”, the original data string X _i is reproduced.

[0011]

In such a conventional differential detection circuit, when the delay element 21 is composed of a shift register, the delay line has a clock frequency of about 16 times the IF frequency input to the demodulator. (If the IF frequency is
Since it operates at about 7.28MHz at 455kHz, there was a problem that it consumed power that cannot be ignored by portable devices.

Therefore, an object of the present invention is to provide a differential detection circuit which can reduce power consumption without using a delay element.

[0013]

In order to achieve the above object, in the differential detection circuit according to the present invention, as shown in principle in FIG. 1, the intermediate frequency signal of the received two-phase PSK modulated wave is converted into a square wave. A limiter amplifier 4 for converting and amplifying a signal, an edge detector 5 for extracting only the rising edge of the square wave signal, and a sawtooth wave generator 6 for generating a sawtooth wave signal having a cycle according to the frequency of the intermediate frequency signal. And sample the sawtooth signal with the rising edge.
First to hold and detect the phase of received signal as voltage
Between the sample-and-hold circuit 8 and the second sample-and-hold circuit 9 that further samples and holds the sample-and-held signal with a timing signal delayed by one symbol, and the output signals of both the sample-and-hold circuits 8 and 9. The subtraction circuit 10 that detects the phase difference between two adjacent symbols by performing the subtraction at 1, the timing reproduction circuit 11 that generates the symbol timing signal synchronized with the output signal of the subtraction circuit 10, and the output of the subtraction circuit 10. And a discrimination circuit 12 for discriminating a signal by the timing signal and outputting reproduced data.

In the present invention, as shown by the dotted line in FIG. 1, an automatic frequency control circuit 13 for adjusting the frequency of the sawtooth wave generator 6 from the output signal of the limiter amplifier 4 may be provided.

[0015]

In the differential detection circuit of the present invention shown in FIG. 1,
The received intermediate frequency signal of the two-phase PSK modulated wave R (t) is converted into a square wave signal by the limiter amplifier 4, amplified and sent to the edge detecting section 5, where the rising edge of the square wave signal is generated. Only edges are fetched.

On the other hand, the sawtooth signal having the period 1 / (ω _C −ω _L ) (the period at the frequency of the intermediate frequency signal) generated by the sawtooth generator 6 is generated by the first sample and hold circuit 8. The rising edge from the edge detection unit 5 is sampled and held as a sampling command, and the phase of the received signal is detected as a voltage at the output.

The output signal of the first sample and hold circuit 8 is further sampled and held by the second sample and hold circuit 9 for each symbol timing signal SCK. Then, by subtracting the output signals of the first and second sample-and-holds 8 and 9 from each other by the subtraction circuit 10, a voltage corresponding to the phase difference between two adjacent symbols is detected in the subtraction result, and this is detected. Reproduction data can be output by making a determination for each symbol by the identification circuit 12. The timing signal S delayed by one symbol is used.
CK is generated by the timing reproduction circuit (STR) 11 from the output signal of the subtraction circuit 10.

As a result, a delay element which has conventionally operated at about 7.28 MHz (when the IF frequency is 455 kHz) can be used, for example.
Sample that operates at about 10kHz (symbol clock)
It can be replaced with a hold circuit, and low power consumption can be achieved.

In the present invention, the limiter amplifier 4 is provided with an automatic frequency control circuit 13 as shown by the dotted line in FIG.
By adjusting the frequency of the sawtooth wave generator 6 according to the output signal of, the deterioration of the demodulation characteristics due to the frequency shift is reduced.

[0020]

FIG. 2 shows an embodiment of a differential detection circuit according to the present invention, which is applied to a two-phase PSK differential detection circuit. The intermediate frequency signal shown in FIG. (IF signal), as is well known, antenna 1
By multiplying the two-phase PSK modulated wave R (t) of the carrier frequency ω _C received by the mixer 2 with the local signal of the frequency ω _L from the local oscillator 3, the frequency ω _C −
It is obtained as an intermediate frequency signal of ω _L.

Further, the edge detecting section 5 includes a capacitor C1.
And a resistor r1 and a comparator 52 connected in series to the differentiator 51,
Both edges of the square wave signal from the limiter amplifier 4 are detected by the differentiating circuit 51, and the comparator extracts only the rising edge thereof.

A buffer amplifier 7 is inserted on the output side of the sawtooth wave generator 6, and the first sample and hold circuit 8 connected to this buffer amplifier 7 and controlled by the output signal of the comparator 52 It is composed of an analog switch 81 and a hold circuit 82 including a capacitor C2 that holds the output voltage of the analog switch 81 and a high input impedance amplifier 82A.

Therefore, the analog switch 81 has a very short time O due to the rising edge from the comparator 51.
It is set to N and the capacitor C2 is charged to a voltage equal to the output voltage from the amplifier 7. Immediately after that, the analog switch 81 is turned off to hold the voltage in the capacitor C2, and when the next sampling command comes, it is charged toward the new voltage in the same manner and then held.

Similarly, the second sample and hold circuit 9 also comprises an analog switch 91 and a hold circuit 92 having a capacitor C3 for holding the output voltage of the analog switch 91 and a high input impedance amplifier 92A.

Further, the subtraction circuit 10 has input resistors r2 and r connected to the sample and hold circuits 8 and 9, respectively.
3 and the feedback resistors r4 and r5 for each of them, and the resistors r2 to r2.
The values of r5 are set equal to each other.

Therefore, when "0" is sent from the transmitting side to the output of the subtraction circuit 10, a voltage corresponding to 0 or ± 2π (a voltage corresponding to the phase difference between two adjacent symbols) is output, and the signal is transmitted. When "1" is sent from the side, a voltage corresponding to ± π (a voltage corresponding to the phase difference between two adjacent symbols) is output (see FIG. 3).

The identification circuit 12 further includes four comparators 1 for comparing the output signal of the subtraction circuit 10 with respective threshold values.
21 to 124, an AND gate 127 for inputting a signal obtained by inverting the output signal of the comparator 121 by the inverter 125 and an output signal of the comparator 122, and a signal obtained by inverting the output signal of the comparator 123 by the inverter 126 and the comparator 124. AN to input output signal
D gate 128, AND gate 129 which inputs AND gates 127 and 128, and AND gate 129
The output signal is output as the data by the timing signal SCK from the timing reproduction circuit 11, and the reproduced data is output by the D-FF (flip-flop) 130.

Therefore, in the discrimination circuit 12, the subtraction circuit 10
A comparator 12 to identify the five value voltages from
The four threshold voltages 1 to 124 (see FIG. 3) are utilized to identify each symbol according to the truth table of FIG. 4 and reproduce the data.

FIG. 5 shows an embodiment in which an automatic frequency control (AFC) circuit 13 is added to the differential detection circuit according to the embodiment of FIG. 2, and in this embodiment, the output signal of the limiter amplifier 4 is frequency discrimination. The frequency fluctuation of the IF signal supplied to the converter 131 is converted into a voltage, and a low pass filter (LP
F) 132 averaged. And filter 1
The output signal of 32 further changes the slope of the voltage change by the amplifier 133, and AFC is performed on the sawtooth wave generator 6 so that the frequency of the sawtooth wave is changed by the amplifier output.
I am hanging. Therefore, if there is a frequency difference between the output of the mixer 2 and the output of the sawtooth wave generator 6, the demodulation characteristic will be deteriorated.
The two frequencies are matched.

[0030]

As described above, according to the differential detection circuit of the present invention, the sawtooth wave having the same period as the IF frequency of the receiver is sampled and held by the received IF signal of the two-phase PSK modulated wave, and Since the sample-and-hold signal itself and the sample-and-hold signal delayed by one symbol are subtracted, the phase difference between two adjacent symbols is detected and differential detection is performed. The required delay element can be replaced with a slower sample and hold circuit, and power consumption can be reduced.

Further, by providing an automatic frequency control circuit for matching the IF frequency and the frequency of the sawtooth wave, it is possible to prevent the demodulation characteristic from being deteriorated due to the frequency difference between the two.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing in principle the configuration of a differential detection circuit according to the present invention.

FIG. 2 is a circuit diagram showing an embodiment of a differential detection circuit according to the present invention.

FIG. 3 is a diagram showing a relationship between a subtraction output and a discrimination result in the embodiment of FIG.

4 is a diagram showing a relationship between a comparator output and an identification result in the embodiment of FIG.

FIG. 5 is a circuit diagram showing another embodiment in which the differential detection circuit according to the present invention is used in a two-phase PSK differential detection circuit.

FIG. 6 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 4 Limiter amplifier 5 Edge detection unit 6 Sawtooth wave generator 8, 9 Sample and hold circuit 10 Subtractor circuit 11 Timing recovery circuit 12 Discrimination circuit 13 Automatic frequency control circuit

Claims (2)

[Claims] 1. A limiter amplifier (4) for converting an intermediate frequency signal of a received two-phase PSK modulated wave into a square wave signal for amplification.
An edge detection unit (5) for extracting only the rising edge of the square wave signal, a sawtooth wave generator (6) for generating a sawtooth wave signal having a cycle according to the frequency of the intermediate frequency signal, and the rising edge. A sample-and-hold circuit (8) that samples and holds the sawtooth wave signal to detect the phase of the received signal as a voltage, and a sample signal that is delayed by one symbol from the sampled and held signal. Second to hold
Sample and hold circuit (9), a subtraction circuit (10) for detecting the phase difference between two adjacent symbols by performing subtraction between the output signals of both sample and hold circuits (9), and the subtraction circuit A timing reproduction circuit (11) for generating a symbol timing signal synchronized with the output signal of (10) and an identification circuit (12) for outputting the reproduction data by identifying the output signal of the subtraction circuit (10) by the timing signal. And a differential detection circuit comprising: 2. The automatic frequency control circuit (13) for adjusting the frequency of the sawtooth wave generator (6) from the output signal of the limiter amplifier (4), as claimed in claim 1. Delay detection circuit.