JPH0870332A - Clock reproduction device - Google Patents

Abstract

PURPOSE: To perform clock reproduction not influenced by the operation of a waveform equalization circuit. CONSTITUTION: An A/D converter 1 samples QAM signals at the timing of clocks from a clock oscillator 25 and first and second multipliers 3 and 5 quasi- synchronously orthogonally detect the output of the A/D converter 1 by detection signals from a local oscillator 7 and a π/2 phase shifter 9 and obtain I signals and Q signals. A first LPF 11 excludes a high band component from the I signals and a first square computing element 13 squares the output. A second LPF 15 excludes the high band component from the Q signals and a second square computing element 17 squares the output. An adder 19 adds the output of the first and second square computing elements 13 and 17 and extracts a clock frequency. A phase error detection circuit 21 detects an error corresponding to a clock frequency deviation and a phase deviation at the time of sampling from the output of the adder 19 and a D/A converter 23 replaces the amount of the error with the strength of analog signals. The clock oscillator 25 converts an oscillation frequency fs corresponding to signal strength from the D/A converter 23. The clocks generated in the clock oscillator 25 also become system clocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, in multilevel QAM (Quadrature Amplitude Modulation) demodulation used in the fields of broadcasting and communication, determines the timing required for demodulating data by QAM.
A clock recovery device for extracting from a signal.

[0002]

2. Description of the Related Art In recent years, studies on high-efficiency coding techniques and digital transmission systems have been conducted. Above all, the digital TV broadcasting using the multilevel QAM (Quadrature Amplitude Modulation) system is CAT
Practical tests and studies have been conducted mainly on V, and it is expected to be the key to future digital transmission.

FIG. 8 shows a conventional multilevel QAM demodulation circuit. The synchronous detection circuit 101 performs synchronous quadrature detection on the QAM signal and outputs an I signal. The synchronous detection circuit 103 performs synchronous quadrature detection on the QAM signal and outputs a Q signal. Multi-value judgment circuit 11
1 receives the I signal, performs multi-valued determination, and outputs the determination result in the form of parallel data. The multi-level determination circuit 113 receives the Q signal, performs multi-level determination, and outputs the determination result in the form of parallel data. The parallel-serial conversion circuit 115 converts the parallel data output from the multi-level determination circuits 111 and 113 into serial data and outputs it as demodulated data.

Further, the carrier recovery circuit 105 receives the I signal and the Q signal output from the synchronous detection circuits 101 and 103, reproduces a reference carrier required for performing synchronous detection, and reproduces the reproduced reference carrier. It is supplied to the synchronous detection circuit 101 directly and to the synchronous detection circuit 103 via a π / 2 phase shifter 107.
The clock reproduction circuit 109 receives the I signal from the synchronous detection circuit 101 and outputs a reproduction clock signal.

However, considering the reception of digital TV broadcasting, it is common to perform waveform equalization before synchronous demodulation. In that case, the demodulation circuit has a structure of synchronous detection circuits 101 and 103 as shown in FIG. The waveform equalization circuit 117 is arranged in the previous stage.

The waveform equalization circuit 117 is also a clock recovery circuit.
It operates in synchronization with the clock signal reproduced in 109. When the waveform equalization circuit 117 and the clock recovery circuit 109 are arranged before and after the synchronous detection circuits 101 and 103 and the carrier recovery circuit 105, since the waveform equalization circuit 117 changes the amplitude and phase of the QAM signal, the clock The reproduction circuit 109 may not be able to accurately reproduce the clock. That is, in the case of a demodulation circuit that reproduces a clock using the output signal of the waveform equalization circuit 117, there is a possibility that a phase difference between the reproduced clock and the phase of the QAM signal input to the demodulation circuit may occur. is there. If the reproduced clock has a phase shift, normal waveform equalization of the input signal cannot be expected even in the waveform equalization circuit. As a result, the synchronous detection by the synchronous detection circuits 101 and 103 cannot be normally performed. If synchronous detection cannot be performed, clock recovery cannot be performed.

As described above, the conventional clock recovery circuit 10
9 has a drawback that it does not operate normally when waveform equalization is performed.

[0008]

DISCLOSURE OF INVENTION Problems to be Solved by the Invention The arrangement of the clock recovery circuit in the conventional demodulation circuit cannot normally demodulate when waveform equalization is considered. However, in order to perform better digital demodulation, the waveform equalizer circuit is indispensable in the demodulator circuit.

Therefore, it is an object of the present invention to provide a clock reproducing device which reproduces a clock without being influenced by the operation of the waveform equalizing circuit.

[0010]

In a clock reproducing apparatus for multilevel QAM demodulation, quadrature detecting means for quasi-coherently detecting an input QAM signal to obtain an I-axis signal and a Q-axis signal, and I from the quadrature detecting means. First to shape the spectrum of the axis signal
Low-pass filter, a second low-pass filter that shapes the spectrum of the Q-axis signal from the quadrature detection means, and a first calculation means that squares the output of the first low-pass filter, A second arithmetic means for squaring the output of the second low-pass filter; an adder means for summing the outputs of the first and second arithmetic means to extract a clock component; A phase error detecting means for detecting a clock phase error from the output and a clock oscillating means for changing the oscillation frequency according to the output from the phase error detecting means are provided.

[0011]

Before being input to the waveform equalizing circuit and the phase synchronizing circuit, the input QAM signal is quasi-coherently detected by the quadrature detecting means and becomes an I signal and a Q signal. The spectrum of the I signal and the Q signal is shaped by the first and second low-pass filters, respectively. The outputs of the first and second low pass filters are squared by the first and second computing means, respectively.

The adding means adds the outputs of the first and second calculating means to extract a clock component. The phase error detecting means detects the clock phase error from the output of the adding means.
The clock oscillating means changes the oscillation frequency according to the clock phase error from the phase error detecting means and generates a clock signal.

Since the clock reproduction device does not depend on the output of the waveform equalization circuit, it can reproduce a stable clock that is not affected by the operation of the waveform equalization circuit.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, FIG. 2 shows a demodulation circuit using the clock recovery device of the present invention. The input QAM signal is sampled by the analog-digital (A / D) converter 1 and converted into a digital signal. The first multiplier 3
A digital signal is quasi-coherently detected by a detection signal having a frequency generated by the local oscillator 7 to obtain an I signal. The second multiplier 5 quasi-coherently detects the digital signal by the detection signal from the local oscillator 7 supplied via the π / 2 phase shifter 9 to obtain the Q signal. The I signal and the Q signal are respectively the third
The low-pass filter (LPF) 33 and the fourth low-pass filter (LPF) 35 of (3) extract the low-pass components. The waveform equalization circuit 37 performs waveform equalization on the outputs of the first and second low pass filters 33 and 35. Phase synchronization circuit 39
Outputs the demodulated signal by phase-locking the output of the waveform equalization circuit 37.

Next, the configuration of the clock recovery device of the present invention will be described with reference to FIG. This clock recovery device uses a part of the demodulation circuit of FIG. 2 as a constituent element.
The input QAM signal is sampled by the A / D converter 1 at the timing of the clock from the clock oscillator 25 and converted into a digital signal. The first multiplier 3
The I signal is obtained by quasi-coherent detection of the digital signal by the detection signal having the frequency (f _o + Δf) generated by the local oscillator 7. The second multiplier 5 quasi-coherently detects the digital signal by the detection signal from the local oscillator 7 supplied via the π / 2 phase shifter 9 to obtain the Q signal. In this way, the detected signals supplied to the first and second multipliers 3 and 5 are out of phase with each other by π / 2 in frequency, so that the QAM signal is quadrature detected. First low pass filter (LP
F) 11 removes a high frequency component from the I signal from the first multiplier 3. The second low pass filter (LPF) 15 is
The high frequency component is removed from the Q signal from the second multiplier 5.

The operation of the above-mentioned quadrature detection and filter will be described with reference to FIG. FIG. 3A is an example of a power spectrum of the input QAM signal found in the signal immediately after being sampled by the A / D converter 1. Spectrum
Reference numeral 43 is a folded component of the spectrum 41 generated by sampling. The spectrum 41 is distributed around the carrier frequency f _o , and the spectrum 43 is symmetrical to the spectrum 41 about f _s / 2 when the sampling rate is f _s . Each spectrum is spread with a width of approximately the clock frequency f _c .

The first and second multipliers 3 and 5 perform quasi-synchronous quadrature detection on this signal according to the frequency (f _o + Δf) generated by the local oscillator 7. As a result, the power spectrum of the entire signal becomes as shown in FIG. Spectra 41 that was in the vicinity of the frequency f _o before quasi-synchronous quadrature detection is frequency shift in the vicinity of DC, distributed as shown in the spectrum 45. Along with that, the spectrum 43 of FIG. 3A also moves to the position of 47, and the whole has the spectrum distribution shown by 45 and 47 in FIG. 3B.

Here, since the spectrum 47 interferes with the extraction of the clock component in the subsequent processing, it is necessary to remove it. Therefore, the first and second low pass filters (L
The spectrum 47 is removed by PF) 11 and 15. First
And the second low-pass filter (LPF) 11 and 15 is half the clock frequency f _c in the input QAM signal f _c
It suffices if the characteristics have a frequency of / 2 in the pass band and the spectrum 47 is in the stop band.
It is a filter having a low-pass characteristic of the cutoff frequency f _c shown in (c).

The output of the first low pass filter 11 is the first
Is squared by the square calculator 13 of. The output of the second low pass filter 15 is squared by the second squaring calculator 17. The adder 19 includes first and second squaring operators 13 and 17
And outputs the clock frequency f _c to extract the clock frequency f _c .

The phase error detection circuit 21 detects from the output of the adder 19 an error corresponding to the clock frequency shift and the phase shift at the time of sampling. The D / A converter 23 replaces the amount of error from the phase error detection circuit 21 with the strength of the analog signal. The clock oscillator 25 receives the output of the D / A converter 23 and changes the oscillation frequency f _s in proportion to the signal strength thereof. The clock from this clock oscillator 25 is
It becomes the sampling clock of the / D converter 1 and the system clock. By configuring the feedback loop in this way and changing the oscillation frequency, the input QA
The clock frequency of the M signal and the oscillation frequency of the clock oscillator 25 are synchronized with each other, and the clock can be reproduced.

The clock extraction circuit shown in FIG. 2 has the first and second low pass filters 11 and 15 and the first and second low pass filters shown in FIG.
Square calculators 13 and 17, adder 19 and phase error detection circuit 21
Consists of

FIG. 4 shows a first concrete example of the phase error detection circuit 21. Signal 51 is the output of adder 19 of FIG. The input 51 is delayed by one clock time by the first delay circuit 53 and further delayed by one clock time by the second delay circuit 55. The arithmetic mean circuit 57 calculates the arithmetic mean between the input signal 51 and the output of the second delay circuit 55. The first subtractor 59 subtracts the output of the averaging circuit 57 from the output of the first delay circuit 53. The second difference unit 61 includes a second delay circuit 55.
The input signal 51 is subtracted from the output of. First sign inversion circuit
63 outputs the output of the first difference unit 59 as it is when the output of the second difference unit 61 is positive, and inverts the output of the first difference unit 59 when the output of the second difference unit 61 is negative. Then, it is output and used as a clock phase error signal.

The operation of the phase error detection circuit shown in FIG. 4 will be described with reference to FIG. FIG. 5A shows an example in which the sampling frequency of the A / D converter 1 is high with respect to the input QAM signal. The timing indicated by a triangle in the figure is the input Q
The sampling timing is synchronized with the AM signal,
The timing indicated by X is the timing at which the actual sampling is performed. The phase error detection circuit 21 can hold the input sample value by the first and second delay circuits 53 and 54, and the values are A, B and C in the order of input.

In the phase error detection circuit 21, the arithmetic mean circuit 57 calculates the arithmetic mean of A and C. The value of this arithmetic mean value is calculated as line 65
Indicate. At this time, there is a difference between the value of B and the addition average value 65, and the difference Δφ becomes the output of the first difference unit 59. Here, as can be seen from the figure, the reproduction clock frequency is high and A <C
In case of, Δφ becomes negative. Under the same conditions, Δφ is positive when A> C. This is clear from the fact that the state of A> C is equalization to, for example, the state in which FIG. Therefore, in order to output the error of the same sign regardless of the magnitude of A and C, the positive / negative of A-C is checked by the second difference unit 61, and accordingly the first
The sign inverting circuit 63 of FIG. That is, for example, if Δφ is used as the output of the first sign inverting circuit 63 when A−C> 0, then −Δφ obtained by inverting the sign of Δφ when A−C <0 is used as the first sign inverting circuit. 63 output.

Further, FIG. 5B shows an example in which the sampling frequency of the A / D converter 1 is low with respect to the input QAM signal. Similar to FIG. 4A, the symbol Δ indicates the sampling timing synchronized with the input QAM signal, and the symbol X indicates the timing at which the actual sampling is performed. The phase error detection circuit 21 converts the input sample value into the first and second delay circuits 53
And 54 can hold values, which are A, B, C in order of input.

The arithmetic mean circuit 27 calculates the arithmetic mean of A and C. The value of this arithmetic mean value is shown by the line segment 67. There is a difference between the arithmetic mean value 67 and the sample value B, which is Δφ
As shown in FIG. 5, it appears with a sign opposite to that of FIG. In this way, the sign of Δφ is reversed when the number of reproduced clock waveforms is high and when the number of reproduced clock waveforms is low, so the output of the phase error detection circuit 21 reflects the clock frequency deviation and phase deviation of the reproduced clock.

The output of the first differentiator 59 sees the positive / negative of A-C by the second differentiator 61 as in the case of FIG. The sign inversion circuit 63 corrects the sign of Δφ, and outputs it as the output of the phase error detection circuit 21.

FIG. 6 shows a second specific example of the phase error detection circuit 21. Signal 71 is the output of adder 19 of FIG. The input signal 71 is delayed by one clock time by the third delay circuit 73. The third differentiator 75 subtracts the input signal 71 from the output of the third delay circuit 73. The fourth delay circuit 77 delays the output of the third difference unit 75 by one clock time. Fourth
The differencer 79 of subtracts the output of the third differencer 75 from the output of the fourth delay circuit 77. The fifth delay circuit 83 delays the output of the fourth difference unit 79 by one clock time. The sixth delay circuit 85 delays the output of the fifth delay circuit 83 by one clock time. The fifth difference unit 87 subtracts the output of the fourth difference unit 79 from the output of the sixth delay circuit 85. The second sign inversion circuit 89 outputs the output B of the fifth delay circuit 83 as it is when the output of the fifth difference device 87 is positive, and the fifth difference device 87 outputs the output B as it is.
When the output of is negative, the output of the output B of the fifth delay circuit 83 is inverted and output, and is used as the clock phase error signal.

The operation of the phase error detection circuit shown in FIG. 6 will be described with reference to FIG. The waveform of the input signal 71, which is the clock component, is shown in FIG. 7A, and the values sampled so that the sampling period is a quarter of the period of the input signal 71 are indicated by black dots. The waveform of the output of the third difference unit 75 is shown in FIG. Further, the waveform of the output of the fourth differencer 79 is as shown in FIG.
Is. By taking the difference between the sample values twice in this way, the sampling timing and the symbol timing of the input QAM signal when the reproduced clock is phase-synchronized with the input QAM signal can be matched. The sample values A, B and C on the difference waveform are held by the fifth and sixth delay circuits 83 and 85, and the value of B is output as a phase error, but the second sign inversion circuit 89 When the output of the differentiator 87 is negative, the sign of B is inverted.

That is, as shown in FIG. 7C, the value A,
When B and C are A <C, the second sign inversion circuit 89
The value is output as it is, but when A> C, the sign is inverted and output as -B. This is necessary to prevent the output of the phase error having the opposite sign due to the sample value input to the phase error detection circuit 21 even if the clock frequency shift or the phase shift is unknown as described above. In addition to the sign inversion, a condition that zero is output when A and C have the same sign or the same value may be added.

Further, considering that the demodulation circuit to which the clock recovery circuit of the present invention is applied includes the waveform equalization circuit 37 as shown in FIG. 2, the input QA in the A / D converter 1 is considered.
It is also possible that the waveform equalization circuit 37 compensates for a sampling phase error that occurs when the M signal is sampled. At this time, the fourth delay circuit 77 surrounded by the dotted line 81 in FIG.
And the part of the fourth differencer 79 is removed, and the third differencer 75
It is also conceivable to supply the output of the above to the fifth delay circuit 83 and the fifth difference unit 87. The waveform equalization circuit 37 removes the phase error between the sampling timing by the reproduced clock and the symbol timing of the input QAM signal generated at this time.

[0032]

As described above, according to the present invention, since the clock is reproduced from the signal before the phase synchronization processing, the stable clock reproduction can be performed without being influenced by the output of the phase synchronization circuit or the waveform equalization circuit. I can.

[Brief description of drawings]

FIG. 1 is a diagram showing a clock recovery device of the present invention.

FIG. 2 is a multilevel QAM using the clock recovery device of the present invention.
It is a figure which shows a demodulation circuit.

FIG. 3 is a waveform diagram for explaining the operation of the clock recovery device of the present invention.

FIG. 4 is a first specific example of the phase error detection circuit of the clock recovery device of the present invention.

5 is a waveform diagram for explaining the operation of the phase error detection circuit in FIG.

FIG. 6 is a second specific example of the phase error detection circuit of the clock recovery device of the present invention.

FIG. 7 is a waveform diagram for explaining the operation of the phase error detection circuit of FIG.

FIG. 8 is a diagram showing a conventional multilevel QAM demodulation circuit.

FIG. 9 is a diagram showing a conventional multilevel QAM demodulation circuit.

[Explanation of symbols]

1 ... Analog-digital (A / D) converter, 3 ... 1st
, 5 ... Second multiplier, 7 ... Local oscillator, 9 ... π
1/2 phase shifter, 11 ... First low-pass filter (LPF),
13 ... 1st square arithmetic unit, 15 ... 2nd low pass filter (LPF), 17 ... 2nd square arithmetic unit, 19 ... Adder, 21 ...
Phase error detection circuit, 23 ... Digital-analog (D /
A) converter, 25 ... clock oscillator, 31 ... clock extraction circuit, 33 ... third low-pass filter (LPF), 35 ... fourth
Low pass filter (LPF), 37 ... Waveform equalization circuit, 39
... phase synchronization circuit, 53 ... first delay circuit, 55 ... second delay circuit, 57 ... arithmetic mean circuit, 59 ... first difference device, 61 ... second
Differentiator, 63 ... First sign inversion circuit, 73 ... Third delay circuit, 75 ... Third differencer, 77 ... Fourth delay circuit, 79 ... Fourth
Differentiator, 83 ... Fifth delay circuit, 85 ... Sixth delay circuit,
87 ... Fifth differencer, 89 ... Second sign inversion circuit.

Claims (4)

[Claims] 1. A multi-level QAM demodulation clock recovery device, wherein quadrature detection means for quasi-coherently detecting an input QAM signal to obtain an I-axis signal and a Q-axis signal, and a spectrum of the I-axis signal from the quadrature detection means. A first low-pass filter that shapes the signal, a second low-pass filter that shapes the spectrum of the Q-axis signal from the quadrature detector, and a first square that squares the output of the first low-pass filter. Calculating means, second calculating means for squaring the output of the second low-pass filter, and adding means for extracting a clock component by taking the sum of the outputs of the first and second calculating means. A clock error detecting means for detecting a clock phase error from the output of the adding means, and a clock oscillating means for changing the oscillation frequency according to the output from the phase error detecting means. Apparatus. 2. The phase error detection means includes first delay means for delaying the output of the addition means by 1 clock time, and second delay means for delaying the output of the first delay means by 1 clock time. A first averaging means for averaging the output of the adding means and the output of the second delay means, and a first difference means for subtracting the output of the averaging means from the output of the first delay means A second difference means for subtracting the output of the adder means from the output of the second delay means; and when the output of the second difference means is positive, the output of the first difference means is used as it is for the clock phase. A first sign inverting means for outputting an error signal and inverting the output of the first difference means when the output of the second difference means is negative to output as a clock phase error signal. Billing Item 2. The clock regenerator according to Item 1. 3. The phase error detecting means includes a third delay means for delaying the output of the adding means by one clock time, and a third delay means for subtracting the output of the adding means from the output of the third delay means. A difference means; a fourth delay means for delaying the output of the third difference means by 1 clock time; a fifth delay means for delaying the output of the fourth delay means by 1 clock time; and a fifth delay means. Fourth difference means for subtracting the output of the third difference means from the output of the delay means, and when the output of the fourth difference means is positive, the output of the fourth delay means is used as it is as the clock phase error signal. Second sign inverting means for outputting and inverting the output of the fourth delay means and outputting it as a clock phase error signal when the output of the fourth difference means is negative. Item 1 Clock reproduction device. 4. The phase error detecting means includes sixth delay means for delaying the output of the adding means by one clock time, and fifth delay means for subtracting the output of the adding means from the output of the sixth delay means. Difference means, seventh delay means for delaying the output of the fifth difference means by one clock time, and sixth difference means for subtracting the output of the fifth difference means from the output of the seventh delay means An eighth delay means for delaying the output of the sixth difference means by one clock time, a ninth delay means for delaying the output of the eighth delay means by one clock time, and the ninth delay means And a seventh difference means for subtracting the output of the sixth difference means from the output of the sixth difference means, and when the output of the seventh difference means is positive, the output of the eighth delay means is directly output as a clock phase error signal. , The seventh difference means Output inverts clock reproducing apparatus according to claim 1, characterized by comprising a third sign inversion means for outputting a clock phase error signal output of the delay means of the eighth when negative.