KR100290869B1 - apparatus for detection frequency off-set sign of demodulation - Google Patents

Abstract

PURPOSE: An identification device for frequency offset code of a demodulator is provided to improve capability of the demodulator via quick demodulating operation of signal by identifying offset code of frequency using relationship between continuously inputting signals to recover symbol timing. CONSTITUTION: A QPSK(quadrature phase shift keying) demodulator includes a tuner, an A/D converter, a demodulator, a filter, an NCO(numerically controlled oscillator) and a sweep generator. The QPSK demodulator comprises a complex conjugate number generation unit(12), an accumulating unit(15), a code output unit(17), and frequency offset code identifying unit. The operating unit produces conjugate complex number with present signal and previous signal of filtered I channel signal and Q channel signal from the demodulator to determine offset of phase angle. The accumulating unit accumulates the offset for certain sample range to output the cumulative offset. The output unit outputs high or low code value via determination of cumulative offset of phase angle. The identifying unit identifies and outputs the frequency offset code vis counting of offset code value of phase angle.

Description

Apparatus for detection frequency off-set sign of demodulation}

The present invention relates to a demodulator, and more particularly, to an apparatus for determining a frequency offset code of a demodulator.

First, a general quadrature phase shift keying (QPSK) demodulator 1 receives an IF (Intermediate Frequency) signal, removes an intermediate frequency, and outputs an I-channel and a Q-channel signal, as shown in FIG. An A / D converter 2 for converting the analog output of the tuner 1 to digital according to a predetermined sampling pulse, a demodulator 3 for demodulating the output of the A / D converter 2, and Matched filter 4 which performs a filtering operation to remove the quadrature components of the output signal of demodulator 3 to have a smooth curve, and removes the phase offset from the output of the matched filter 4. And a phase error detector for detecting a phase error from the output of the derotator 5 and outputting to a forward error correction (FEC) stage (not shown) for correcting an error occurring during transmission. (PhaseError Detector) (6), Time recovery 7 for compensating for the sampling time of the A / D converter 2 according to the output of the derotator 5, and a sweep generator having a constant amplitude and periodically changing the output frequency. (8), a NCO (Numerically Controlled Oscillator) 9 oscillating in accordance with the sum of the output of the phase error detector 6 and the output of the sweep generator 8 and providing its oscillation frequency to the demodulator 3; It is configured to include.

The operation of the QPSK demodulator configured as described above is as follows.

First, when the IF signal is input, the intermediate frequency component is removed via the tuner 2 and separated and output as an odd / even numbered I-channel signal and a Q-channel signal.

The I-channel and Q-channel signals are then converted into digital signals according to a constant sampling period of the A / D converter 2 and demodulated via the demodulator 3.

The digital output signal of the demodulator 3 passes through the matched filter 4 and the derotator 5, and its slope is smoothed and the phase offset is compensated and outputted to the FEC stage.

At this time, the output of the derotator 5 is input to the FEC stage and to the phase error detector 6 and the time recovery 7.

Therefore, if there is a phase error at the output of the derotator 5, the phase error value is added to the output of the sweep generator 8 by an adder and input to the NCO 9, and the NCO 9 is output of the adder. The sine wave, i.e., the sine wave and the cosine wave, having the phases corrected and having a phase difference of π / 2 with each other, is output to the demodulator 3.

The demodulator 3 applies a sine wave output of the NCO 9 to the output of the A / D converter 2 to perform a demodulation operation.

On the other hand, the time recovery 7 compensates the sampling time by providing a timing compensation value according to the output of the derotator 5 to the A / D converter 2.

At this time, in performing demodulation, the signal is demodulated after removing the carrier for transmitting the signal.

However, due to various reasons, such as interference between signals and noise generated in a circuit, a carrier is not completely removed and a frequency difference, that is, an offset, is generated due to the local oscillation frequency of the tuner 1, thereby inputting the current signal. As shown in Fig. 2, the frequency offset occurs between the signals.

At this time, since all systems cannot ideally have a certain offset tolerance, if the offset generated during signal demodulation is within the tolerance, that is, the offset period, symbol timing restoration is performed as shown in FIG. 3A and signal restoration is performed accordingly.

However, if the offset is out of the offset period, as shown in Figure 3b, symbol timing recovery becomes difficult and thus signal recovery is impossible.

At this time, in order to restore the symbol timing, it is necessary to grasp the sign of the offset, that is, the direction of occurrence. Conventionally, the direction of occurrence of the offset is detected by increasing the search interval alternately in the (+) and (-) directions based on a certain data symbol. As a result, the offset period is properly adjusted to recover the symbol timing.

The QPSK demodulator according to the prior art has a problem in that the symbol timing recovery is not performed well and the signal demodulation time is delayed because the code discrimination process of the offset outside the offset allowance is complicated.

Accordingly, an object of the present invention is to provide an offset code discrimination apparatus of a demodulator capable of quickly performing signal demodulation by determining a frequency offset code.

1 is a block diagram showing the configuration of a typical QPSK demodulator

2 is a diagram illustrating frequency offsets of two consecutive symbols in an input signal;

3A and 3B are diagrams showing signal distribution states depending on whether symbol timing is recovered in the presence of a frequency offset;

Figure 4 is a block diagram showing the configuration of a QPSK demodulator including a frequency offset code discrimination apparatus according to the present invention

5 is a block diagram showing the detailed configuration of the frequency offset code determination apparatus of FIG.

6 is a graph showing a transition state of an input signal

7A and 7B are graphs illustrating changes in signal values according to symbol timing errors.

8 is a block diagram showing the configuration of another embodiment of a frequency offset code determination apparatus according to the present invention.

Explanation of symbols for main parts of the drawings

10: frequency offset code discriminator 11: signal synthesis section

12: conjugate complex generator 13: delay unit

14: imaginary detector 15: accumulator

16: first counter 17: code value output unit

18: second counter 19: third counter

20: Transition signal (+) section generator 21: Transition signal (-) section generator

22: RC filter A ₁ : OP amplifier

The present invention provides a demodulator comprising: a signal synthesizer which receives an I-channel signal and a Q-channel signal, and synthesizes them in a complex form; Delay unit for a predetermined time delay, a multiplier for multiplying the output of the delay unit with the output of the signal synthesis unit, an imaginary detector for detecting only imaginary components of the multiplier output, an accumulation unit for accumulating the outputs of the imaginary detector unit, and a signal sample If the carry is counted by a number of times, the first counter for turning on the accumulator and outputting the accumulated value of the accumulator part and outputting a 'high' or 'low' signal depending on the sign of the accumulator output value. Second and third counters and second counters for counting the number of 'high' signals or 'low' signals among the outputs of the output unit and the code value output unit, respectively. Transition signal (+) section generation section and transition signal (-) section generation which generate transition signal of (+) section and transition signal of (-) section according to the carry generated in the third counter and input to the sweep generator It is configured to include wealth.

Another feature of the present invention is that the number of bits of the second counter and the third counter is set according to the sampling frequency.

Hereinafter, a frequency offset code determination apparatus of a demodulator according to the present invention will be described with reference to the accompanying drawings.

4 is a block diagram showing a configuration of a QPSK demodulator including a frequency offset code discrimination apparatus according to the present invention, FIG. 5 is a block diagram showing a detailed configuration of the frequency offset code discrimination apparatus of FIG. 4, and FIG. 6 is a transition state of an input signal. 7A and 7B are graphs showing changes in signal values according to symbol timing errors, and FIG. 8 is a block diagram showing a configuration of another embodiment of an apparatus for determining a frequency offset code according to the present invention.

Since the configuration of the QPSK demodulator to which the apparatus for discriminating the frequency offset code of the demodulator according to the present invention is applied is the same as that of the general QPSK demodulator described above, the description thereof will be omitted and the same reference numerals will be given.

As shown in FIG. 4, the frequency offset code discriminator 10 according to the present invention receives the filtered I-channel and Q-channel signals through the matched filter 4, and determines the sign of the frequency offset therefrom. The signal is thus configured to be input to the sweep generator 8.

In this case, as shown in FIG. 5, the detailed configuration of the frequency offset code discrimination apparatus includes a signal synthesizing unit 11 and a signal synthesizing unit 11 for receiving an I-channel signal and a Q-channel signal and synthesizing it into a complex form of I + jQ A complex conjugate generator 12 for generating a complex conjugate of the I + jQ signal output from 11), a delay unit 13 for delaying the output of the conjugate complex generator 12 for a predetermined time, and a delay unit 13; A multiplier (M) for multiplying an output and a signal input next to the signal used for the complex-complex generation, an imaginary detector (14) for selectively outputting only an imaginary component corresponding to a frequency offset among the output values of the multiplier (M), and the imaginary detector Accumulation unit 15 that continuously adds and accumulates the output of 14, counts as many as the number of signal samples, and if a carry occurs, outputs a reset signal to the accumulation unit 15 and switches SW _1. ) To 'on' the output of the accumulator 15 The first counter 16 to be transmitted to the control unit, the code value output unit 17 for outputting '0' or '1' according to the sign of the output value of the accumulator unit 15, N bits corresponding to the number of signal sampling, respectively The second and third counters 18 and 19 for counting the number of '1' or '0' among the output values of the code value output unit 17 and generating a carry when the count value exceeds N bits; Transition signal (+) section generation unit 20 for generating a + direction transition signal according to the output of the second counter 18, Transition signal for generating a -direction transition signal according to the output of the third counter 19 It consists of a (-) section generation part 21.

Looking at the operation of the frequency offset code determination device configured as described above in detail as follows.

First, when an I-channel signal and a Q-channel signal are input from the matched filter 4, the signal synthesis unit 11 synthesizes a complex form of I (t) + jQ (t), and the conjugate complex generator 12 A conjugate complex number for the signal is generated.

At this time, the phase angle difference between two consecutively input signals is derived by multiplying the complex conjugate of the current signal and the previous signal.

Therefore, the conjugate complex number is delayed until the next signal is input through the delay unit 13 and multiplied by the next input signal.

Next, the imaginary number detector 14 detects only imaginary components of the multiplication output values.

Where I (t) + jQ (t) is The previous signal, I (t-1) + jQ (t-1), Since multiplying two signals does not change the cosine value, it does not affect the phase angle difference.

Therefore, the real component is removed and only the imaginary component, that is, the phase angle difference is detected.

The imaginary components continuously detected according to the input signal are continuously accumulated in the accumulation unit 15.

In this case, as shown in FIG. 6, when the input signal transitions to a number of 16 cases and there are pairs having opposite values within 1 to 8 and 9 to 16, and phase difference detection is performed with 8000 samples, as shown in FIG. 7A, Probably uniform signal processing is performed and the cumulative value of the accumulator 15 converges to '0', so that the symbol timing is recovered in the presence of the frequency offset, and it is not necessary to determine the sign of the frequency offset.

However, if the symbol timing is not recovered in the presence of the frequency offset, as shown in FIG. 7B, even though the pairs of opposite signs are different in size, the cumulative values do not become '0' and increase or decrease by '+' or '-'. This cumulative value can be used as a signal for determining the sign of the frequency offset.

At the same time, when the first counter 16 counts the imaginary component detection number, that is, the 8000 sampling numbers, and reaches 8000 counts, the accumulation unit 15 is reset and the switch SW ₁ is turned on to turn on the accumulation unit ( The value accumulated in 15 is input to the sign value output unit 17.

Subsequently, the sign value output unit 17 detects only the sign of the output value of the accumulator 15 and outputs '1' if the accumulated value is '+' and '0' if the accumulated value is '-'.

In the present invention, since the 8000 sampling is repeated a predetermined time, the second counter 18 increases the count value whenever the output of the code value output unit 17 is '1', and the carry generated by exceeding the number of bits is generated. The transition signal (+) is input to the section generator 20.

On the other hand, since the third counter 19 receives '1' through the inverter IV ₁ whenever the output of the sign value output unit 17 is '0', the count value is increased and the carry generated is increased. The transition signal (-) is input to the section generator 21.

Subsequently, the transition signal (+) section generator 20 or the transition signal (-) section generator 21 transitions the '+' section when the output of the second counter 18 or the third counter 19 is input. A signal or a '-' interval transition signal is input to the sweep generator 8, and accordingly, the sweep generator 8 changes the oscillation frequency to induce a frequency offset into a section capable of symbol timing recovery.

Hereinafter, another embodiment of the frequency offset code determination apparatus of the demodulator according to the present invention will be described with reference to FIG.

The second embodiment of the frequency offset code discrimination apparatus of the demodulator according to the present invention is to process the signal processing according to the frequency offset code discrimination by analog, not digital, and tuner (instead of adjusting the oscillation frequency of the sweep generator 8). A device for controlling the frequency offset by controlling the AFC stage of 2), the RC filter 22 for analogizing the output of the transition signal (+) section generator 20 and the transition signal (-) section generator 21 The configuration and operation are the same except that an OP amplifier A ₁ for amplifying the output of the RC filter 22 to a predetermined level and inputting the same to the AFC stage is added.

The apparatus for discriminating the frequency offset code of the demodulator according to the present invention discriminates the sign of the frequency offset by using the relationship between the signals which are continuously input and performs the fast signal demodulation operation by adjusting the frequency offset to the section where symbol timing recovery is possible accordingly. It has the effect of improving the performance.

Claims (6)

In QPSK demodulator including tuner, A / D converter, demodulator, filter, NCO and sweep generator, Phase angle offset calculating means for generating a conjugate complex number from the current signal and the previous signal of the filtered I channel signal and the Q channel signal output from the demodulator to calculate the offset of the phase angle; Accumulation means for accumulating and outputting the offset of the phase angle for a predetermined sample period; Phase angle offset code value output means for determining a accumulated phase angle offset for each predetermined sample interval and outputting a high or low code value; Frequency offset code discrimination means for discriminating and outputting the frequency offset code by the carry generated by counting the phase angle offset code value for each code, and symbol timing recovery is possible according to the frequency offset code from the frequency offset determination means. And a frequency offset code discrimination apparatus for demodulating the QSPK demodulator. The method of claim 1, The phase angle offset calculating means, A signal synthesizing unit which combines the I channel signal and the Q channel signal into a complex form; A conjugate complex generator which generates a conjugate complex number of the signal synthesizer output; A delay unit for delaying an output of the conjugate complex number generation unit for a predetermined time; A multiplication unit for multiplying the output of the delay unit and the output of the signal synthesis unit; And an imaginary detector for detecting only imaginary components of the output of the multiplier. The method of claim 1, The accumulation means An accumulator for adding and accumulating the phase angle offsets output from the phase angle offset calculating means; And a first counter which resets the accumulator and turns on the switch to output the accumulated value of the accumulator when a carry is generated by counting a predetermined operation for a predetermined period of time. The method of claim 1, The frequency offset determination means, A second count for generating a carry by counting a high code value among the phase angle offset code values; A transition signal (+) section generation unit for generating a transition signal of a (+) section according to the carry generated in the second count, A third count generating a carry by counting a low code value among the phase angle code values; And a transition signal (-) section generation unit for generating a transition signal of the (-) section according to the carry generated from the third count. The method of claim 1, And the frequency offset discrimination means is configured such that an output is connected to an input of the sweep generator. The method of claim 1, The output of the frequency offset determining means further comprises an RC filter for analogization, and the output of the frequency offset determining means is configured to be connected to be input to the AFC stage of the tuner via the RC filter. Frequency offset code discrimination device.