JP2000270030A - Fsk signal demodulating circuit - Google Patents

Fsk signal demodulating circuit

Info

Publication number
JP2000270030A
JP2000270030A JP11075113A JP7511399A JP2000270030A JP 2000270030 A JP2000270030 A JP 2000270030A JP 11075113 A JP11075113 A JP 11075113A JP 7511399 A JP7511399 A JP 7511399A JP 2000270030 A JP2000270030 A JP 2000270030A
Authority
JP
Japan
Prior art keywords
signal
frequency
fsk
fsk signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11075113A
Other languages
Japanese (ja)
Inventor
Tadashi Kobayashi
忠 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP11075113A priority Critical patent/JP2000270030A/en
Publication of JP2000270030A publication Critical patent/JP2000270030A/en
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PROBLEM TO BE SOLVED: To lower the cost of an FSK receiver by constituting a demodulating circuit for a FSK signal without using a multiplier entailing an increase in the number of components. SOLUTION: An FSK signal of down-converted intermediate frequency is converted by an A/D converter 1 into a digital signal, which is inputted to a CPU; and a Fourier transformation part 3 transforms a signal varying in value with time into frequency spectrum data and inputs the data to a frequency decision part 4 to decide a code word. When a multi-valued FSK signal is demodulated, the program of the CPU is rewritten for the demodulation.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はFSK(Frequency S
hift Keying)信号の復調回路に関する。
The present invention relates to an FSK (Frequency S)
Hift Keying) signal demodulation circuit.

【0002】[0002]

【従来の技術】FSK信号受信機に用いる復調回路には
同期検波方式あるいは遅延検波方式等があるが、同期検
波方式は搬送波再生回路、掛け算器、フィルタ、位相検
波器および微分回路で構成され、また、遅延検波方式は
遅延回路、掛け算器、フィルタ、位相検波器および微分
回路で構成されるもので、何れも、部品点数の増加につ
ながる掛け算器を備えなければならないという問題があ
った。
2. Description of the Related Art A demodulation circuit used in an FSK signal receiver includes a synchronous detection method and a delay detection method. The synchronous detection method is composed of a carrier recovery circuit, a multiplier, a filter, a phase detector, and a differentiation circuit. In addition, the delay detection method includes a delay circuit, a multiplier, a filter, a phase detector, and a differentiating circuit, and has a problem in that each of the delay detection methods must include a multiplier that increases the number of components.

【0003】[0003]

【発明が解決しようとする課題】本発明は、部品点数の
増加につながる掛け算器を不要とし、FSK受信機のコ
ストの低減を可能にするFSK信号復調回路を得ること
を目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide an FSK signal demodulation circuit which eliminates the need for a multiplier which leads to an increase in the number of components and which can reduce the cost of an FSK receiver.

【0004】[0004]

【課題を解決するための手段】上記目的を達成するた
め、本発明のFSK信号復調回路は、FSK信号をサン
プリングしディジタル信号に変換するA/Dコンバータ
と、A/Dコンバータよりの時間と共に値が変化する信
号を周波数スペクトルデータに変換する演算回路と、演
算回路よりの信号の周波数から符号語を判定し出力する
周波数判定部とから構成する。
In order to achieve the above object, an FSK signal demodulation circuit according to the present invention comprises: an A / D converter for sampling an FSK signal and converting it to a digital signal; And a frequency determination unit that determines and outputs a codeword from the frequency of the signal from the arithmetic circuit.

【0005】なお、演算回路にはフーリエ変換の演算を
なす回路を用いる。
Note that a circuit that performs a Fourier transform operation is used as the operation circuit.

【0006】また、周波数判定部には、FSK信号のビ
ット数に対応する符号語判定機能を有するものを用い
る。
[0006] A frequency determination unit having a code word determination function corresponding to the number of bits of the FSK signal is used.

【0007】この周波数判定部には、FSK信号のビッ
ト数に応じて符号語を判定するためのプログラムの書替
えが可能なものを用いるようにしてもよい。
[0007] The frequency determination section may use a rewriteable program for determining a codeword in accordance with the number of bits of the FSK signal.

【0008】[0008]

【発明の実施の形態】発明の実施の形態を実施例に基づ
き図面を参照して説明する。図1は本発明によるFSK
信号復調回路の一実施例の要部ブロック図である。図に
おいて、1はA/Dコンバータで、中間周波数に変換さ
れたFSK信号をサンプリングし、ディジタル信号に変
換する。2はCPUで、フーリエ変換部3、周波数判定
部4および制御部5で構成され、フーリエ変換部3(演
算回路)でA/Dコンバータ1よりの時間と共に値が変
化する信号を周波数スペクトルデータに変換し、周波数
判定部4でスペクトルの周波数から符号語を判定する。
制御部5はフーリエ変換部3および周波数判定部4を制
御する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 1 shows an FSK according to the present invention.
FIG. 3 is a block diagram of a main part of an embodiment of a signal demodulation circuit. In the figure, reference numeral 1 denotes an A / D converter, which samples an FSK signal converted into an intermediate frequency and converts it into a digital signal. Reference numeral 2 denotes a CPU, which includes a Fourier transform unit 3, a frequency determination unit 4, and a control unit 5. The Fourier transform unit 3 (arithmetic circuit) converts a signal whose value changes with time from the A / D converter 1 into frequency spectrum data. After conversion, the codeword is determined from the frequency of the spectrum by the frequency determination unit 4.
The control unit 5 controls the Fourier transform unit 3 and the frequency determination unit 4.

【0009】次に、本発明によるFSK信号復調回路の
動作を説明する。FSK変調された信号は高周波回路で
ダウンコンバートし、中間周波増幅回路で増幅され、A
/Dコンバータ1に入力する。A/Dコンバータ1で
は、後段のフーリエ変換部3で変換される符号語の最大
周波数の2倍以上の周波数のクロックで入力FSK信号
をサンプリングし、ディジタル信号に変換する。この信
号はCPU2に入力し、演算回路であるフーリエ変換部
3で演算し、図2(イ)に示すように時間と共に値が変
化する信号を、図2(ロ)に示す周波数スペクトルのデ
ータ(所定の周波数に線スペクトルで表される)にフー
リエ変換する(フーリエ変換の公式による)。FSK変
調された符号語はそれぞれ所定の周波数(例えば、FS
K信号が2値の場合はf1またはf2)に対応しており、例
えば、第1の符号語の入力にて、フーリエ変換により周
波数f1に線スペクトルが現れ、第2の符号語の入力に
て、周波数f2に線スペクトルが現れる。すなわち、フー
リエ変換によりFSK信号が復調される。これら復調さ
れた信号を周波数判定部4に入力し、周波数f1、f2等か
ら符号語を判定し、出力する。符号語は、例えば、FS
K信号が2値の場合は0または1(1ビット)であり、
FSK信号が4値の場合は00、01、10または11(2ビッ
ト)であり、FSK信号が8値の場合は000 、001 、01
0 、011 、100 、101 、110 または111 (3ビット)で
ある。
Next, the operation of the FSK signal demodulation circuit according to the present invention will be described. The FSK-modulated signal is down-converted by a high frequency circuit, amplified by an intermediate frequency amplifier circuit, and
/ D converter 1 The A / D converter 1 samples the input FSK signal with a clock having a frequency twice or more the maximum frequency of the codeword converted by the subsequent Fourier transform unit 3 and converts it into a digital signal. This signal is input to the CPU 2 and calculated by the Fourier transform unit 3 which is an arithmetic circuit. A signal whose value changes with time as shown in FIG. 2A is converted into data of the frequency spectrum shown in FIG. Fourier transform (represented by a line spectrum at a predetermined frequency) (according to the Fourier transform formula). Each of the FSK-modulated codewords has a predetermined frequency (for example, FS
If the K signal is binary, it corresponds to f1 or f2). For example, at the input of the first codeword, a line spectrum appears at the frequency f1 by Fourier transform, and at the input of the second codeword. , A line spectrum appears at the frequency f2. That is, the FSK signal is demodulated by Fourier transform. These demodulated signals are input to the frequency determination unit 4, where the codeword is determined from the frequencies f1, f2, etc., and output. The code word is, for example, FS
If the K signal is binary, it is 0 or 1 (1 bit),
If the FSK signal has four values, it is 00, 01, 10 or 11 (2 bits). If the FSK signal has eight values, it is 000, 001, 01.
0, 011, 100, 101, 110 or 111 (3 bits).

【0010】周波数判定部4は、復調されるFSK信号
のビット数に対応する符号語判定機能を有するものと
し、多値のFSK信号の復調回路にも対応できるように
する。このため、符号語の数に応じて判定すべき周波数
を設定できるように、例えば、CPU2のプログラムの
書替えにより多値のFSK信号に対応できるようにして
おく。
The frequency determination section 4 has a code word determination function corresponding to the number of bits of the FSK signal to be demodulated, so that it can support a demodulation circuit for a multi-level FSK signal. Therefore, in order to set the frequency to be determined according to the number of codewords, for example, the program of the CPU 2 is rewritten so that it can cope with a multi-level FSK signal.

【0011】[0011]

【発明の効果】以上に説明したように、本発明によるF
SK信号復調回路によれば、A/DコンバータとCPU
(フーリエ変換部および周波数判定部等からなる)によ
りFSK信号を復調するものであるから、部品点数の増
加につながる掛け算器を用いる必要がなく、また、多値
のFSK信号を復調する場合でもCPUのプログラムの
書替えで対応することができ、FSK信号受信機を経済
的に構成することができる。
As described above, the F according to the present invention is used.
According to the SK signal demodulation circuit, the A / D converter and the CPU
Since the FSK signal is demodulated by a Fourier transform unit and a frequency determination unit, there is no need to use a multiplier that leads to an increase in the number of parts. Can be dealt with by rewriting the program, and the FSK signal receiver can be constructed economically.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明によるFSK信号復調回路の一実施例の
要部ブロック図である。
FIG. 1 is a main block diagram of an embodiment of an FSK signal demodulation circuit according to the present invention.

【図2】フーリエ変換の説明図である。FIG. 2 is an explanatory diagram of a Fourier transform.

【符号の説明】[Explanation of symbols]

1 A/Dコンバータ 2 CPU 3 フーリエ変換部 4 周波数判定部 5 制御部 DESCRIPTION OF SYMBOLS 1 A / D converter 2 CPU 3 Fourier conversion part 4 Frequency judgment part 5 Control part

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 FSK(Frequency Shift Keying)信号を
サンプリングしディジタル信号に変換するA/Dコンバ
ータと、A/Dコンバータよりの時間と共に値が変化す
る信号を周波数スペクトルデータに変換する演算回路
と、演算回路よりの信号の周波数から符号語を判定し出
力する周波数判定部とからなるFSK信号復調回路。
1. An A / D converter for sampling an FSK (Frequency Shift Keying) signal and converting it to a digital signal, an arithmetic circuit for converting a signal whose value changes with time from the A / D converter to frequency spectrum data, An FSK signal demodulation circuit comprising: a frequency determination unit that determines and outputs a codeword from a frequency of a signal from an arithmetic circuit.
【請求項2】 前記演算回路はフーリエ変換の演算をな
す回路からなる請求項1記載のFSK信号復調回路。
2. The FSK signal demodulation circuit according to claim 1, wherein said operation circuit comprises a circuit for performing a Fourier transform operation.
【請求項3】 前記周波数判定部は、前記FSK信号の
ビット数に対応する符号語判定機能を有するものでなる
請求項1または2記載のFSK信号復調回路。
3. The FSK signal demodulation circuit according to claim 1, wherein the frequency judgment unit has a code word judgment function corresponding to the number of bits of the FSK signal.
【請求項4】 前記周波数判定部は、前記FSK信号の
ビット数に応じて符号語を判定するためのプログラムの
書替えが可能なものを用いてなる請求項1、2または3
記載のFSK信号復調回路。
4. The frequency determining unit according to claim 1, wherein a program for determining a code word according to the number of bits of the FSK signal is rewritable.
The FSK signal demodulation circuit as described in the above.
JP11075113A 1999-03-19 1999-03-19 Fsk signal demodulating circuit Pending JP2000270030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11075113A JP2000270030A (en) 1999-03-19 1999-03-19 Fsk signal demodulating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11075113A JP2000270030A (en) 1999-03-19 1999-03-19 Fsk signal demodulating circuit

Publications (1)

Publication Number Publication Date
JP2000270030A true JP2000270030A (en) 2000-09-29

Family

ID=13566812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11075113A Pending JP2000270030A (en) 1999-03-19 1999-03-19 Fsk signal demodulating circuit

Country Status (1)

Country Link
JP (1) JP2000270030A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010050546A (en) * 2008-08-19 2010-03-04 Toshiba Corp Demodulation device and demodulating method
WO2014103267A1 (en) * 2012-12-27 2014-07-03 パナソニック株式会社 Receiving apparatus and demodulation method
JP2015159466A (en) * 2014-02-25 2015-09-03 パナソニック株式会社 Receiving device and modulation method
JP2015159467A (en) * 2014-02-25 2015-09-03 パナソニック株式会社 Receiving device and modulation method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010050546A (en) * 2008-08-19 2010-03-04 Toshiba Corp Demodulation device and demodulating method
WO2014103267A1 (en) * 2012-12-27 2014-07-03 パナソニック株式会社 Receiving apparatus and demodulation method
JP2014127910A (en) * 2012-12-27 2014-07-07 Panasonic Corp Reception device and demodulation method
US10142143B2 (en) 2012-12-27 2018-11-27 Panasonic Corporation Receiving apparatus and demodulation method
JP2015159466A (en) * 2014-02-25 2015-09-03 パナソニック株式会社 Receiving device and modulation method
JP2015159467A (en) * 2014-02-25 2015-09-03 パナソニック株式会社 Receiving device and modulation method

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