JP3616709B2 - Data recovery circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data recovery circuit for recovering input data using a recovered clock signal created from an input bit synchronization signal.
[0002]
[Prior art]
The selective call signal is transmitted / received in accordance with a digital signal protocol generally called POCSAG (Post Office Code Standardization Advisory Group). This selective paging signal is shown in the document “POCSAG radio paging system RCR STD-42” (Radio System Development Center, formulated on November 10, 1994).
[0003]
In the POCSAG system, before the information signal is transmitted, a repetition of 1, 0 of at least 576 bits is transmitted at the transmission bit rate for bit synchronization. This is called a preamble. Then, an information signal is transmitted following this preamble. In a normal selective call signal receiver (pager or the like), bit synchronization is performed when this preamble is received.
[0004]
FIG. 5 is a diagram showing a conventional data recovery circuit for performing data recovery with bit synchronization as described above. In this circuit, the phase comparator 1 compares the phase of the input signal and the output clock (regenerated clock) of the digitally controlled oscillator 3, and the result is passed through the loop filter 2 and then input to the digitally controlled oscillator 3. It is composed of Then, the reproduction clock obtained by the digital control oscillator 3 is input to an FF (flip-flop) circuit 4, and the input signal is sampled at the falling edge of the reproduction clock to reproduce the data. In this conventional data reproducing circuit, as shown in FIG. 6, if the duty of the input signal is 50%, the preamble can always be reproduced.
[0005]
[Problems to be solved by the invention]
However, in a selective call receiver, even a preamble with a duty of 25% to 75% usually has to be recognized as a preamble. However, as shown in FIG. If the signal cannot be received in%, the preamble could not be played back at the initial stage where synchronization could not be achieved. This is because the timing for fetching data in the FF circuit 4 is delayed.
[0006]
The present invention has been made in view of the above points, and an object of the present invention is to perform data reproduction at high speed by using both the rising edge and falling edge of the reproduction clock. .
[0007]
[Means for Solving the Problems]
According to a first aspect of the present invention for achieving the above object, in a data reproduction circuit for reproducing a digital signal including a synchronization signal for bit synchronization consisting of at least two or more repetitions of 1 and 0, the same bit period as the synchronization signal A clock recovery means for generating a recovered clock, a first sampling means for sampling an input signal at one rising or falling edge of the recovered clock, and at the other rising or falling edge of the recovered clock. A second sampling means for sampling an input signal; and the first sampling means does not detect a repetition of 1 or 0 of 2 bits or more of the input signal, and the second sampling means detects the repetition. Determining means for controlling the clock recovery means to invert the recovered clock; And Bei, and the output data of said first sampling means configured to the reproduction data.
According to a second invention, in the first invention, the clock recovery means is controlled by the determination means only during the reception period of the synchronization signal, and thereafter holds the polarity of the recovered clock.
According to a third aspect of the present invention, in a data reproduction circuit for reproducing a digital signal including a synchronization signal for bit synchronization consisting of at least two or more repetitions of 1 and 0, a reproduction clock having the same bit period as the synchronization signal is generated. A clock recovery means; a first sampling means for sampling an input signal at one rising edge or falling edge of the recovered clock; and a second sampling means for sampling the input signal at the other rising / falling edge of the recovered clock. A sampling means; and a selection means for selecting, as reproduction data, an output signal of the sampling means on the side of the first and second sampling means that detects the repetition of 1, 0 of 2 bits or more of the input signal. It comprised so that it might comprise.
According to a fourth aspect, in the third aspect, the selection unit operates only during a period during which the synchronization signal is received, and thereafter maintains the selection state.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
FIG. 1 is a block diagram of a data reproducing circuit according to the first embodiment of the present invention. The same components as those shown in FIG. 5 are given the same reference numerals. Reference numerals 5 and 6 denote S / P (serial / parallel) converters for inputting serial data and outputting 3-bit parallel data. One of the S / P converters 5 is an input signal at the falling edge of the reproduction clock. The other S / P converter 6 samples the input signal at the rising edge of the recovered clock. Reference numeral 7 denotes an inverter for inverting the reproduction clock. Reference numeral 8 is a determination unit that compares and determines the 3-bit data of the S / P conversion circuits 5 and 6, and 9 is an AND circuit that opens the gate only when the preamble is received, and this output is applied to the polarity control terminal of the digital control oscillator 3. You are typing. The reproduction data is taken out from the output of the first bit of the S / P converter 5 that samples the input signal at the falling edge of the reproduction clock.
[0009]
The operation will be described below with reference to FIG. The input signal is the same as the input signal shown in FIG. At times t1, t3, and t5 of the falling edge of the recovered clock obtained by the digital control oscillator 3, the sampling data of the S / P converter 5 is 0, 0, 0, and the time t2 of the rising edge of the recovered clock. At t4 and t6, the sampling data of the S / P converter 6 is 1, 0, 1.
[0010]
Thus, if the bit string of the output data of the S / P converter 5 on the side from which the reproduction data is extracted is “000”, and the bit string of the output data of the other S / P converter 6 is “101”, the determination is made. The device 8 sends “1” to the digitally controlled oscillator 3 via the AND circuit 9. For this reason, the phase of the recovered clock output from the digitally controlled oscillator 3 is inverted.
[0011]
After the reproduction clock is inverted, the preamble is normally reproduced from the first bit terminal of the S / P converter 5. Since the AND circuit 9 closes the gate except when the preamble is received, the digitally controlled oscillator 3 is not affected by the determination result of the determiner 8 after the preamble reception.
[0012]
FIG. 3 is a diagram showing the determination contents of the determiner 8. This determination unit 8 reproduces data when the same data such as “000” or “111” continues (the preamble cannot be received) at the output of the S / P converter 5 that captures data at the falling edge of the reproduction clock. When the same data such as “101” or “010” does not follow the output of the S / P converter 6 that captures data at the rising edge of the clock (preamble is received), it operates and outputs “1”. Then reverse the playback clock. Further, when the output data of the S / P converter 5 has a change of even 1 bit out of 3 bits, the preamble reception is possible and the determiner 8 sets “0” regardless of the data of the S / P converter 6. Is output.
[0013]
From the above, even if the preamble portion of the input signal is deteriorated due to noise or the like and the duty cannot be received at 50%, the bit synchronization signal synchronized with the preamble can be reproduced early after the reception of the input signal is started. it can.
[0014]
[Second Embodiment]
FIG. 4 is a diagram showing a data reproduction circuit according to the second embodiment. Here, a selector 10 is newly provided for the circuit shown in FIG. 1, and the selector 10 selects the output of the first bit of the S / P converter 5 or S / P converter 6. Output as playback data. The determination unit 8 controls the selection unit 10 so that the selection unit 10 selects the bit string “101” or “010”, that is, the output of the S / P converter on the side where the preamble is obtained. The digitally controlled oscillator 3 is not controlled. The selection unit 10 holds the selected state after the preamble reception is completed.
[0015]
Therefore, even in this embodiment, even when the preamble portion of the input signal is deteriorated due to noise or the like and the duty cannot be received at 50%, the bit synchronization signal synchronized with the preamble early after the reception of the input signal is started. Can be played.
[0016]
[Other embodiments]
In the first embodiment, the output of the first bit of the S / P converter 5 is extracted as reproduction data. However, the output of the first bit of the S / P converter 6 is used as reproduction data. When the output of the S / P converter 6 is “000” or “111” and the output of the S / P converter 5 is “101” or “010”, the recovered clock is inverted. Good.
[0017]
Further, the S / P converters 5 and 6 described above are not limited to output data of 3 bits. For example, in the case of 4 bits, in the first embodiment, when one S / P converter 5 cannot detect the bit string “1010” or “0101”, the other S / P converter When 6 detects it, the recovered clock may be inverted. Similarly, regardless of how many bits the output bit length of the S / P converters 5 and 6 is 2 or more, one S / P converter 5 is “1010...” Or “0101. When the other S / P converter 6 detects it when the bit string “.” Cannot be detected, the recovered clock may be inverted.
[0018]
Alternatively, one S / P converter 5 may sample the input signal at the rising edge of the recovered clock, and the other S / P converter 6 may sample the input signal at the rising edge.
[0019]
In the above description, the case where a POCSAG paging signal is received has been described. However, the present invention can be applied to all apparatuses that reproduce a signal including a bit synchronization signal composed of repetition of “1” and “0”.
[0020]
【The invention's effect】
As described above, according to the present invention, even if the input signal is deteriorated due to noise or the like, there is an advantage that the bit synchronization signal can be reproduced early after the reception of the input signal, that is, at a high speed.
[Brief description of the drawings]
FIG. 1 is a block diagram of a data reproduction circuit according to a first embodiment.
FIG. 2 is an operation waveform diagram of the data reproduction circuit.
FIG. 3 is an explanatory diagram of determination contents of a determination unit of the data reproduction circuit.
FIG. 4 is a block diagram of a data reproduction circuit according to a second embodiment.
FIG. 5 is a block diagram of a conventional data reproduction circuit.
FIG. 6 is an operation waveform diagram when receiving a 50% duty input signal of a conventional data reproduction circuit.
FIG. 7 is an operation waveform diagram when receiving a deteriorated input signal of a conventional data reproduction circuit.

Claims (4)

In a data reproduction circuit for reproducing a digital signal including a synchronization signal for bit synchronization consisting of at least two or more repetitions of 1, 0,
Clock recovery means for generating a recovered clock having the same bit period as the synchronization signal;
First sampling means for sampling an input signal at one of rising and falling edges of the reproduction clock;
Second sampling means for sampling the input signal at the other rising or falling edge of the recovered clock;
When the first sampling means does not detect the repetition of 1 or 0 of 2 bits or more of the input signal and the second sampling means detects the repetition, the clock recovery means is controlled to control the recovered clock. Determining means for inverting
Comprising
A data reproduction circuit characterized in that the output data of the first sampling means is reproduction data. 2. The data recovery circuit according to claim 1, wherein the clock recovery means is controlled by the determination means only during the reception period of the synchronization signal, and thereafter holds the polarity of the recovery clock. In a data reproduction circuit for reproducing a digital signal including a synchronization signal for bit synchronization consisting of at least two or more repetitions of 1, 0,
Clock recovery means for generating a recovered clock having the same bit period as the synchronization signal;
First sampling means for sampling an input signal at one of rising and falling edges of the reproduction clock;
Second sampling means for sampling the input signal at the other edge of the rising and falling edges of the reproduction clock;
A selection means for selecting, as reproduction data, an output signal of the sampling means on the side of detecting the repetition of 1, 0 of 2 bits or more of the input signal among the first and second sampling means;
A data reproduction circuit comprising: 4. The data reproduction circuit according to claim 3, wherein the selection unit operates only during a period during which the synchronization signal is received, and thereafter holds the selected state.

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