JPH10173642A - Clock-synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain clock synchronization with one circuit by considering only data for extracting clock components necessary for clock synchronization, and operating clock synchronization by holding clock data reproduced from the data for extracting clock components for the other unstable data parts. SOLUTION: The data of a specific channel are inputted from an input terminal 1, and clock components are reproduced through a rectifier 3 and a BP filter 4. A reproduced clock is transmitted through a phase comparator 5, an A/D converter 6, and a loop filter 9 constituted of an adder 7 and a memory 8, and the phase of an inside clock is compared with the phase of the clock reproduced from the received data. A voltage control oscillator 11 is controlled to a direction for returning the inside clock only by a phase difference detected this time. When unstable data are inputted from an input terminal 1, a selector 13 is switched so as to be connected with a memory 14 by a switching signal generated by a switching control signal generator 16, and the voltage control oscillator 11 is controlled by phase difference data stored in the memory 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a clock synchronization circuit used for communication equipment and transmission equipment for performing TDMA data transmission.

[0002]

2. Description of the Related Art As a conventional clock synchronous circuit, there is a circuit as shown in FIG. Hereinafter, this conventional example will be described with reference to FIG. FIG. 3 is a block diagram illustrating an example of the TDMA receiver. FIG. 4 shows a 4-channel TD
This shows the format of one frame of MA. In the figure, a is a clock, b is a preamble, c is data, d
Is a postamble. Data of a specific channel of the TDMA transmission data of a plurality of channels received from the input terminal 1 is input, and a clock component is reproduced through the rectifier 3 and the band-pass filter 4. The recovered clock is
A clock synchronized with input data by a PLL circuit 12 composed of a phase comparator 5, an A / D converter 6, a loop filter 9 including an adder 7 and a memory 8, a D / A converter 10, and a voltage controlled oscillator 11. Generate At this time, phase difference data between the phase of the internal clock output from the voltage control oscillator 7 and the clock recovered from the received value is output from the phase comparator 5, and the difference is accumulated by the loop filter 9. The voltage-controlled oscillator 1
1 to match the phase of the received value. The clock synchronized with the input data output from the voltage controlled oscillator 11 is output from the output terminal 2. Reference numeral 18 denotes a data processing circuit operated by a clock from the clock synchronization circuit.

[0003]

In the case of normal data transmission, a clock signal "a" which repeats "0" and "1" for easily extracting a clock component is added in one frame in addition to a data signal. . However, in the above-mentioned conventional example, since the clock signal is reproduced and clock synchronized without separating the data signal portion c other than the clock component extraction data in particular, when the speed of the signal increases, undefined data other than the clock component extraction data is undefined. There is a disadvantage that synchronization is easily lost due to the influence of data. Further, when the amplitude of the clock component extraction data in the received signal is reduced due to fading, noise, or the like, there is a disadvantage that the clock cannot be reproduced. Furthermore, since clock synchronization can be performed only within a certain specific channel, a clock synchronization circuit for each channel is required when using a plurality of channels.

The present invention eliminates the influence of indefinite data other than the clock component extraction data which causes a loss of synchronization, and can cope with a case where the amplitude of a received signal becomes small and the clock cannot be reproduced. It is an object of the present invention to provide a clock synchronization circuit capable of realizing clock synchronization of each channel in transmission by one circuit.

[0005]

In order to achieve the above object, the present invention focuses only on clock component extraction data necessary for clock synchronization, and reproduces other indefinite data portions from the clock component extraction data. The clock synchronization is performed while holding the clock data. Further, even when the amplitude of the clock component extraction data in the received signal becomes small and the clock cannot be reproduced, the clock synchronization may be performed using the held clock data. Further, a memory for storing phase difference data between the internal clock of each channel and the clock reproduced from the received value may be prepared for each channel, and clock synchronization may be performed by switching for each channel.

As a result, it is possible to provide a clock synchronization circuit that performs clock synchronization without using indefinite data other than the clock component extraction data that causes a loss of synchronization. Further, it is possible to provide a clock synchronous circuit that can cope with a case where the amplitude of the clock component extraction data in the received signal becomes small and the clock cannot be reproduced.
Further, it is possible to provide a clock synchronization circuit that can realize clock synchronization of each channel in multiple-channel data transmission by one circuit.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will now be described with reference to FIG.
This will be described with reference to FIG.

[0008] The input terminal 1 is connected to the rectifier 3. The output of the rectifier 3 is connected to a phase comparator 5 via a band pass filter 4. The output of the band-pass filter 4 is connected to the switching control signal generator 16, and the output of the switching control signal generator 16 is connected to the control terminal of the selector 13.
The output of the phase comparator 5 is supplied to an adder 7 via an A / D converter 6.
Connect with The output of the adder 7 is connected to the other input terminal of the adder 7 via the memory 8. The output of the adder 7 is connected to the selector 13. The output of the selector 13 is connected to another input terminal of the selector 13 via the memory 14. The output of the selector 13 is connected to the voltage controlled oscillator 11 via the D / A converter 10. The output of the voltage controlled oscillator 11 is output from the phase comparator 5 and the output terminal 2.
Connect to These components constitute the PLL 17. Hereinafter, the operation principle will be described.

The input terminal 1 receives data of a specific channel from the received TDMA transmission data of a plurality of channels (see FIG. 4), and supplies a rectifier 3 and a band-pass filter 4.
To regenerate the clock component. The recovered clock compares the phase of the internal clock with the phase of the clock recovered from the received data by the phase comparator 5, the A / D converter 6, the adder 7, and the loop filter 9 including the memory 8. The D / A converter 1 adds the sum of the phase difference data and the sum of the phase difference data stored up to one sample before stored in the memory 8 and returns the internal clock by the currently output phase difference.
0 controls the voltage-controlled oscillator 11. Where 1
When the clock component extraction data 9 which is always at a fixed position in the frame is input from the input terminal 1, the selector 13 uses the switching signal generated by the switching control signal generator 16.
Is selected to be connected to the adder 7, and the voltage controlled oscillator 11 is controlled by the phase difference data output every sample. At this time, data for controlling the voltage controlled oscillator 11 is stored in the memory 14. When the input of the clock component extraction data a is completed and indefinite data is input from the input terminal 1, the selector 13 is switched by the switching signal generated by the switching control signal generator 16 so as to connect the selector 13 to the memory 14. The voltage-controlled oscillator 11 is controlled by the phase difference data stored in. That is, clock synchronization is performed using only the clock component extraction data. When the switching control signal generator 16 recognizes that the amplitude of the received signal has fallen below the level at which the clock can be reproduced at the time of inputting the clock component extraction data, the switching control signal generator 16 connects the selector 13 to the memory 14. The voltage control oscillator 11 is controlled using the data stored in the memory 14.

Next, an application example using one embodiment of the present invention will be described with reference to FIG.

The input terminal 1 is connected to the rectifier 3. The output of the rectifier 3 is connected to a phase comparator 5 via a band pass filter 4. The output of the band pass filter 4 is connected to a switching control signal generator 16, and the output of the switching control signal generator 16 is connected to a selector 15i- _N (N: 1, 2, ...,
n (the number of channels)) and the control terminal of the selector 13. The output of the phase comparator 5 is connected to an adder 7 via an A / D converter 6. The output of the adder 7 is supplied to the selector 15
o _-N (N: 1, 2, ..., n (number of channels)), memory 8
_-N (N: 1, 2,..., N (number of channels)) to another input terminal of the adder 7. Also, the adder 7
Is connected to the selector 13. These constitute the loop filter 20. The output of the selector 13 is connected to another input terminal of the selector 13 via the memory 14. The output of the selector 13 is a D / A converter 10
To the voltage controlled oscillator 11 via The output of the voltage controlled oscillator 11 is connected to the phase comparator 5 and the output terminal 2.

The operation principle will be described below.

From the input terminal 1, the T channel of the received n channel
The data of the first channel of the DMA transmission data is input, and the same operation as in the embodiment of the present invention is performed. At this time, n memories in the loop filter are prepared in the same number as the number of channels, and only the selector _{15-1 is} connected by the switching control signal generator 16 so as to select the first memory _8-1 . Next, data of the second channel is input from the input terminal 1. At this time, only the selector _{15-2 is} connected by the switching control signal generator 16 so as to select the memory _8-2 . Similarly, when the data of the first specific channel is input again after one frame after the repetition of n channels, only the selector _{15-1 is} connected by the switching control signal generator 16 so as to select the memory _8-1, and Continues before the frame. As a result, it is possible to perform n-channel clock synchronization with one circuit without having a clock synchronization circuit for n channels.

[0014]

According to the present invention, the clock data reproduced from the clock component extraction data and the data holding the clock data are switched by the selector to perform clock synchronization. A clock synchronization circuit capable of performing clock synchronization without using undefined data other than data can be provided. Further, the present invention provides a clock synchronization circuit capable of realizing clock synchronization by using the held clock data when the amplitude of the clock component extraction data in the received signal becomes small and the clock cannot be reproduced. be able to. Further, a memory for storing the phase difference data between the internal clock of each channel and the clock recovered from the received value is prepared for each channel, and the clock synchronization is performed by switching over each channel so that the clock synchronization of a plurality of channels can be performed by one circuit. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing one embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional clock synchronization circuit.

FIG. 4 is an explanatory diagram of a data frame in TDMA data transmission.

[Explanation of symbols]

1: input terminal, 2: output terminal, 3: rectifier, 4: band-pass filter (BPF), 5: phase comparator, 6: A
/ D converter, 7: adder, 8,8 _-1 to 8 _-N : memory (N: integer), 9: loop filter, 10: D / A converter, 11: voltage controlled oscillator, 17, 19 : PLL circuit, 13: selector, 14: memory, 15 _-1 to 15 _-N :
Selector (N: integer), 16: switching control signal generator.

Claims (3)

[Claims] 1. A clock synchronous circuit comprising at least a phase-locked loop including at least a phase comparator and a voltage-controlled oscillator, wherein a loop filter is provided at a stage subsequent to the phase-shift comparator. A memory for storing the value of an internal variable of the loop filter, and controlling the voltage controlled oscillator by switching between an output of the loop filter and a memory output storing the output of the loop filter at a subsequent stage of the loop filter. A clock synchronization circuit comprising: signal switching means for setting a voltage; and switching control means for monitoring an input signal of the phase-locked loop and controlling the signal switching means in accordance with the presence or absence of detection of a synchronous clock. 2. The clock synchronization circuit according to claim 1, wherein said storage means holds clock data reproduced from clock component extraction data in a transmission signal frame, and stores said clock data in said received signal. Amplitude is
A clock synchronization circuit for performing clock synchronization using data held in the storage means when clock recovery becomes impossible. 3. The clock synchronization circuit according to claim 1, wherein a memory for storing a phase difference between a clock output from the voltage-controlled oscillator and a clock recovered from a received value for each channel in a multi-channel data transmission is used as the channel. A clock synchronizing circuit, wherein the clock synchronizing circuit performs clock synchronization by switching the memories for each channel.