JPH1022988A - Reception controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve receiving performance while keeping the stability of a system high. SOLUTION: At the time of receiving a phase deviation signal obtained by initial clock reproduction after starting reception through a loop filter 5, a voltage preset circuit 6 presets a controlled voltage value (controlled variable) based on the phase deviation signal to VCC(voltage control clock) oscillation circuit 7 and at the time of controlling the VCC oscillation circuit 7 based on the phase deviation signal obtained by clock reproduction after initial clock reproduction, controls it by difference between the controlled voltage value of this time and the preset controlled voltage value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reception control device, and more particularly to a reception control device for optimizing reception performance in radio communication in response to changes in an external environment such as fading, reception level, and multipath.

[0002]

2. Description of the Related Art In the field of wireless communication, mobile communication technology has recently been expanding. Typical examples of such techniques include a DS (Direct Sequence) system using spread spectrum and an FH (Frequency Hopping) system. These systems increase noise immunity and interference immunity by expanding the occupied frequency band. The following is an example of a DS system.

In this DS system, a PN (Pseudorand)
Using the sharp peak peculiar to the spreading code existing in the autocorrelation function of the (om Noise) sequence, synchronization pull-in based on the slow correlation value and the fast correlation value and its retention are performed.

In this DS system, for example, a delay lock loop (hereinafter referred to as DLL) is used, and once the synchronization is established by the above-described synchronization pull-in, it operates so as to maintain the synchronization establishment state. . Hereinafter, the synchronization pull-in and its holding are collectively referred to as clock recovery.

Here, the DLL will be described in detail. FIG.
0 is a block diagram showing a configuration of a DLL applied to a conventional reception control device. In the figure, reference numeral 81 denotes an input terminal for inputting a demodulated signal as a received signal, 82 and 83 multipliers for multiplication, 84 Is an adder that performs addition, 85 is a loop filter that removes high-frequency components, 86 is a VCC oscillation circuit that oscillates a voltage control clock (hereinafter, referred to as VCC),
87 generates a spreading code based on VCC and shifts the spreading code in accordance with a clock pulse (not shown).
(N is a natural number) shows a stage feedback shift register.

The N-stage feedback shift register 87 combines a spreading code generation circuit with N-stage shift registers.
Taps are provided at two places in the middle of the shift register. In the N-stage feedback shift register 87, the data extracted from each tap position is multiplied by multipliers 82 and 8
3. After being processed through the loop filter 85 and the VCC oscillation circuit 86, it returns to the head position again.

Next, clock reproduction will be described. In the DLL shown in FIG. 10, for the multipliers 82 and 83,
A spreading code is supplied from each of two tap positions of the N-stage feedback shift register 87. In other words, from one of the two taps, a spreading code whose phase is slightly delayed from the correct phase, that is, a slow spreading code L
C is extracted and output to the multiplier 83. Further, from the other tap position, a spreading code whose phase is slightly advanced from the correct phase, that is, a leading spreading code EC is extracted, and is output to the multiplier 82.

The multipliers 82 and 83 have input terminals 8
The demodulated signal input to 1 is also supplied. For this reason, the multipliers 82 and 83 respectively provide a phase spreading code EC and a phase spreading code L having different phases to the common demodulated signal of the PN sequence.
C is multiplied, and the result of the multiplication is output to the adder 84 with the early phase correlation value and the late phase correlation value. The adder 84 combines the input early correlation value and the late correlation value, and supplies the combined output to the loop filter 85.

When the combined output of the adder 84 becomes zero,
This means that the clock frequency generated on the receiving side (DLL) is synchronized with the clock frequency on the transmitting side (not shown). If the combined output takes a value other than zero, the adder 84
Generates a DC voltage proportional to the amount of the deviation, and outputs this to the loop filter 85 as a phase deviation signal. In this case, the loop filter 85 removes a high-frequency component from the input phase deviation signal and outputs the same to the subsequent-stage VCC oscillation circuit 86.

When the VCC oscillation circuit 86 receives the phase deviation signal from which the high-frequency component has been removed, the VCC oscillation circuit 86 adjusts the output of the VCC based on the phase deviation signal so that the above-mentioned combined output becomes zero. The N-stage feedback shift register 87 has a VCC
When the regulated VCC is supplied from the oscillation circuit 86,
The early spreading code EC and the late spreading code L based on the VCC
C is output to the multiplier 82 and the multiplier 83, respectively.

As described above, the conventional DLL reproduces the clock while adjusting the phase of the PN sequence in order to remove the clock frequency error generated between the radio transmitting / receiving apparatuses and the steady phase deviation including the phase jitter amount of the transmission line. The feedback loop is formed.

[0012]

Since the conventional reception control device is configured as described above, the control for removing the steady phase deviation between the radio transmitting and receiving devices is performed every time the clock is recovered. Since the phase deviation is very large, the amount of control required for removing the phase deviation is also large, resulting in a problem that the stability of the system is reduced. Especially,
Since the clock frequency error takes an extremely large value compared to the amount of phase jitter, it is necessary to perform control to eliminate the steady-state phase deviation between wireless transmission / reception devices every time the clock is recovered, regardless of the presence or absence of phase jitter due to the transmission path. there were.

Further, in order to have a synchronization pull-in width which can cope with a clock frequency error, it is necessary to largely estimate the stability of the system. For this reason, the phase jitter amount within the steady-state phase deviation needs to be allowed to some extent, so that there is a problem that the tracking performance of the phase jitter is reduced and the receiving performance is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is a first object of the present invention to provide a reception control apparatus capable of suppressing a control amount of a phase deviation and improving the stability of a system. The purpose of.

A second object of the present invention is to provide a reception control device capable of improving the reception performance by improving the tracking performance of the phase jitter while keeping the stability of the system high.

[0016]

Means for Solving the Problems The above-mentioned problems are solved,
In order to achieve the object, a reception control device according to the present invention includes:
If the control amount of the internal oscillation circuit is preset based on the phase deviation generated by the initial clock recovery after the start of reception, and the internal oscillation circuit is controlled based on the phase deviation generated by the clock recovery after the initial clock recovery, this time Is controlled by the difference between the control amount and the preset control amount.

Therefore, a control amount corresponding to the phase deviation of the initial clock is preset, and thereafter, the internal oscillation is controlled in such a manner that the preset control amount is subtracted. This eliminates the need for an operation for removing the clock signal, and greatly reduces the control amount per clock recovery. Therefore, it is possible to improve the reception performance while maintaining high system stability.

A reception control device according to the next invention presets a control amount of an internal oscillation circuit based on a phase deviation generated by initial clock recovery after the start of reception, and controls a phase deviation generated by clock recovery after the initial clock recovery. When controlling the internal oscillation circuit based on the control amount, the control is performed by the difference between the current control amount and the preset control amount, and the loop gain of the loop filter is set to be smaller than the current loop gain based on the control amount. Control.

Therefore, a control amount corresponding to the initial clock phase deviation is preset, and thereafter, the internal oscillation is controlled in a form in which the preset control amount is subtracted, and the loop gain is further reduced in that state. Since the loop filter is controlled so as to suppress it, it is only necessary to remove only the amount of phase jitter by suppressing the loop filter with the clock frequency error already removed,
For this reason, the performance of following the phase jitter is improved, and the reception performance can be improved while maintaining high system stability.

The reception control device according to the next invention presets the control amount of the internal oscillation circuit based on the phase deviation generated in the initial clock recovery after the start of reception, and sets the phase deviation generated in the clock recovery after the initial clock recovery. When the internal oscillation circuit is controlled based on the control amount, the control is performed by the difference between the current control amount and the preset control amount, and the delay amount is controlled to be smaller than the current delay amount based on the control amount.

Accordingly, the control amount corresponding to the initial clock phase deviation is preset, and thereafter, the internal oscillation is controlled by subtracting the preset control amount, and the loop gain is further reduced in that state. Since the delay amount is controlled so as to suppress it, it is only necessary to remove the phase jitter amount by suppressing the delay amount when the clock frequency error has already been removed, thus improving the tracking performance to the phase jitter As a result, it is possible to improve the reception performance while keeping the stability of the system high.

In the reception control apparatus according to the next invention, in the time division multiplex communication, the control amount of the internal oscillation circuit is preset based on the phase deviation of the clock generated in the initial burst reception after the start of reception, and after the initial clock recovery, When the internal oscillation circuit is controlled based on the phase deviation of the clock generated by the clock regeneration, the control is performed by the difference between the current control amount and the preset control amount.

Therefore, even if the phase deviation of the clock in the first burst reception of the burst reception is to be removed, the steady-state phase deviation is removed at the beginning, and thereafter, the control amount per clock regeneration is greatly increased. Since the system stability is increased by the reduction, it is possible to improve the reception performance while maintaining high system stability even in time division multiplex communication.

In the reception control apparatus according to the next invention, in the time division multiplex communication, the control amount of the internal oscillation circuit is preset based on the phase deviation generated by the clock recovery, and based on the phase deviation generated by the subsequent clock recovery. When controlling the internal oscillation circuit, the control is performed based on the difference between the current control amount and the previously preset control amount.

Therefore, the control amount for the phase deviation of the clock is preset every time a burst is received for the own device, so that the phase deviation is successively removed each time the burst is received, and the burst reception is performed. The clock frequency error gradually decreases. As a result, the control amount per clock recovery is greatly reduced and the stability of the system is increased. Therefore, even in time division multiplex communication, the reception performance can be improved while maintaining high system stability. Will be possible.

The reception control apparatus according to the next invention presets the control amount of the voltage controlled oscillator based on the phase deviation generated in the initial carrier recovery after the start of reception, and sets the phase generated in the carrier recovery after the initial carrier recovery. When controlling the voltage-controlled oscillation circuit based on the deviation, the control is performed using the difference between the current control amount and the preset control amount.

Therefore, the control amount corresponding to the initial phase deviation of the carrier is preset, and thereafter the internal oscillation is controlled in such a manner that the preset control amount is subtracted. This eliminates the need for the operation of removing the signal, and greatly reduces the control amount per carrier wave reproduction, so that it is possible to improve the reception performance while maintaining high system stability.

The reception control apparatus according to the next invention presets the control amount of the voltage controlled oscillator based on the phase deviation generated in the initial carrier recovery after the start of reception, and sets the phase generated in the carrier recovery after the initial carrier recovery. When controlling the voltage-controlled oscillation circuit based on the deviation, control is performed using a difference between the current control amount and a preset control amount, and the loop gain of the loop filter becomes smaller than the current loop gain based on the control amount. Control.

Therefore, a control amount corresponding to the phase deviation of the initial carrier wave is preset, and thereafter, the internal oscillation is controlled by subtracting the preset control amount.
In that state, the loop filter is controlled so as to further reduce the loop gain, so that only the phase jitter amount needs to be removed by suppressing the loop filter in a state where the carrier frequency error has already been removed. Thus, the performance of following the phase jitter is improved, and the reception performance can be improved while maintaining the stability of the system at a high level.

[0030] In a time division multiplex communication, the reception control device according to the next invention presets a control amount of a voltage controlled oscillation circuit based on a phase deviation of a carrier wave generated in initial burst reception after the start of reception, and reproduces an initial carrier wave. When controlling the voltage-controlled oscillation circuit based on the phase deviation of the carrier generated in the subsequent carrier regeneration, the control is performed using the difference between the current control amount and the preset control amount.

Therefore, even if the phase deviation of the carrier in the first burst reception of the burst reception is to be removed, the phase deviation is removed at the initial stage, and thereafter, the control amount per carrier recovery is also greatly reduced. As a result, the stability of the system increases, so that even in time division multiplex communication, it is possible to improve the reception performance while keeping the stability of the system high.

In the reception control apparatus according to the next invention, in time division multiplex communication, the control amount of the voltage controlled oscillation circuit is preset based on the phase deviation generated by carrier recovery, and based on the phase deviation generated by subsequent carrier recovery. When controlling the voltage controlled oscillation circuit by using the control amount, the control is performed based on the difference between the current control amount and the previously preset control amount.

Therefore, the control amount corresponding to the phase deviation of the carrier is preset every time a burst reception for the own device is performed. Therefore, the phase deviation is sequentially removed each time the burst reception is performed. The frequency error of the carrier gradually decreases. As a result, the control amount per carrier wave regeneration is greatly reduced and the stability of the system is increased. Therefore, the reception performance can be improved while maintaining the stability of the system high even in time division multiplex communication. Will be possible.

[0034]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

(Embodiment 1) In this embodiment 1,
A reception control device such as a DLL employing a DS system will be described as an example.

FIG. 1 is a block diagram showing a configuration of a reception control apparatus according to Embodiment 1 of the present invention. In FIG. 1, for example, reference numeral 1 denotes an input terminal for inputting a demodulated signal, which is a received signal; Multiplier for performing multiplication, 4 for an adder for performing addition, 5 for a loop filter for removing high frequency components, 6 for a voltage preset circuit for changing a control voltage value for a VCC oscillation circuit 7 described later, and 7 for a voltage preset circuit 6 VCC oscillation circuit that oscillates VCC according to the control voltage value, 8
Indicates an N-stage feedback shift register that generates a spread code based on VCC and shifts the spread code in accordance with a clock pulse (not shown).

Although not shown, the N-stage feedback shift register 8 includes a spreading code generating circuit for generating a spreading code based on the control voltage value of the VCC oscillation circuit 7, and an N-stage shifting circuit for shifting the spreading code in bit units. And a minute shift register. The shift register is provided with taps 8a and 8b at two places on the way. In the N-stage feedback shift register 8, after the data extracted from each of the taps 8a and 8b is processed through the multipliers 2 and 3, the loop filter 5, the voltage preset circuit 6, and the VCC oscillation circuit 7, the data is again processed. Return to the top position.

Next, clock reproduction will be described. In the reception control device shown in FIG.
A spreading code is supplied from two taps 8a and 8b of the N-stage feedback shift register 8, respectively. That is, the slow spreading code LC is extracted from one of the two taps 8 a and 8 b and output to the multiplier 3. Further, a leading phase spreading code EC is extracted from the other tap 8 a and output to the multiplier 2.

The multipliers 2 and 3 are also supplied with a demodulated signal input to the input terminal 1. Therefore, the multiplier 2,
3 multiplies the common demodulated signal of the PN sequence by a leading spreading code EC and a retarding spreading code LC having different phases, respectively, and adds an advanced correlation value and a delayed correlation value obtained as a result of the multiplication to an adder. 4 is output. Then, the adder 4 combines the input fast correlation value and the late correlation value, and supplies the combined output to the loop filter 5.

When the combined output of the adder 4 becomes zero, the phase of the clock frequency generated on the receiving side (own apparatus) is synchronized with the phase of the clock frequency on the transmitting side (not shown).
This corresponds to the removal of the phase deviation. When the combined output takes a value other than zero, the adder 4
Generates a DC voltage proportional to the amount of phase shift detected by the voltage preset circuit 6, and outputs this to the loop filter 5 as a phase deviation signal. In this case, the loop filter 5 removes high-frequency components from the input phase deviation signal and outputs the same to the voltage preset circuit 6 at the subsequent stage.

In the voltage preset circuit 6, the control voltage value of the VCC oscillation circuit 7 is obtained according to the following equations (1) to (3). That is, p (1) = p (0) + Δm (0) (1) p (0) → p (1) (2) p (t) = p (1) + Δn (t) ·・ ・ (3)

In the above formulas (1) to (3), p (0)
Is a control voltage value in the first uncontrolled state of the VCC oscillation circuit 7, p (1) is a control voltage value in the uncontrolled state to be preset, and Δm (0) is a voltage value generated from the loop filter 5 by the demodulated signal first. , P (t) is the control voltage value generated after presetting, and Δn (t) is the value from the loop filter 5 generated by the demodulated signal after presetting. And the control voltage value p (t) of the VCC oscillation circuit 7 are shown.

The voltage preset circuit 6 obtains the control voltage value p (t) according to the procedures of the above equations (1) to (3), and according to the control voltage value p (t), the VCC oscillation circuit 7
Drive control.

The VCC oscillation circuit 7 adjusts the output of the VCC based on the control voltage value p (t) received from the voltage preset circuit 6 so that the combined output of the adder 4 becomes zero. The N-stage feedback shift register 8 includes a VCC oscillation circuit 7
When the supply of the adjusted VCC is received from the power supply, it outputs the leading spread code EC and the late spread code LC based on the VCC to the multiplier 2 and the multiplier 3, respectively.

As described above, according to the first embodiment, at the time of the first synchronization pull-in, the voltage preset circuit 6 presets the control amount corresponding to the initial steady-state phase deviation. Drive control of the VCC oscillating circuit 7 with the control amount subtracted. That is, it is not necessary to remove the steady-state phase deviation between the wireless transmission / reception devices every time the clock is recovered. This makes the processing and time in the clock recovery more efficient, and also reduces the steady-state phase deviation due to the phase jitter of the transmission path. , It is possible to remove while maintaining the stability of the system.

Accordingly, when the steady-state phase deviation is reduced, the control amount per clock recovery is also greatly reduced, and the stability of the system is increased. Therefore, the reception performance is improved while maintaining the stability of the system at a high level. It becomes possible.

(Embodiment 2) Also in this embodiment 2,
Similar to the first embodiment, a description will be given of a reception control device such as a DLL adopting the DS system as an example.

FIG. 2 is a block diagram showing a configuration of a reception control apparatus according to a second embodiment of the present invention. In FIG. 2, for example, reference numeral 11 denotes an input terminal for inputting a demodulated signal which is a received signal; A multiplier that performs multiplication, 14 is an adder that performs addition, 15 is a variable loop filter for removing a high-frequency component that changes a loop gain under the control of a loop filter setting circuit 17 described later, and 16 is a VCC oscillation circuit 1
A voltage preset circuit for changing the control voltage value for 8;
A loop filter setting circuit 17 controls the loop gain of the variable loop filter 15, a VCC oscillation circuit 18 oscillates VCC according to a control voltage value of the voltage preset circuit 16, and 19 generates a spreading code based on VCC and spreads the code. An N-stage feedback shift register that shifts a code according to a clock pulse (not shown) is shown.

The N-stage feedback shift register 19 has a spread code generating circuit and a shift register (not shown) as in the first embodiment, and taps 19a and 19a are provided at two places in the shift register, respectively. 19b is provided. In this N-stage feedback shift register 19, each tap 1
9a and 19b are output from the multiplier 12,
13, variable loop filter 15, voltage preset circuit 1
6, and after being processed through the VCC oscillation circuit 18,
It returns to the head position again.

Next, clock reproduction will be described. In the reception control device shown in FIG. 2, two taps 19 of an N-stage feedback shift register 19 are provided to multipliers 12 and 13.
The spreading codes are supplied from a and 19b, respectively. That is, the slow spreading code LC is extracted from one of the two taps 19 a and 19 b and output to the multiplier 13. Further, the leading phase spreading code EC is taken out from the other tap 19 a and output to the multiplier 12.

The multipliers 12 and 13 have input terminals 1
The demodulated signal input to 1 is also supplied. For this reason, the multipliers 12 and 13 respectively provide a leading spread code EC and a late spread code L having different phases to the common demodulated signal of the PN sequence.
C, and outputs the result of the multiplication to the adder 14 as a leading correlation value and a lagging correlation value. And the adder 14
Synthesizes the input early correlation value and the late correlation value,
The combined output is supplied to the variable loop filter 15.

When the combined output of the adder 14 becomes zero,
This means that the phase of the clock frequency generated on the receiving side (own apparatus) is synchronized with the phase of the clock frequency on the transmitting side (not shown). When the combined output takes a value other than zero, the adder 14 generates a DC voltage proportional to the amount of deviation detected by the voltage preset circuit 16, and uses the generated DC voltage as a phase deviation signal as a variable loop filter. 15 is output. In this case, the variable loop filter 15 removes high-frequency components from the input phase deviation signal, and outputs the same to the subsequent voltage preset circuit 16.

The voltage preset circuit 16 obtains the control voltage value p (t) of the VCC oscillation circuit 18 according to the procedures of the above-described equations (1) to (3), similarly to the first embodiment, and VCC oscillation circuit 1 according to voltage value p (t)
8 is drive-controlled.

In the second embodiment, a loop filter setting circuit 17 is connected to the output of the voltage preset circuit 16. The loop filter setting circuit 17 generates a loop gain control signal LG based on the control voltage value p (t) in the uncontrolled state output from the voltage preset circuit 16 so that the loop gain becomes smaller than the current loop gain. This is output to the variable loop filter 15.

At this time, upon receiving the loop gain control signal LG, the variable loop filter 15 lowers the combined output output from the adder 14 based on the loop gain control signal LG so that the loop gain is further reduced. And supplies it to the voltage preset circuit 16.

The VCC oscillating circuit 18 operates so that the combined output of the adder 24 becomes zero based on the control voltage value p (t) received from the voltage preset circuit 16.
Adjust the output of. The control voltage value p (t) input to the VCC oscillating circuit 18 is determined by the processing between the variable loop filter 15, the voltage preset circuit 16, and the loop filter setting circuit 17 in the uncontrolled state. Is obtained.

The N-stage feedback shift register 19
Upon receiving the supply of the adjusted VCC from the VCC oscillation circuit 18, it outputs the leading spread code EC and the slow spreading code LC based on the VCC to the multipliers 12 and 13, respectively.

As described above, according to the second embodiment, at the time of the first synchronization pull-in, the voltage preset circuit 16 determines the control voltage value p (t) for the initial steady-state phase deviation, and then sets the loop filter setting circuit. At 17 the control voltage value p
Since the variable loop filter 15 is controlled to further reduce the loop gain based on (t), only the amount of phase jitter is removed by suppressing the variable loop filter 15 in a state where the clock frequency error has already been removed. It becomes possible. Therefore, the follow-up performance to the phase jitter is improved, so that it is possible to improve the reception performance while keeping the stability of the system high.

Also in the second embodiment, similarly to the first embodiment, when the steady-state phase deviation is reduced, the control amount per clock regeneration is greatly reduced, and the stability of the system is increased. Therefore, it is possible to remove the steady phase deviation due to the phase jitter of the transmission line while maintaining the stability of the system.

(Embodiment 3) Also in this embodiment 3,
Similar to the first embodiment, a description will be given of a reception control device such as a DLL adopting the DS system as an example.

FIG. 3 is a block diagram showing the configuration of a reception control apparatus according to Embodiment 3 of the present invention. In FIG. 3, for example, reference numeral 21 denotes an input terminal for inputting a demodulated signal which is a received signal; A multiplier for performing multiplication; 24, an adder for performing addition; 25, a loop filter for removing high-frequency components; 26, a voltage preset circuit for changing a control voltage value for a VCC oscillation circuit 28; 29 is a delay amount setting circuit that changes the amount of phase delay (the phase difference between the early spread code and the late spread code) by switching the output tap position of 29, and 28 is the voltage preset circuit 2
A VCC oscillation circuit that oscillates VCC according to the control voltage value of 6, and 29 denotes an N-stage feedback shift register that generates a spread code based on VCC and shifts the spread code in accordance with a clock pulse (not shown). .

The N-stage feedback shift register 29 includes a spreading code generator (not shown) and an N
And a shift register for each stage. The shift register includes taps 29-1 to 29-2 in N-stage registers, respectively.
9-N. The output tap positions of the leading spread code and the slow spreading code are set according to the tap switching signal TS supplied from the delay amount setting circuit 2727 among the taps 29-1 to 29-N. Switch. Here, the output tap position of the early spread code is set to tap 29a, and the output tap position of the late spread code is set to tap 29b.

In the N-stage feedback shift register 29, the data extracted from each tap 29a, 29b is
2, 23, loop filter 25, voltage preset circuit 2
6, and after being processed through the VCC oscillation circuit 28,
It returns to the head position again.

Next, clock reproduction will be described. In the reception control device shown in FIG. 3, two taps 29 of an N-stage feedback shift register 29 are provided to multipliers 22 and 23.
The spreading codes are supplied from a and 29b. That is, the slow spreading code LC is extracted from one of the two taps 29 a and 29 b and output to the multiplier 23. Further, the leading phase spreading code EC is taken out from the other tap 29 a and output to the multiplier 22.

The multipliers 22 and 23 have input terminals 1
The demodulated signal input to 1 is also supplied. For this reason, the multipliers 22 and 23 respectively provide the leading spread code EC and the late spread code L having different phases to the common demodulated signal of the PN sequence.
C, and outputs the result of the multiplication as an early phase correlation value and a late phase correlation value to the adder 24. And the adder 14
Synthesizes the input early correlation value and the late correlation value,
The combined output is supplied to the variable loop filter 25.

When the combined output of the adder 24 becomes zero,
This means that the clock frequency generated on the receiving side (own apparatus) is synchronized with the clock frequency on the transmitting side (not shown). If the combined output takes a value other than zero, the adder 24
Generates a DC voltage proportional to the amount of deviation detected by the voltage preset circuit 26, and outputs this to the loop filter 25 as a phase deviation signal. In this case, the loop filter 25 removes high-frequency components from the input phase deviation signal, and outputs the same to the voltage preset circuit 26 in the subsequent stage.

In the voltage preset circuit 26, as in the first embodiment, the control voltage value p (t) of the VCC oscillation circuit 28 is obtained by the procedures of equations (1) to (3), and the control voltage value The driving of the VCC oscillation circuit 28 is controlled according to p (t).

In the third embodiment, a delay amount setting circuit 27 is connected to the output of the voltage preset circuit 26,
The delay amount setting circuit 27 changes the setting of the delay amount based on the control voltage value p (t) in the uncontrolled state output from the voltage preset circuit 26 so that the loop gain becomes smaller than the current loop gain. . Specifically, the delay amount setting circuit 27 generates a tap switching signal TS based on the delay amount to be changed, and transmits the tap switching signal TS to the N-stage feedback shift register 2.
9 is output.

Upon receiving the tap switching signal TS, the N-stage feedback shift register 29 receives the tap switching signal TG.
The output tap position is switched based on. This allows
Since the phase difference between the early spreading code and the late spreading code output to the multipliers 22 and 23 changes, the adder 24 outputs the early correlation value and the late correlation code in a form in which the setting of the delay amount is changed. Synthesis with the value is performed. The loop gain is suppressed to be small by the combination of the adder 24, and the combined output is supplied to the voltage preset circuit 26 via the loop filter 25 at the subsequent stage.

The VCC oscillating circuit 28 sets the VCC output so that the combined output of the adder 24 becomes zero based on the control voltage value p (t) received from the voltage preset circuit 26.
Adjust the output of. The control voltage value p (t) input to the VCC oscillation circuit 28 is, in the uncontrolled state, a preset control voltage value and a loop gain of the loop filter 25, the voltage preset circuit 26, and the delay amount setting circuit 27 during processing. This results in reduction.

The N-stage feedback shift register 29
When the regulated VCC is supplied from the VCC oscillation circuit 28, the leading spreading code E of the spreading code based on the VCC is received.
C and the slow spreading code LC are respectively applied to the multiplier 22 and the multiplier 2
Output to 3.

As described above, according to the third embodiment, at the time of the first synchronization pull-in, the voltage preset circuit 26 determines the control voltage value p (t) for the initial steady-state phase deviation, and the delay amount setting circuit 27 Since the delay amount of the N-stage feedback shift register 29 is controlled based on the control voltage value p (t) so as to further reduce the loop gain, the control of the phase jitter amount also functions by suppressing the loop gain. Thus, the performance of following the phase jitter is improved.

Also, in the third embodiment, as in the first embodiment, when the steady-state phase deviation is reduced, the control amount per clock regeneration is greatly reduced, and the stability of the system is increased. Therefore, it is possible to remove the steady phase deviation due to the phase jitter of the transmission line while maintaining the stability of the system. As a result, it is possible to improve the reception performance while keeping the stability of the system high.

(Embodiment 4) The above-described Embodiments 1 to
3 is a time-division multiplex communication described below (hereinafter, TDMA
). Therefore, in the fourth embodiment, the above-described voltage preset circuits 6, 16,
26 shows an example in the case where H.26 is applied to TDMA.

FIG. 4 is a diagram for explaining a method of removing a stationary phase deviation according to the fourth embodiment of the present invention. TDMA is
As shown in FIG. 4, this system transmits a burst signal of a wireless transmission device to slots ch1... Assigned to a plurality of reception control devices.

In the voltage preset circuit according to the fourth embodiment, for example, when the slot ch1 is allocated to the own device, the first slot SL1 establishes a connection between the transmission partner (radio transmitting device) and the own device (reception control device). The stationary phase deviation (clock frequency error) is read, the clock frequency of the own device is corrected based on the stationary phase deviation, and the stationary phase deviation is removed. Thus, it is possible to prepare for the next burst reception (slot SL2).

As described above, according to the fourth embodiment, TD
In the application to the MA, the stationary phase deviation in the first slot of the burst reception is to be removed. In this case as well, the stationary phase deviation is initially set in common with the effects of the first to third embodiments. Since it is removed, the control amount per clock regeneration is greatly reduced thereafter, and the stability of the system increases, so that it is possible to improve the reception performance while maintaining the stability of the system at a high level. .

(Embodiment 5) In Embodiment 5, the reception control apparatus according to Embodiment 1 is applied to TDMA.

FIG. 5 is a block diagram showing a configuration of a reception control apparatus according to Embodiment 5 of the present invention. In FIG. 5, for example, reference numeral 31 denotes an input terminal for inputting a demodulated signal obtained by demodulating a received burst signal; 33 is a multiplier that performs multiplication, 34 is an adder that performs addition, 35 is a loop filter that removes high-frequency components, and 36 is a VCC oscillation circuit 3 described later.
7 is a sequential voltage preset circuit that changes the control voltage value for each time a burst is received in its own slot, 37 is a VCC oscillation circuit that oscillates VCC according to the control voltage value of the sequential voltage preset circuit 36, and 38 is a spread based on VCC. An N-stage feedback shift register for generating a code and shifting the spread code according to a clock pulse (not shown) is shown.

Although not shown, the N-stage feedback shift register 38 includes a spread code generation circuit for generating a spread code based on the control voltage value of the VCC oscillation circuit 37, and an N-stage shift circuit for shifting the spread code in bit units. And a minute shift register. The shift register is provided with taps 38a and 38b at two places on the way. In this N-stage feedback shift register 38, each tap 3
8a and 38b are output from the multiplier 32,
33, a loop filter 35, a voltage preset circuit 36,
Then, after being processed through the VCC oscillation circuit 37, it returns to the head position again.

Next, clock reproduction will be described. In the reception control device shown in FIG. 5, two taps 38 of an N-stage feedback shift register 38 are provided to multipliers 32 and 33.
The spreading codes are supplied from a and 38b, respectively. That is, the slow spreading code LC is extracted from one of the two taps 38 a and 38 b and output to the multiplier 33. Further, a leading spread code EC is extracted from the other tap 38 a and output to the multiplier 32.

The multipliers 32 and 33 have input terminals 3
The demodulated signal input to 1 is also supplied. For this reason, the multipliers 32 and 33 respectively provide the leading spread code EC and the late spread code L having different phases to the common demodulated signal of the PN sequence.
C, and outputs the result of the multiplication as an early phase correlation value and a late phase correlation value to the adder 34. And the adder 34
Synthesizes the input early correlation value and the late correlation value,
The combined output is supplied to the loop filter 35.

When the combined output of the adder 34 becomes zero,
This means that the clock frequency generated on the receiving side (own apparatus) is synchronized with the clock frequency on the transmitting side (not shown). If the combined output takes a value other than zero, the adder 34
Generates a DC voltage proportional to the amount of deviation detected by the voltage preset circuit 36, and outputs this to the loop filter 35 as a phase deviation signal. In this case, the loop filter 35 removes high-frequency components from the input phase deviation signal and outputs the same to the subsequent sequential voltage preset circuit 36.

In the sequential voltage preset circuit 36, the equations (1) to (3) are used, as in the first embodiment.
The control voltage value p (t) of the VCC oscillation circuit 37 is
Is required. That is, the sequential voltage preset circuit 36 presets the sequential control voltage value at the time of the burst reception in the own slot.

The VCC oscillation circuit 37 adjusts the output of the VCC based on the control voltage value p (t) received from the sequential voltage preset circuit 6 so that the combined output of the adder 4 becomes zero. When the N-stage feedback shift register 38 receives the supply of the adjusted VCC from the VCC oscillation circuit 7, the N-stage feedback shift register 38 outputs the leading spread code EC and the slow spreading code LC based on the VCC to the multiplier 32 and the multiplier 33, respectively. .

As described above, according to the fifth embodiment, the control amount for the steady-state phase deviation is preset by the successive voltage preset circuit 36 every time a burst is received for the own device. Since the system is based on the premise, the steady phase deviation is successively removed each time a burst is received. As a result, it becomes possible to gradually reduce the clock frequency error every time a burst is received. This is similar to the first embodiment described above, in that the control amount per clock recovery is greatly reduced and the stability of the system is increased. Can be improved while maintaining a high level.

(Embodiment 6) In Embodiment 6, the reception control apparatus according to Embodiment 1 described above is applied to a Costas loop type carrier recovery circuit.

FIG. 6 is a block diagram showing a configuration of a reception control apparatus according to Embodiment 6 of the present invention. In FIG. 6, for example, reference numeral 41 denotes an intermediate frequency band signal (hereinafter referred to as IF (Intermediate) signal of a received carrier signal). Frequency) signal, an IF input terminal for receiving a demodulated signal obtained by demodulating the signal,
Reference numeral 42 denotes a 90 ° phase shifter which gives a 90 ° phase difference to an output of a voltage controlled oscillation circuit (hereinafter referred to as a VCO) 48 and outputs the same to a mixer 43B described later.
A mixer for demodulating the signal by 90 ° out of phase, 44
A and 44B are low-pass filters (hereinafter referred to as LPFs) for removing high-frequency components, 45 is a phase comparator for comparing phases by multiplication, 46 is a loop filter for removing high-frequency components, and 47 is a control voltage value for a VCO 48 described later. , A reference numeral 48 denotes a VCO which oscillates a local oscillator signal in accordance with a control voltage value of the voltage preset circuit 47.

Next, carrier wave reproduction for reproducing the frequency phase of a carrier wave between transmission and reception will be described. In the Costas loop type carrier recovery circuit shown in FIG.
Is branched into two systems, one of which is output to the mixer 43A and the other is output to the mixer 43B. In these mixers 43A and 43B, a local oscillator signal is supplied from the VCO 48, so that demodulation based on the input IF signal is performed. At this time, since the 90 ° phase shifter 42 is coupled between the VCO 48 and the mixer 43B, the input IF signal of the mixer 43B has a 90 ° phase difference from the local oscillator signal of the mixer 43A. Demodulated by the local oscillator signal.

The signals demodulated by the mixers 43A and 43B are output to LPFs 44A and 44B, respectively, and high-frequency components are removed from the input signals in order to limit the band. The signals output from the LPFs 44A and 44B are multiplied by a phase comparator 45, and the multiplication result is further output to a loop filter 46 as a phase deviation signal. In the loop filter 46, high frequency components are removed from the input phase deviation signal.

When the output of the phase comparator 45, that is, the phase deviation signal becomes zero, it means that the carrier frequency generated on the receiving side (own apparatus) is synchronized with the carrier frequency on the transmitting side (not shown). If the phase deviation signal takes a value other than zero, the phase comparator 45 generates a DC voltage proportional to the amount of deviation detected by the voltage preset circuit 47, and uses this as a phase deviation signal. Output to the filter 46. In this case, the loop filter 46 removes high-frequency components from the input phase deviation signal, and outputs the same to the subsequent voltage preset circuit 47.

In the voltage preset circuit 47, the control voltage value of the VCO 48 is obtained according to the following equations (4) to (6). That is, q (1) = q (0) + Δu (0) (4) q (0) → q (1) (5) q (t) = q (1) + Δv (t) ·・ ・ (6)

In the above formulas (1) to (3), q (0)
Is the control voltage value in the first uncontrolled state of the VCO 48,
q (1) is a preset control voltage value in an uncontrolled state, Δ
u (0) is the difference between the voltage value from the loop filter 46 initially generated by the demodulated signal and the control voltage value in the first uncontrolled state of the VCO 48, q (t) is the control voltage value generated after presetting, and Δv ( t) is the voltage value from the loop filter 46 generated by the demodulated signal after preset and V
The difference from the control voltage value q (t) of the CO 48 is shown.

The voltage preset circuit 47 obtains the control voltage value q (t) according to the procedures of the above equations (4) to (6), and drives and controls the VCO 48 according to the control voltage value q (t).

The VCO 48 adjusts the local oscillator signal based on the control voltage value q (t) received from the voltage preset circuit 47 so that the phase deviation signal of the phase comparator 45 becomes zero.

As described above, according to the sixth embodiment, at the time of the first synchronization pull-in, the voltage preset circuit 47 presets the control amount corresponding to the frequency phase deviation of the initial carrier wave. The drive control of the VCO 48 with the preset control amount subtracted is sufficient. In other words, the operation of removing the frequency phase deviation between the radio transmitting and receiving apparatuses is not required every time the carrier wave is reproduced. This makes the processing and the time in the carrier wave recovery more efficient, and also reduces the steady phase deviation due to the phase jitter of the transmission path. , It is possible to remove while maintaining the stability of the system.

Therefore, when the carrier phase deviation becomes small,
The control amount per carrier wave regeneration is also greatly reduced, and the stability of the system is increased. Therefore, it is possible to improve the reception performance while maintaining high stability of the system.

(Embodiment 7) In Embodiment 7, the reception control apparatus according to Embodiment 1 is applied to a Costas loop type carrier recovery circuit.

FIG. 7 is a block diagram showing a configuration of a reception control apparatus according to Embodiment 7 of the present invention. In FIG. 7, for example, reference numeral 51 denotes a demodulated signal obtained by demodulating an IF signal of a received carrier signal. IF input terminal 52, 90 ° phase shifters 53A, 53B for giving a 90 ° phase difference to the output of VCO 59 to be described later and outputting the same to mixer 53B to be described later
Is a mixer that demodulates the IF signal by 90 ° out of phase,
54A and 54B are LPFs for removing high-frequency components, 55 is a phase comparator for comparing phases by multiplication, 56 is a loop filter for removing a high-frequency component according to the control of a loop filter 58 described later, and 57 is described later. A voltage preset circuit that changes the control voltage value for the VCO 59, a loop filter circuit 58 that controls the loop gain of the variable loop filter 56, and a VCO 59 that oscillates a local oscillator signal according to the control voltage value of the voltage preset circuit 57 are shown. I have.

Next, carrier wave reproduction will be described. FIG.
In the Costas loop type carrier recovery circuit shown in FIG.
The IF signal input to the input terminal 51 is branched into two systems, one is output to the mixer 53A, and the other is output to the mixer 53A.
B. These mixers 53A and 53B have V
When the local oscillator signal is output from the CO 58, the IF
Demodulation based on the signal is performed. At this time, since the 90 ° phase shifter 52 is coupled between the VCO 58 and the mixer 53B, the input IF signal of the mixer 53B has a 90 ° phase difference from the local oscillator signal of the mixer 53A. Demodulated by the local oscillator signal.

The signals demodulated by mixers 53A and 53B are output to LPFs 54A and 54B, respectively, and high-frequency components are removed from the input signals in order to limit the band. The signals output from the LPFs 54A and 54B are multiplied by a phase comparator 55, and the multiplication result is further output to a loop filter 56 as a phase deviation signal. The loop filter 56 removes high frequency components from the input phase deviation signal.

When the output of the phase comparator 55, that is, the phase deviation signal becomes zero, it means that the carrier frequency generated on the receiving side (own apparatus) is synchronized with the carrier frequency on the transmitting side (not shown). If the phase deviation signal takes a value other than zero, the phase comparator 55 generates a DC voltage proportional to the amount of deviation detected by the voltage preset circuit 57, and uses this as a phase deviation signal. Output to the filter 56. In this case, the loop filter 56 removes a high-frequency component from the input phase deviation signal and outputs the same to the voltage preset circuit 57 at the subsequent stage.

The voltage preset circuit 57 obtains the control voltage value q (t) of the VCO 59 by the procedures of the above-described equations (4) to (6), as in the sixth embodiment, and obtains the control voltage value q The drive of the VCO 59 is controlled according to (t).

In the seventh embodiment, a loop filter setting circuit 58 is connected to the output of the voltage preset circuit 57. The loop filter setting circuit 58 generates the loop gain control signal LG based on the control voltage value q (t) in the uncontrolled state output from the voltage preset circuit 57 so that the loop gain becomes smaller than the current loop gain. This is output to the variable loop filter 56.

At this time, upon receiving the loop gain control signal LG, the variable loop filter 56 converts the phase deviation signal output from the phase comparator 55 based on the loop gain control signal LG so that the loop gain is further reduced. , And supplies it to a voltage preset circuit 57.

The VCO 59 adjusts the local oscillator signal based on the control voltage value q (t) received from the voltage preset circuit 57 so that the phase deviation signal of the phase comparator 55 becomes zero.

As described above, according to the seventh embodiment, at the time of the first synchronization pull-in, the voltage preset circuit 56 controls the control voltage value q (t) with respect to the initial frequency phase deviation of the carrier.
Is obtained, the variable loop filter 56 is controlled by the loop filter setting circuit 58 based on the control voltage value q (t) so as to further reduce the loop gain, so that the frequency phase error has already been removed. Thus, only the amount of phase jitter can be removed by the suppression of the variable loop filter 56 in the above. Therefore, the follow-up performance to the phase jitter is improved, so that it is possible to improve the reception performance while keeping the stability of the system high.

Also, in the seventh embodiment, as in the sixth embodiment, when the frequency / phase deviation becomes small,
The control amount per carrier wave regeneration is also greatly reduced, and the system stability is increased, so it is possible to remove the frequency phase deviation due to the phase jitter of the transmission line while maintaining the system stability. Become.

(Eighth Embodiment) The sixth embodiment described above.
7 can also be applied to the TDMA described below. Therefore, the eighth embodiment shows an example in which the above-described voltage preset circuits 47 and 57 are applied to TDMA.

In the voltage preset circuit according to the eighth embodiment, similarly to the fourth embodiment, for example, the slot ch
When 1 is assigned (see FIG. 4), a frequency phase deviation between the transmission partner (wireless transmission device) and the own device (reception control device) is read in the first slot SL1, and based on the frequency phase deviation. Compensate your carrier frequency,
The frequency phase deviation is removed. Thus, it is possible to prepare for the next burst reception (slot SL2).

As described above, according to the eighth embodiment, similarly to the fourth embodiment, in the application to TDMA, the frequency phase deviation of the carrier in the first slot of the burst reception is to be removed. In addition, since the frequency and phase deviations are initially removed in common with the effects of the above-described sixth and seventh embodiments, the control amount per carrier wave recovery is greatly reduced, and the system Since the stability is increased, it is possible to improve the reception performance while keeping the stability of the system high.

(Embodiment 9) Embodiment 9 is an application of the reception control apparatus according to Embodiment 6 described above to TDMA.

FIG. 8 is a block diagram showing a configuration of a reception control apparatus according to Embodiment 9 of the present invention. In FIG. 8, for example, reference numeral 61 denotes a demodulated signal obtained by demodulating an IF signal of a received carrier signal. An IF input terminal 62 is a 90 ° phase shifter that gives a 90 ° phase difference to an output of a VCO 68 described later and outputs the same to a mixer 63B described later.
Is a mixer that demodulates the IF signal by 90 ° out of phase,
64A and 64B are LPFs for removing high-frequency components, 65 is a phase comparator for comparing phases by multiplication, 66 is a loop filter for removing high-frequency components, and 67 is a VCO 6 to be described later.
Reference numeral 68 denotes a sequential voltage preset circuit for changing the control voltage value for each burst reception to the own slot, and reference numeral 68 denotes a VCO for oscillating a local oscillator signal in accordance with the control voltage value of the voltage preset circuit 67.

Next, clock reproduction will be described. In the reception control device shown in FIG. 8, the IF signal input to the IF input terminal 61 is split into two systems, one of which is a mixer 63.
A, and the other is output to mixer 63B. The local oscillator signal is output from the VCO 68 to these mixers 63A and 63B, and demodulation based on the IF signal is performed.
At this time, since the 90 ° phase shifter 62 is coupled between the VCO 68 and the mixer 63B, the input IF signal in the mixer 63B has a 90 ° phase difference with the local oscillator signal from the mixer 63A. Demodulated by the local oscillator signal.

The signals demodulated by mixers 63A and 63B are output to LPFs 64A and 64B, respectively, and high-frequency components are removed in order to limit the band. LPF64A,
The signal output from 64B is multiplied by a phase comparator 65, and the multiplication result is further output to a loop filter 66 as a phase deviation signal, where high-frequency components are removed.

When the output of the phase comparator 65, that is, the phase deviation signal becomes zero, it means that the clock frequency generated on the receiving side (own apparatus) is synchronized with the demodulated signal received from the transmitting side (not shown). When the phase deviation signal takes a value other than zero, the phase comparator 65 generates a DC voltage proportional to the amount of deviation detected by the voltage preset circuit 67, and uses this as a phase deviation signal. Loop filter 6
6 is output. In this case, the loop filter 66 removes high-frequency components from the input phase deviation signal and outputs the same to the subsequent sequential voltage preset circuit 67.

In this sequential voltage preset circuit 67, the equations (4) to (6) are used in the same manner as in the sixth embodiment.
The control voltage value of the VCO 68 is obtained by the procedure described above. That is, the sequential voltage preset circuit 67 presets the sequential control voltage value at the time of the burst reception in the own slot.

The VCO 68 includes a sequential voltage preset circuit 6
Based on the control voltage value q (t) received from 7, the local oscillator signal is adjusted so that the phase deviation signal of the phase comparator 65 becomes zero.

As described above, according to the ninth embodiment, the control amount for the steady-state phase deviation is preset by the sequential voltage preset circuit 67 every time a burst is received.
Since DMA is a system premised on burst communication, steady phase deviation is sequentially removed each time burst reception is performed. As a result, the clock frequency error of the carrier is gradually reduced every time burst reception is performed. It is possible to go. This is similar to the above-described sixth embodiment, in that the control amount per clock recovery is greatly reduced and the stability of the system is increased. Can be improved while maintaining a high level.

(Embodiment 10) In Embodiment 10, a reception control device employing an FH system will be described as an example.

FIG. 9 is a block diagram showing the configuration of a reception control apparatus according to Embodiment 10 of the present invention. In FIG. 9, for example, reference numeral 71 denotes an IF input terminal for inputting an IF signal;
72A and 72B are multipliers for performing multiplication, 73A and 73B are detectors for performing demodulation by detection for primary modulation, 74 is an adder for adding, 75 is a loop filter for removing high-frequency components, and 76 is a VCC oscillation to be described later. A voltage preset circuit for changing a control voltage value for the circuit 77; 77, a VCC oscillation circuit for oscillating VCC according to the control voltage value of the voltage preset circuit 76; 78, a spread code generated based on VCC; N-stage feedback shift register for shifting in accordance with the clock pulse of
Denotes frequency synthesizers that generate local oscillation signals for frequency conversion on the receiving side.

Although not shown, the N-stage feedback shift register 78 generates a hopping frequency signal based on the control voltage value of the VCC oscillation circuit 77, and shifts the hopping frequency signal in bit units. N stages of shift registers are connected. The shift register is provided with taps 78a and 78b at two places on the way, respectively, and is connected to frequency synthesizers 79A and 79B, respectively.

In the N-stage feedback shift register 78, the data extracted from each of the taps 78A and 78B is transmitted to the frequency synthesizers 79A and 79B, the multipliers 72A and 72B, the detectors 73A and 73B, the adder 74, and the loop filter 7.
5. Voltage preset circuit 76 and VCC oscillation circuit 77
, And returns to the head position again.

Next, clock reproduction will be described. In the reception control device shown in FIG. 9, two taps 7 of an N-stage feedback shift register 78 are provided to multipliers 72A and 72B.
The hopping frequency signals are supplied from 8a and 78b, respectively. Before the supply, the hopping frequency signals are frequency-converted by the frequency synthesizers 79A and 79B. Note that, out of the two taps 78a and 78b, the slow spreading code LC is extracted from one of the taps 78b, and is output to the frequency synthesizer 79B. Further, the leading spread code EC is extracted from the other tap 78a,
This is output to the frequency synthesizer 79A.

The IF signals input to the IF input terminal 71 are also supplied to the multipliers 72A and 72B. For this reason, the multipliers 72A and 72B multiply the common IF signal by the early spread code EC and the late spread code LC having different phases, respectively, and obtain a result of the multiplication, that is, a fast correlation value and a slow correlation value. Are demodulated by detectors 73A and 73B, respectively, and output to adder 74. Then, the adder 74 combines the demodulated early phase correlation value and the delayed phase correlation value, and supplies the combined output to the loop filter 75.

When the combined output of the adder 74 becomes zero,
This means that the clock frequency generated on the receiving side (own apparatus) is synchronized with the clock frequency on the transmitting side (not shown). If the combined output takes a value other than zero, the adder 74
Generates a DC voltage proportional to the amount of deviation detected by the voltage preset circuit 77, and outputs this to the loop filter 75 as a phase deviation signal. In this case, the loop filter 75 removes a high-frequency component from the input phase deviation signal and outputs the same to the voltage preset circuit 76 at the subsequent stage.

The voltage preset circuit 76 obtains the control voltage value p (t) of the VCC oscillation circuit 77 by the procedure of the above-described equations (1) to (3), as in the first embodiment, and VCC oscillation circuit 7 according to voltage value p (t)
7 is drive-controlled.

The VCC oscillation circuit 77 adjusts the output of the VCC based on the control voltage value p (t) received from the voltage preset circuit 76 so that the combined output of the adder 74 becomes zero. When the N-stage feedback shift register 78 receives the supply of the adjusted VCC from the VCC oscillation circuit 77, the N-stage feedback shift register 78 outputs a leading spread code EC and a slow spreading code LC based on the VCC.
Are output to the frequency synthesizers 79A and 79B, respectively.

As described above, according to the tenth embodiment, at the time of the first synchronization pull-in, the control amount for the initial steady-state phase deviation is preset by the voltage preset circuit 76. Drive control of the VCC oscillation circuit 77 in a form in which the control amount is subtracted. That is, it is not necessary to remove the steady-state phase deviation between the wireless transmission / reception devices every time the clock is recovered. This makes the processing and time in the clock recovery more efficient, and also reduces the steady-state phase deviation due to the phase jitter of the transmission path. , It is possible to remove while maintaining the stability of the system.

Accordingly, when the steady-state phase deviation is reduced, the control amount per clock reproduction is also greatly reduced, and the stability of the system is increased. Therefore, the receiving performance is improved while maintaining the stability of the system at a high level. It becomes possible.

[0131]

As described above, according to the present invention, the control amount corresponding to the initial clock phase deviation is preset, and thereafter, the internal oscillation is controlled in such a manner that the preset control amount is subtracted. This eliminates the need to remove the phase deviation every time the clock is recovered, and greatly reduces the amount of control per clock recovery, thus improving the reception performance while maintaining high system stability. There is an effect that a reception control device capable of causing the reception can be obtained.

According to the next invention, the control amount corresponding to the phase deviation of the initial clock is preset, and thereafter the internal oscillation is controlled by subtracting the preset control amount. Since the loop filter is controlled so as to further reduce the loop gain, it is only necessary to remove the phase jitter amount by suppressing the loop filter in a state where the clock frequency error has already been removed. Is improved, and the reception control device capable of improving the reception performance while keeping the stability of the system high can be obtained.

According to the next invention, the control amount corresponding to the phase deviation of the initial clock is preset, and thereafter, the internal oscillation is controlled by subtracting the preset control amount. Since the amount of delay is controlled so as to keep the loop gain even smaller, it is only necessary to remove only the amount of phase jitter by suppressing the amount of delay when the clock frequency error has already been removed. Is improved, and the reception control device capable of improving the reception performance while keeping the stability of the system high can be obtained.

According to the next invention, in the time division multiplex communication, even if the phase deviation of the clock in the first burst reception of the burst reception is to be removed, the phase deviation is removed at the initial stage. Since the control amount per playback is greatly reduced and the system stability increases, a reception control device that can improve the reception performance while maintaining high system stability even in time division multiplex communication. The effect is obtained.

According to the next invention, in the time-division multiplex communication, the control amount corresponding to the phase deviation of the clock is preset every time a burst reception for the own device is performed. The removal is performed, and the clock frequency error gradually decreases each time the burst is received. As a result, the control amount per clock recovery is greatly reduced and the stability of the system is increased. Therefore, even in time division multiplex communication, the reception performance can be improved while maintaining high system stability. There is an effect that a possible reception control device can be obtained.

According to the next invention, the control amount corresponding to the initial carrier phase deviation is preset, and thereafter, the internal oscillation is controlled by subtracting the preset control amount. The operation of removing the phase deviation is not required every time, and the control amount per carrier wave regeneration is greatly reduced, so that the reception control can improve the reception performance while maintaining high system stability. This has the effect of obtaining the device.

According to the next invention, the control amount corresponding to the phase deviation of the initial carrier is preset, and thereafter, the internal oscillation is controlled by subtracting the preset control amount. Since the loop filter is controlled to keep the loop gain even smaller,
It is only necessary to remove only the amount of phase jitter by suppressing the loop filter in a state where the carrier frequency error has already been removed, so that the tracking performance to the phase jitter is improved and the stability of the system is kept high. There is an effect that a reception control device capable of improving reception performance can be obtained.

According to the next invention, in the time-division multiplexing communication, even if the phase deviation of the carrier in the first burst reception of the burst reception is to be removed, the phase deviation is removed at the initial stage. Since the control amount per playback is greatly reduced and the system stability increases, a reception control device that can improve the reception performance while maintaining high system stability even in time division multiplex communication. The effect is obtained.

According to the next invention, in the time-division multiplexing communication, the control amount corresponding to the phase deviation of the carrier is preset every time a burst is received for the own device. Will have to be removed,
The frequency error of the carrier gradually decreases with each burst reception. As a result, the control amount per carrier wave regeneration is greatly reduced and the stability of the system is increased. Therefore, the reception performance can be improved while maintaining the stability of the system high even in time division multiplex communication. There is an effect that a possible reception control device can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a reception control device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reception control device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a reception control device according to a third embodiment of the present invention.

FIG. 4 is a diagram illustrating a method for removing a stationary phase deviation according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a reception control device according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a reception control device according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a reception control device according to a seventh embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a reception control device according to a ninth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a reception control device according to a tenth embodiment of the present invention.

FIG. 10 shows D applied to a conventional reception control device.
It is a block diagram showing composition of LL.

[Explanation of symbols]

2,3,12,13,22,23,32,33,72
A, 72B multiplier, 4, 14, 24, 34, 74 adder, 5, 25, 35, 46, 66, 75 loop filter, 6, 16, 26, 47, 57, 76 voltage preset circuit, 7, 18 , 28, 37, 77 VCC oscillation circuit, 8, 19, 29, 38, 78 N-stage feedback shift register, 15, 56 Variable loop filter, 17, 58
Loop filter setting circuit, 27 delay amount setting circuit, 3
6,67 sequential voltage preset circuit, 45,55,65
Phase comparator, 48, 59, 68 VCO

Claims (9)

[Claims] 1. A reception control device for reproducing a clock by controlling an internal oscillation circuit according to a phase deviation between an external clock included in a reception signal and an internal clock oscillated by an internal oscillation circuit, the reception control device comprising: When the control amount of the internal oscillation circuit is preset based on a phase deviation generated in the initial clock reproduction after the start, and the internal oscillation circuit is controlled based on a phase deviation generated in the clock reproduction after the initial clock reproduction. The present invention further comprises a preset control means for controlling the difference between the current control amount and the preset control amount. 2. The internal oscillation circuit is controlled in accordance with a phase deviation between an external clock included in a reception signal from which a high-frequency component has been removed via a loop filter and an internal clock oscillated by the internal oscillation circuit. In a reception control device that performs clock recovery, a control amount of the internal oscillation circuit is preset based on a phase deviation generated in initial clock recovery after reception starts, and based on a phase deviation generated in clock recovery after the initial clock recovery. When controlling the internal oscillating circuit, a preset control unit that controls the current control amount and a difference between the preset control amount, and a loop gain of the loop filter based on the control amount of the preset control unit. Loop gain control means for controlling the gain to be smaller than the current loop gain. Control device. 3. A method for controlling an internal oscillation circuit according to a phase deviation between an external clock included in a received signal and an internal clock oscillated by an internal oscillation circuit, wherein the phase correlation value and the phase correlation value are controlled. In a reception control device that performs clock recovery with a constant delay amount for taking a clock, a control amount of the internal oscillation circuit is preset based on a phase deviation generated in the initial clock recovery after the start of reception, and after the initial clock recovery, When the internal oscillation circuit is controlled based on the phase deviation generated by the clock regeneration of the preset control amount, the preset control amount is controlled by a difference between the current control amount and the preset control amount. A delay amount control means for controlling the delay amount to be smaller than the current delay amount based on the control amount. . 4. Clock recovery is performed by controlling the internal oscillation circuit in accordance with a phase deviation between an external clock included in a received burst signal by time division multiplex communication and an internal clock oscillated by the internal oscillation circuit. In the reception control device, the control amount of the internal oscillation circuit is preset based on the phase deviation of the clock generated in the initial burst reception after the start of reception, and based on the phase deviation of the clock generated in the clock recovery after the initial clock recovery. And a preset control means for controlling the internal oscillation circuit by a difference between a current control amount and the preset control amount. 5. Clock recovery is performed by controlling the internal oscillation circuit according to a phase deviation between an external clock included in a received burst signal by time division multiplex communication and an internal clock oscillated by the internal oscillation circuit. In the reception control device, when the control amount of the internal oscillation circuit is preset based on a phase deviation generated by clock recovery, and when the internal oscillation circuit is controlled based on a phase deviation generated by subsequent clock recovery, the present control is performed. A reception control device comprising a sequential preset control means for controlling a difference between the amount and a control amount preset last time. 6. A reception control apparatus for recovering a carrier by controlling the voltage-controlled oscillation circuit according to a phase deviation between an external carrier included in a received signal and an internal carrier controlled by a voltage-controlled oscillation circuit. Presetting the control amount of the voltage-controlled oscillation circuit based on the phase deviation generated in the initial carrier reproduction after the start of reception, the voltage-controlled oscillation circuit based on the phase deviation generated in the carrier reproduction after the initial carrier reproduction. A reception control device, comprising: a preset control means for controlling a difference between a current control amount and the preset control amount when controlling. 7. The voltage-controlled oscillation circuit is controlled in accordance with a phase deviation between an external carrier included in a received signal from which a high-frequency component has been removed via a loop filter and an internal carrier controlled by a voltage-controlled oscillation circuit. In the reception control device that performs carrier recovery, the control amount of the voltage-controlled oscillation circuit is preset based on the phase deviation generated in the initial carrier recovery after the start of reception, and the phase generated in the carrier recovery after the initial carrier recovery is performed. When controlling the voltage-controlled oscillation circuit based on the deviation, preset control means for controlling the difference between the current control amount and the preset control amount; and the loop filter based on the control amount of the preset control means. Loop gain control means for controlling the loop gain to be smaller than the current loop gain. Reception control device. 8. Carrier wave reproduction by controlling said voltage controlled oscillation circuit in accordance with a phase deviation between an external carrier wave included in a received burst signal by time division multiplex communication and an internal carrier wave controlled by a voltage controlled oscillation circuit. In the receiving control device, the control amount of the voltage-controlled oscillation circuit is preset based on the phase deviation of the carrier generated in the initial burst reception after the start of reception, and the phase of the carrier generated in the carrier recovery after the initial carrier recovery is controlled. A reception control device, comprising: a preset control unit for controlling the voltage-controlled oscillation circuit based on a deviation by controlling a difference between a current control amount and the preset control amount. 9. A carrier wave reproduction by controlling the voltage controlled oscillation circuit according to a phase deviation between an external carrier wave included in a received burst signal by time division multiplex communication and an internal carrier wave controlled by a voltage controlled oscillation circuit. In the case of controlling the voltage-controlled oscillation circuit based on the phase deviation generated in the subsequent carrier wave recovery, the control amount of the voltage-controlled oscillation circuit is preset based on the phase deviation generated in the carrier wave recovery. A reception control device comprising a sequential preset control means for controlling a difference between a current control amount and a previously preset control amount.