JP2555928B2 - Step track tracking device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a step track tracking device, and more particularly to a step track tracking device which receives an intermittent (burst) received signal at an antenna.

[0002]

2. Description of the Related Art In a conventional earth station apparatus for satellite communication, in order to correctly direct an antenna beam to a satellite, the antenna is mechanically step-driven to change the pointing direction of the antenna by a small angle. A step track tracking device is provided that compares and determines the received signal levels of the above and controls the antenna pointing direction so that the received level becomes maximum. An example of this type of step track tracking device is disclosed in Japanese Patent Laid-Open No. 60-222780.
This step track tracking device measures a temporal level fluctuation dL of a received signal during an antenna stationary period before and after step driving, and drives the antenna when this level fluctuation dL is smaller than a predetermined reference fluctuation value dL0. Then, the step track operation is performed, and conversely, if the level fluctuation dL is larger than the reference fluctuation value dL0, the antenna is not driven. Further, this step track tracking device integrates the level of the received signal for a certain period of time in order to reduce the level fluctuation of the received signal due to noise.

[0003]

The above-mentioned conventional step track tracking device performs tracking when a received signal is intermittently transmitted, for example, when there is no voice (information) as in a communication system using voice activation. When bursts are transmitted intermittently, the received signal constantly fluctuates, and there is a problem that the step driving of the antenna cannot be performed.

[0004]

SUMMARY OF THE INVENTION A step track tracking device of the present invention is an antenna circuit for receiving a burst-shaped reception signal and changing the antenna pointing direction stepwise under the control of a drive command signal, and the burst-shaped reception signal. a receiving circuit is level from the signal resulting intermediate frequency signal proportional to the level of the received signal, in the from the receiving circuit
A phase demodulator for synchronizing the inter-frequency signal with a reference signal and generating a synchronization signal and a reception level signal representing the level of the intermediate frequency signal in the phase synchronization state; and responding to the synchronization signal and the reception level signal. Signal processing circuit that integrates the reception level signal for a predetermined period to generate an integrated reception level signal, and the drive command by comparing the integration reception level signal and the integration reception level signal obtained at the time of inputting the previous synchronization signal. And a drive control circuit for generating a signal.

In this step track tracking device, the integrated reception level signal may include a signal obtained by integrating the reception signals of a plurality of bursts in order to secure the predetermined time.

Further, in this step track tracking device, the received signal is a burst signal having a period of a non-modulated signal (CW signal) at the head, and the receiving circuit and the demodulator have a section of the CW signal. However, it may have means for enabling synchronization of the intermediate frequency signal.

When the drive control circuit receives the analog / digital converter for converting the reception level signal into a digital format and the synchronization signal, the drive control circuit integrates the reception level signal in the digital format for the predetermined time. Level integration means, reception level conversion means for converting the integrated reception level signal into a reception level per unit time, and the reception level per unit time and the reception per unit time obtained at the previous input of the synchronization signal. A microprocessor including drive control signal generating means for generating a digital drive control signal by comparing with a level, and a digital / analog converter for converting the digital drive control signal into the drive control signal may also be provided. Good.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. This step track tracking device receives an intermittent reception signal S1 at an antenna 1. The reception signal S1 is amplified by the low noise amplifier 21 of the reception circuit 2, and then the intermediate frequency (IF) signal S is transmitted by the frequency converter (MIX) 23 having the voltage controlled oscillator (VCO) 22 as a local oscillator.
Converted to 3. The IF signal S3 is supplied to the demodulator 3.
It Demodulator 3, received in response to the IF signal S3 signal S1
Level signal S5 indicating the level (reception level) 1 of
And the phase synchronization between the reference signal generated by the built-in reference signal oscillator and the IF signal S3 (hereinafter, the phase synchronization is omitted as synchronization).
It is) synchronized with the signal S7 identifying the state, resulting in. Further, the demodulator 3 feeds back the phase difference signal S2 to the VCO 22 and phase-matches the IF signal S3 with the reference signal.
Control automatically to the proper frequency. Here, as will be described later with reference to FIG. 2, the demodulator 3 in this embodiment is capable of transmitting the synchronizing signal S7 and the reception level signal S5 of the IF signal S3 only when the IF signal S3 is a CW signal. . As the demodulator 3, it is of course possible to use a known demodulator that operates even when the IF signal S3 is a modulated signal. The demodulator 3 in this case uses the IF signal S
The synchronization signal S7 and the reception level signal S5 representing the synchronization state are transmitted during the modulation signal period of 3, and the IF signal S
The demodulated signal S6 is reproduced from S3.

The reception level signal S5 and the synchronization signal S7 are supplied to the drive control circuit 5. The drive control circuit 5 receives the reception level signal S when the synchronization signal S7 indicates a synchronization state.
5 is integrated, and the integrated value L is converted into the reception level a per unit time. Then, the drive control circuit 5 sends a drive command signal S8 to the electric motor 4 including a step motor, and the electric motor 4 slightly drives the antenna 1 in a predetermined direction by the drive signal S4. After the asynchronous state of the demodulator 3 (IF signal S3) has passed, the synchronization control of the demodulator 3 restores the synchronous signal S7 to the synchronous state again.
Newly integrates the reception level signal S5, and the integrated value L
Then, the reception level b per unit time after the step driving of the antenna 1 is obtained. After that, the drive control circuit 5 compares the reception levels a and b to determine the drive direction of the antenna 1, and the drive command signal S in the analog format based on this determination.
8 is sent to the electric motor 4. By repeating the above-described reception level comparison and step driving of the antenna 1, the antenna 1 directs the antenna directivity in an appropriate direction in which the reception level signal S5 is maximized.

FIG. 2 is a diagram for explaining the details of the demodulator 3 used in the step track tracking device of FIG.
(A) is a block diagram, (b) has shown an example of the received signal S1 (IF signal S3 supplied to the demodulator 3) supplied to this step track tracking apparatus.

The IF signal S3 has a repetition cycle of 480 mS.
This is a burst signal of ec, and a CW signal period is provided only for 38 mSec at the head of this IF signal S3.
The CW signal is followed by the modulation signal, and the CW signal and the modulation signal form one packet. The modulation method may be AM, FM, BPSK, QPSK, or the like.

When the IF signal S3 is the CW signal,
The IF signal S3 is converted into a constant level IF signal S31 by the AGC amplifier 31 of the demodulator 3. This IF signal S31
The reference signal S 35 from the part and the reference signal oscillator 35 is, is phase compared by phase detector 32 produces a phase difference signal S32. The phase difference signal S32 is the loop filter 3
3 by position is band limited to less than the bandwidth of the modulated signal
It becomes the phase difference signal S2. The phase difference signal S2 is supplied to the VCO22 receiving circuit 2, a reference signal onset of the IF signal S3
The phase is synchronized with the reference signal S35 from the shaker 35 and the frequency is controlled to an appropriate frequency. That is, the VCO 22 and MIX 23 of the receiving circuit 2, the AGC amplifier 31, the phase detector 32, the loop filter 33 and the reference signal oscillator 34 of the demodulator 3.
And form a phase-locked loop. IF
The other part of the signal S31 and the reference signal S35 are supplied to the synchronous detector 34, and the synchronous detector 34 uses the reference signal S35 as a reference.
The IF signal S31 is synchronously detected by the DC demodulation signal S36
Is generated. This demodulated signal S36 is a low-pass filter (L
PF) 36 to control the gain of the AGC amplifier 31 and become a reception level signal S5 representing the reception level of the reception signal S1.

Here, in the demodulator 3, the IF signal S3 is C
When it is a W signal, it becomes in a synchronous state, and in this synchronous state,
The reception level signal S36 is the IF signal S3 (reception signal S1).
DC signal proportional to the level of. Sync detector 37
Determines whether or not the DC level of the demodulated signal S36 exceeds a predetermined threshold value to detect whether the demodulator 3 is synchronous or asynchronous. When the synchronous state is “H”, the asynchronous state is “L”. Produces signal S7.

In this embodiment, the band of the loop filter 33 is narrower than the band of the modulated signal of the IF signal S3. Therefore, during the period of the modulation signal of the IF signal S3, the phase lock loop for controlling the frequency of the IF signal S3 does not operate, and the synchronization detector 37 outputs the AC demodulation signal S36 of which the level changes. . The AC demodulation signal S36 does not normally pass through the LPF 36, and therefore the demodulator 3 does not generate the reception level signal S5 during the modulation signal of the IF signal S3.

FIG. 3 is a signal diagram for explaining one of the operations of the embodiment shown in FIG. 4 is a flow chart showing the operation of the embodiment of FIG. 1 in the signal state of FIG.

The operation of the step track tracking device will be described with reference to FIGS. 1, 3 and 4. Period T1
When the received signal S1 is supplied to this step track tracking device at the beginning of (step 11), the demodulator 3 outputs the level l
The reception level signal S5 of 1 and the synchronization signal S7 indicating the synchronization state are transmitted. The reception level signal S5 is converted into a digital format by an analog / digital converter (A / D) 51 of the drive control circuit 5. In addition, the synchronization signal S7
Is a microprocessor (CPU) 5 of the drive control circuit 5.
4 is supplied. The CPU 54 uses the synchronization signal S7 to
Whether the demodulator 3 is synchronous or asynchronous is determined (step 12).
When the synchronization signal S7 indicates an asynchronous state (N in step 12)
O), the CPU 54 repeats step 12. When the synchronization signal S7 indicates the synchronization state in step 12 (YES in step 12, for example, T1 period), the CPU 54 sets T
The digital-type reception level signals (l1) from the A / D 51 in one period are sequentially added, that is, integrated, and the integrated value L1 (= ∫l1dt) is stored in the memory 55 (step 13). Next, the CPU 54 converts the integrated value L1 into a reception level a (= L1 / T1) per unit time (step 14). Steps 13 and 15 are continued as long as the synchronization of the demodulator 3 continues (step 1
5 YES).

On the other hand, when the demodulator 3 becomes in an asynchronous state after the period T1, for example, the reception signal S1 is interrupted (NO in step 15), the CPU 54 causes the digital / analog converter (D / A) 53 and the drive amplifier 52 to operate. A drive command signal S8 indicating a predetermined driving step and direction of the antenna 1 is sent to the electric motor 4 via the electric motor 4, and the electric motor 4 step-drives the antenna 1 by the driving signal S4 (step 16).
After that, the CPU 54 further checks the operation of the demodulator 3 until the demodulator 3 enters the synchronization state (step 1).
7). When the demodulator 3 indicates the synchronized state in the period T2 (YES in step 17), the CPU 54 integrates the received signal level (12) from the A / D 51 in the period T2, and the integrated value L2 (= ∫l2dt) is obtained. It is stored in the memory 55 (step 18). Next, the CPU 54 sets the integrated value L2 to the reception level b (= L2 / T2) per unit time.
(Step 19).

Next, the CPU 54 compares the reception levels a and b (step 20), and when the reception level b is larger than a, outputs the drive command signal S8 for performing the drive step in the same direction as before and receives the signal. Replace level b with a (step 21). The electric motor 4 drives the antenna 1 stepwise (step 16). Also, the reception level b
Is smaller than a (step 22), the CPU 54
Outputs a drive command signal S8 that causes a drive step in the opposite direction to the previous one and replaces the received signal b with a (step 23). The electric motor 4 drives the antenna 1 in a reverse step (step 16).

According to the above-mentioned flow, this step track tracking device can execute the appropriate step track drive of the antenna 1 even if the received signal is a signal sent intermittently.

FIG. 5 is a signal diagram for explaining another operation of the embodiment shown in FIG. In this figure, when the period of the CW signal of the received signal S1 is short (periods T1, T2 and T3) and the synchronization state period of the demodulator 3 is short (difference between each of the periods T1, T2 and T3 and the period T4). It shows the case. Hereinafter, a method of calculating the reception level when the step track tracking device of FIG. 1 receives the reception signal S1 as shown in FIG. 5 will be described.

Now, let Ts be the minimum integration period of the reception level signal S5 necessary for determining the reception levels a and b. In this case, the drive circuit 5 outputs (T1 + T2 + T3
The reception level signal S5 is integrated until +, ..., Ti, ... Tn)> Ts is satisfied (i and n are positive integers). In FIG. 5, (T1 + T2 + T3)> Ts holds, and the reception level a before the step driving of the antenna 1 is a = (L
1 + L2 + L3) / (T1 + T2 + T3). Here, L1 = ∫l1dT1, L2 = ∫l2dT2, L3 =
∫ 13dT3. 1 after the first drive of antenna 1
Since T4> Ts is established in the synchronization period T4 of the time, the reception level b = L4 / T4. Where L4 =
∫ l4dT4.

As described above, the embodiment of FIG. 1 can determine the reception level with sufficient accuracy even if the synchronization period of the reception signal S1 varies.

[0024]

As described above, according to the present invention, tracking information is obtained by integrating the reception level signal in synchronization with the demodulator synchronization period, and the antenna is step-driven when the demodulator is in an asynchronous state. Therefore, even if the received signal is a burst signal, there is an effect that the tracking control of the satellite or the like by the step track can be performed without the pilot signal.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

2A and 2B are diagrams for explaining details of a demodulator 3 used in the step track tracking apparatus of the present embodiment, FIG. 2A is a block diagram, and FIG. 2B is a reception supplied to the step track tracking apparatus. An example of the signal S1 (IF signal S3 supplied to the demodulator 3) is shown.

FIG. 3 is a signal diagram illustrating one operation of the present embodiment.

4 is a flowchart showing the operation of the present embodiment in the signal state of FIG.

FIG. 5 is a signal diagram illustrating another operation of the present embodiment.

[Explanation of symbols]

 1 Antenna 2 Reception Circuit 3 Demodulator 4 Motor 5 Drive Control Circuit 21 Low Noise Amplifier 22 Frequency Converter (MIX) 23 Voltage Controlled Oscillator (VCO) 31 AGC Amplifier 32 Phase Detector 33 Loop Filter 34 Synchronous Detector 35 Reference Signal Generation Device 36 Low pass filter (LPF) 37 Synchronization detector 51 Analog / digital converter (A / D) 52 Drive amplifier 53 Digital / analog converter (D / A) 54 Microprocessor (CPU) 55 Memory

Claims (4)

(57) [Claims] 1. An antenna circuit which receives a burst-shaped reception signal and which is controlled by a drive command signal to change the antenna pointing direction in steps, and an intermediate level of the burst-shaped reception signal whose level is proportional to the level of the reception signal. A receiving circuit for producing a frequency signal and the medium from the receiving circuit
A phase demodulator for synchronizing the inter-frequency signal with a reference signal and generating a synchronization signal and a reception level signal representing the level of the intermediate frequency signal in the phase synchronization state; and responding to the synchronization signal and the reception level signal. Signal processing circuit that integrates the reception level signal for a predetermined period to generate an integrated reception level signal, and the drive command by comparing the integration reception level signal and the integration reception level signal obtained at the time of inputting the previous synchronization signal. A step track tracking device comprising: a drive control circuit for generating a signal. 2. The step track tracking device according to claim 1, wherein the integrated reception level signal includes a signal obtained by integrating the reception signals of a plurality of bursts in order to secure the predetermined time. 3. The received signal is a burst signal having a period of an unmodulated signal at the head, and the receiving circuit and the demodulator enable synchronization of the intermediate frequency signal only in the section of the unmodulated signal. The step track tracking device according to claim 1, further comprising: 4. The analog / digital converter, wherein the drive control circuit converts the reception level signal into a digital format,
When receiving the synchronization signal, a reception level integrating means for integrating the reception level signal in digital form for the predetermined time, a reception level converting means for converting the integrated reception level signal into a reception level per unit time, and A microprocessor including drive control signal generating means for generating a drive control signal in digital form by comparing a reception level per unit time with a reception level per unit time obtained at the time of inputting the previous synchronization signal; 2. The step track tracking device according to claim 1, further comprising a digital / analog converter for converting a drive control signal of a format into the drive control signal.