JPH098859A - Delay detection circuit - Google Patents

Abstract

PURPOSE: To save power consumption in an A/D converter. CONSTITUTION: Base band signals I and Q are respectively adopted as digital signals d1-d4 by few-letter word length A/D converters 101, 102 and multiple- letter word A/D converters 103, 104 so as to be multiplexed time sequence data DI and DQ at every component of a quadrature signal by a multiplexer 10. Time sequence data of phase angle θ is obtained by the ratio of DI and DQ and separated into time sequence data θ corresponding to a few-letter word length A/D converter output and time sequence data 9 2 corresponding to a multiple-letter word length A/D converter output by a demultiplexer 108. Then, a symbol clock is picked-up from θ1 by DPLL 113 and a demodulation output is obtained from θ2 by a judging circuit 114. In result the number of a switch leg is drastically reduced than heretofore in the multiple-letter word A/D converter and also in the few-letter word length A/D converter so that power consumption is saved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential detection circuit for demodulating a modulated signal which is phase-difference-modulated by a digital signal, and is particularly suitable for a portable radio device or the like where power consumption reduction is required. The present invention relates to a differential detection circuit.

[0002]

2. Description of the Related Art FIG. 2 shows a configuration example of a conventional QPSK type differential detection circuit used in a digital type wireless telephone device or the like. The quadrature detection signals I and Q, which are baseband signals after quadrature detection of the received signal, have a multi-word length A / D converter 201 at a sampling rate twice or more the symbol rate.
It is converted into a digital signal by 202. Here, the multi-word length A / D converter means that when a quantization bit number, that is, a word length of 2 to 3 bits or less is used as a small word length A / D converter, A long A / D converter having a word length of 8 bits or more, for example, is assumed.

The phase detection circuit 203 includes an A / D converter 20.
A calculation such as obtaining an arc tangent from the outputs 1, 202 is performed to calculate and output the phase θ of the received signal. Assuming that one symbol time of the digital signal is T, in the differential detection, the difference between the phase of the signal T time before and the phase of the current signal is obtained, and therefore the delay circuit 204 for N (oversampling number) samples is used. A delayed signal in which θ is delayed by one symbol time T is created. In this case, assuming that the word length (quantization bit number) of the A / D converters 201 and 202 is m, one sample value is represented by m bits, and therefore m × N bits, that is, m × N delay elements. Will be used. In this way, the difference circuit 205 calculates the difference between the phase delayed by one symbol and the current phase. Digital phase synchronization circuit (hereinafter referred to as DPLL) 206
The symbol clock phase is extracted from the output of the differential circuit 205, and the phase value of the output of the differential circuit 205 is determined by the determination circuit 207 at the timing of this extraction phase, and a demodulated digital signal (DEM OUT) is obtained.

[0004]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention At the rising and falling points of a pulse of a digital circuit, the circuit is charged and discharged, resulting in a large power consumption. Therefore, in the above-mentioned conventional circuit, the number of output pulses of the multi-word length A / D converter becomes m × N during one symbol time T, and the power consumption increases. Further, the delay circuit is also composed of a circuit having many delay elements such as m × N stages of shift registers, which causes a problem that the circuit scale increases.

An object of the present invention is to provide a differential detection circuit which consumes less power in an A / D converter and can realize a delay circuit on a smaller scale.

[0006]

According to the present invention, first and second baseband signals generated by quadrature detection of a four-phase phase difference modulation signal are sampled by a sampling clock to provide first and second small word lengths. A small word length A / D converter for generating a digital signal, and a multi-word length third and fourth digital signal for sampling the first and second baseband signals by a symbol clock. A first phase time series data is calculated from a multi-word length A / D converter and an arctangent of a ratio of the first and second digital signals, and an arctangent of a ratio of the third and fourth digital signals. Phase detecting means for calculating the second phase time series data from the above, and a first delay circuit for delaying the first phase time series data by one cycle of the sampling clock,
A first subtractor for obtaining a difference between the first phase time-series data and the output of the first delay circuit; and a phase cycle circuit for generating the symbol clock from the output of the first subtractor. A second delay circuit for delaying the second phase time series data by one cycle of the symbol clock,
A second subtractor for obtaining a difference between the second time series data and the output of the second delay circuit, and a demodulation output by making a determination based on the output of the second subtractor and the phase of the symbol clock. And a decision circuit for performing the same.

[0007]

[Operation] Small word length A / for extracting symbol clock
Although the D converter has a normal sampling number, the output word length is small, and therefore the number of pulse conversion points per unit time is also small. On the other hand, the multi-word length A / D converter for obtaining the demodulated signal has a long output word length but a small number of samplings, and also has a small number of pulse conversion points per unit time. Therefore, the power consumption of the A / D converter may be small, and the number of elements of the delay circuit may be small.

[0008]

The present invention will be described in detail below with reference to the embodiment shown in FIG. In FIG. 1, quadrature detection signals I and Q, which are baseband signals obtained by quadrature detection of a received signal, are small-word-length A / D converters 101 and 102 and multi-word-length A / D converters. Input to 103 and 104. Small word length A / D converter 1
01 and 102 sample the input signals I and Q by the sampling clock from the clock generator 105, quantize a small word length, and output a digital signal. On the other hand, the multi-word length A / D converters 103 and 104 sample the input signals I and Q by the symbol clock,
Multi-word length quantization is performed and a digital signal is output. Here, the sampling clock from the clock generator 105 is a pulse train having a period T _SP including N (oversampling number) pulses during one symbol period T _SB , and it is assumed that the symbol clock is multiplied by N. . In the following, N = 8.

FIG. 3 is a waveform diagram showing an operation example of the small word length A / D converter and the multi-word length A / D converter.
The digital outputs d1-d4 of the converters 101-104 are shown. In this example, the small word length A / D converters 101, 1
02 performs 1-bit quantization indicating only positive or negative of the input, and one arrow of the outputs d1 and d2 represents one sample value. Further, the multi-word length A / D converters 103 and 104 perform 8-bit quantization, and the sample value represented by the 8-bits is shown by one arrow in the figure.

Returning to FIG. 1, the signals d1 to d4 digitized as described above are time-division multiplexed by the multiplexer 106 and converted into two pulse trains.
That is, the output d obtained by digitizing the input signal I by the small word length A / D converter 101 and the multiple word length A / D converter 103.
1 and d3 are multiplexed into one pulse train signal DI, and the outputs d2 and d4 obtained by digitizing the input signal Q by the small word length A / D converter 102 and the multiple word length A / D converter 104 are multiplexed. It is made into one pulse train signal DQ.

FIG. 4 shows this multiplexed pulse train signal D.
I and DQ are shown, and each arrow indicates the value of data consisting of 8 bits and has the same meaning as one arrow of d1 to d4 in FIG. Further, thin line arrows indicate small word length A / D converter outputs d1 and d2, and thick line arrows indicate multi word length A / D converter outputs d3 and d4. However, the thin line arrow is shown in FIG.
Although it was represented by a 1-bit pulse at the stage of d1 and d2, an 8-bit pulse is represented by adding 7 "0" s to this. Since the thick arrow originally represents 8-bit data, the cycle of the pulse train level is adjusted as described above. Further, before the multiplexing, the thin arrow data (data of d1 and d2) also existed at the position of the thick arrow in FIG. 4, but this was removed during the multiplexing and the data of the thick arrow was inserted. There is. Like this
Even if the pulses of 1 and d2 are lost, no problem will occur because the symbol clock is only extracted from now on as will be described later.

The pulse train signals DI and DQ generated by being multiplexed by the multiplexer 106 are phase detection circuits 107.
Is input to the digital camera, and the tan ⁻¹ (DQ / DI) operation is performed here to detect the phase angle θ. This calculation calculates one θ for each arrow in FIG. 4, and the result is shown in FIG.

The multiplexer 108 includes the phase detection circuit 1
The time-series data of the phase angle θ output from 07 as shown in FIG. 5 is output from the small word length A / D converters 101 and 102 by d1 and
Phase angle time series data θ1 corresponding to d2 and multiword length A /
The phase angle time series data θ2 corresponding to the outputs d3 and d4 of the D converters 103 and 104 are separated. FIG. 6 shows a result of separating the time series data of FIG.

Of such separated time series data,
For θ1, the adjacent phase difference is calculated by the delay circuit 109 and the subtractor 111, and the DPLL 113 is calculated from the difference output.
The symbol clock is extracted by. Time series data θ
1 is a sequence of phase values obtained from the outputs of the small word length A / D converters 101 and 102. The word length is short and the quantization error is large, but the symbol clock extraction is phase change information between symbols. The clock extraction can be sufficiently performed if the number of samples is sufficient.

On the other hand, from the time series data θ2 separated by the demultiplexer 108, the adjacent phase difference is calculated by the delay circuit 110 and the subtractor 112, and the difference output is judged by the judgment circuit 114 and the demodulated digital signal ( D
EM OUT) is obtained. This judgment output is a multi-word length A / D converter 10 having a multi-word length but a small number of samples.
It is determined by delay detection from the outputs of 3 and 104. Therefore, the sampling timing in the multi-word length A / D converters 103 and 104 needs to be substantially the timing of symbol determination. However, since the symbol clock is already detected and synchronized by another path and the sampling is performed in the multi-word length A / D converter using this, this sampling is used as a substantial symbol decision timing. The condition is satisfied.

According to the above embodiment, the small word length A / D converters 101 and 102 have the same number of samples as the conventional one, but the word length is short, so that the number of pulse conversion points per unit time can be small. Further, as described above, if "0" is added for multiplexing, the number of pulses is logically increased. However, since this pulse train is usually 100% duty and a pulse having no level change is used for "0", the number of pulse conversion points is not increased. On the other hand, multi-word length A / D converter 10
Samples 3 and 104 have a large number of words, but the number of samples is small.
Therefore, the number of pulse conversion points per unit time is small. In this way, the power consumption of the A / D converter can be greatly reduced by using the configuration of this embodiment. Also, the required number of delay elements in the delay circuits 109 and 110 can be reduced for the same reason as above.

[0017]

According to the present invention, the power consumption of the A / D converter can be greatly reduced, and the delay circuit can be constructed with a small number of delay elements.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a differential detection circuit of the present invention.

FIG. 2 is a block diagram showing a configuration example of a conventional differential detection circuit.

FIG. 3 is an operation explanatory diagram of a small word length A / D converter and a multi-word length A / D converter.

FIG. 4 is a diagram showing an example of a multiplexer output.

FIG. 5 is a diagram showing an example of a phase detector output.

FIG. 6 is a diagram showing an example of a demultiplexer output.

[Explanation of symbols]

 101, 102 Small-word length A / D converter 103, 104 Multi-word length A / D converter 105 Sampling clock generation circuit 106 Multiplexer 107 Phase detector 108 Demultiplexer 109, 110 Delay circuit 111, 112 Subtractor 114 Judgment circuit

Claims (3)

[Claims] 1. A small word for generating first and second digital signals having a small word length by sampling first and second baseband signals generated by quadrature detection of a four-phase phase difference modulation signal with a sampling clock. A long A / D converter, and a multiword length A / D converter for sampling the first and second baseband signals by a symbol clock to generate multiword third and fourth digital signals And calculating the first phase time series data from the arctangent of the ratio of the first and second digital signals, and calculating the second phase time series data from the arctangent of the ratio of the third and fourth digital signals. A first delay circuit for delaying the first phase time-series data by one cycle of the sampling clock, the first phase time-series data and the first phase time-series data Late A first subtractor for obtaining a difference from the output of the circuit; a phase cycle circuit for generating the symbol clock from the output of the first subtractor; and a second phase time-series data of the symbol clock of the symbol clock. A second delay circuit for delaying by one cycle, a second subtractor for obtaining a difference between the second time series data and an output of the second delay circuit, and an output of the second subtractor And a determination circuit for generating a demodulation output by determining the phase of the symbol clock. 2. The phase detecting means time-division-multiplexes the first and third digital signals with first multiplex time-series data, and the second and fourth digital signals with second multiplex-time data. A multiplexer for time-division-multiplexing the sequence data, a phase calculation means for calculating the phase time-series data from the arctangent of the ratio of the first and second multiplexed time-series data, and output time-series data of the means The demultiplexing circuit according to claim 1, further comprising: a demultiplexer for separating the first phase time-series data and the second phase time-series data. 3. The output word length of the small word length A / D converter is 1
3. The number of bits, the output word length of the multi-word length A / D converter is 8 bits, and the frequency of the sampling clock is 8 times the frequency of the symbol clock. Delay detection circuit.