JP2008072186A - Synchronous tracking circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous tracking circuit capable of holding a synchronous state with a phase giving maximum SN with high precision. <P>SOLUTION: In case of a synchronization shift from the phase for the maximum SN, an interpolation circuit 103 regulates an interpolation calculation coefficient of a base-band analog signal that an output digital signal of an A/D converting circuit indicates based on a phase shift amount from a phase shift detecting circuit 105 when carrying out an interpolation calculation processing over the output digital signal, and supplies the interpolated signal to a secondary sampling circuit 104. The secondary sampling circuit 104 performs sampling with a recovered clock to sample data having the maximum SN, and outputs the resulting data to a demodulating circuit 110. Consequently, the demodulating circuit can carry out a stable demodulation processing with excellent SN, so reception sensitivity can be improved. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a synchronization tracking circuit used on the receiving side of a communication apparatus.

  On the receiving side of the communication device, in order to demodulate the signal sent from the transmitting side, it is necessary to synchronize with the received signal. In this synchronization operation, there are two methods: synchronization acquisition that starts demodulation operation when an expected signal is received, and synchronization tracking that maintains synchronization by monitoring phase shift and performing phase correction at any time during demodulation. Is required.

  In the latter synchronization tracking, a clock that is recovered at the time of capturing the synchronization is used to generate a clock whose phase is advanced or delayed by one clock, and thus the phase correction is performed while shifting the recovered clock one clock at a time. A method is known (for example, Patent Document 1). Hereinafter, an outline of a conventional synchronization tracking method will be described with reference to FIG.

  FIG. 9 is a block diagram showing a configuration example of a conventional synchronization tracking circuit. A conventional synchronization tracking circuit 900 shown in FIG. 9 is provided at the input stage of the demodulation circuit 910, and includes an A / D conversion circuit 901, a clock recovery circuit 902, a phase shift circuit 903, and a secondary sampling circuit 904. And a phase shift detection circuit 905.

  The A / D conversion circuit 901 samples and quantizes the baseband analog signal and outputs it to the secondary sampling circuit 904.

  The clock recovery circuit 902 generates a recovered clock, an early clock that is one clock earlier than the recovered clock, and a late clock that is one clock later than the recovered clock, and outputs the generated clock to the phase shift circuit 903.

  The phase shift circuit 903 shifts each phase of the three clock signals input from the clock recovery circuit 902 based on the phase shift information when the phase shift information is input from the phase shift detection circuit 905 to perform the secondary operation. Output to the sampling circuit 904.

  The secondary sampling circuit 904 performs secondary sampling on the sampling data input from the A / D conversion circuit 901 using the three clocks input from the phase shift circuit 903, and provides early timing data, reproduction timing data, and rate. Timing data is generated and supplied to the phase shift detection circuit 905.

  The phase shift detection circuit 905 detects the phase shift by comparing the amplitudes of the three clock timing data input from the secondary sampling circuit 904 and detects the phase shift contents (phase shift amount and phase shift direction). The phase shift information shown is given to the phase shift circuit 903.

  Of the three clock timing data output from the secondary sampling circuit 904, the reproduction timing data is input to the demodulation circuit 910, and data demodulation at the time of synchronization tracking is performed.

  Next, the operation of the conventional synchronous tracking circuit 900 shown in FIG. 9 will be described. First, when synchronization acquisition is established for an effective baseband signal, the clock recovery circuit 902 starts to output a recovered clock, an early clock, and a late clock.

  At this time, the phase shift circuit 903 outputs each input clock as it is to the secondary sampling circuit 904 without performing phase shift. The secondary sampling circuit 904 subjects the input data from the A / D conversion circuit 901 to secondary sampling with each clock input from the phase shift circuit 903 and outputs the result to the phase shift detection circuit 905.

  Assuming that the synchronization is accurately obtained, among the three timing data output from the secondary sampling circuit 904, the data sampled with the reproduction clock has the highest SN ratio and becomes reliable data, and the demodulation circuit In 910, since demodulation is performed using data having a high S / N ratio, no problem occurs.

  However, with the passage of time, the synchronization with the received signal gradually shifts due to the master clock shift between the transceivers. For example, when the amount of deviation reaches a higher S / N ratio than the data secondarily sampled by the early clock output from the phase shift circuit 903 and the data secondarily sampled by the recovered clock. The data input to the demodulating circuit 910 is preferably data sampled with the early clock rather than data sampled with the recovered clock.

  Therefore, when detecting such a phase shift, the phase shift detection circuit 905 notifies the phase shift circuit 903 of the content of the detected phase shift. Upon receiving the notification, the phase shift circuit 903 performs an operation to shift the phase so that the current early clock becomes a new reproduction clock. As a result, the new early clock and the new late clock become a clock one clock earlier than the new recovered clock and a clock later than the new recovered clock, respectively.

By performing such an operation, in the secondary sampling circuit 904, the data that has been sampled with the early clock until then is sampled with the new reproduction clock, and it is passed to the demodulation circuit 910. The circuit 910 can demodulate using data with a high S / N ratio.
JP-A-8-335892

  However, in the above conventional synchronization tracking circuit, the data that can be selected by the reproduction clock is any of the data output from the A / D conversion circuit, so that the A / D conversion circuit performs n times oversampling (n is a natural number). Assuming that the synchronization tracking circuit performs the best operation, a time of about T / (2n) at the maximum is obtained by setting T as a symbol period or chip period before and after shifting the phase of the recovered clock by the phase shift circuit. Deviation from the ideal sample timing is one of the causes of demodulation errors.

  In addition, the conventional synchronization tracking circuit has a problem that a phase shift period is long because a phase shift is not detected unless a shift of about T / (2n) occurs in the recovered clock.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a synchronization tracking circuit that can maintain a synchronization state at a phase that gives a maximum S / N ratio with high accuracy.

  In order to achieve the above-described object, the present invention performs an interpolation calculation process on an A / D conversion circuit that converts a baseband analog signal into a digital signal and a digital signal that is input from the A / D conversion circuit. In this case, when phase shift information is input, an interpolation circuit that adjusts an interpolation calculation coefficient based on the phase shift information, a recovered clock regenerated at the time of synchronization acquisition, and one processing clock for the recovered clock A secondary sampling circuit that samples and outputs the interpolation data output by the interpolation circuit using three clocks of two clocks whose phases are advanced / delayed by a minute, and the secondary sampling circuit outputs Deviation from phase giving maximum signal-to-noise ratio using 3 sampling data A phase shift detection circuit that monitors and outputs the phase shift information when a predetermined phase shift is detected; and a demodulation circuit that performs a demodulation process using data sampled by a reproduction clock output from the secondary sampling circuit; It is characterized by having.

  According to the present invention, when synchronization deviation is detected, the A / D is set so that the timing at which the S / N ratio becomes maximum and the timing of the recovered clock match the interpolation circuit based on the phase deviation amount from the phase deviation detection circuit. Since the data from the conversion circuit is interpolated and output, high-accuracy synchronous tracking can be realized and reception sensitivity can be improved.

  According to the present invention, since the synchronization state at the phase that provides the maximum SN ratio can be maintained with high accuracy, it is possible to improve the SN ratio of data used for demodulation and improve reception sensitivity.

  Exemplary embodiments of a synchronization tracking circuit according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a synchronous tracking circuit according to Embodiment 1 of the present invention. A synchronization follow-up circuit 100 according to the first embodiment shown in FIG. 1 includes an A / D conversion circuit 101, a band limiting filter 102, an interpolation circuit 103, a secondary sampling circuit 104, and a phase shift detection circuit 105. And a jitter removal filter 106. Note that the band limiting filter 102 and the jitter removal filter 106 are provided as necessary.

  The A / D conversion circuit 101 oversamples and quantizes the baseband analog signal and outputs it to the band limiting filter 102.

  The band limiting filter 102 performs band limiting processing on the sampling data output from the A / D conversion circuit 101 and outputs the result to the interpolation circuit 103. For example, when the baseband analog signal is input with sufficiently suppressed out-of-band noise, the band limiting filter 102 can be omitted.

  The interpolation circuit 103 performs an interpolation process (interpolation process) on the sampling data input from the band limiting filter 102 and outputs it to the secondary sampling circuit 104, for example, with the configuration shown in FIG. Detailed operation of the interpolation circuit 103 will be described later.

  The secondary sampling circuit 104 generates an early clock that is one clock earlier and a late clock that is one clock later from a reproduction clock that is input from the outside when synchronization is acquired, and uses these three clocks to generate an interpolation circuit. The sampling data (interpolation data) that has been subjected to the interpolation processing at 103 is secondarily sampled to generate early timing data, reproduction timing data, and late timing data, which are supplied to the phase shift detection circuit 105. .

  The phase shift detection circuit 105 detects the phase shift by comparing the amplitudes of the three clock timing data input from the secondary sampling circuit 104, and the detected phase shift content (phase shift amount and phase shift direction). Is provided to the jitter removal filter 106.

  The jitter removal filter 106 averages the phase shift information input from the phase shift detection circuit 105 to remove the influence of jitter, and outputs it to the interpolation circuit 103. If the phase shift detection information in the phase shift detection circuit 105 has few jitter components and the detection accuracy is sufficient, the jitter removal filter 106 can be omitted.

  Of the three clock timing data output from the secondary sampling circuit 104, the reproduction timing data is input to the demodulation circuit 110, and data demodulation at the time of synchronization tracking is performed.

  FIG. 2 is a block diagram showing a configuration example of the interpolation circuit 103 shown in FIG. For example, as shown in FIG. 2, the interpolation circuit 103 includes a shift register 201 that shifts sampling data input from the band limiting filter 102 by two stages, and a multiplier circuit that uses the first-stage output data of the shift register 201 as one input data. 202, a multiplication circuit 203 that uses the final output data of the shift register as one input data, and an interpolation calculation coefficient that generates an interpolation calculation coefficient (multiplication coefficient p) that is the other input data of the multiplication circuit 202 A multiplication circuit 204, an interpolation calculation coefficient generation circuit 205 for generating an interpolation calculation coefficient (multiplication coefficient q) which is the other input data of the multiplication circuit 203, and the multiplication results of the multiplication circuits 202 and 203 are added. Secondary sampling as the interpolation data And an adding circuit 206 to be output to the circuit 104.

  Here, the interpolation calculation coefficient generation circuits 204 and 205 perform interpolation at a period determined in consideration of the relationship between the sampling rate of the A / D conversion circuit 101 and the symbol rate (chip rate in the case of spread spectrum). Generate arithmetic coefficients. The period is determined as follows.

  First, assuming that the sampling rate of the A / D conversion circuit 101 is Ra, the symbol rate (chip rate in the case of spread spectrum) is Rs, and the number of oversampling when performing synchronization tracking processing is n, the interpolation circuit 103 is Using Ra data per unit time sampled at equal intervals for the baseband analog signal, as if (n × Ra) equal interval sampling per unit time was performed on the baseband analog signal Output data.

  The period of the interpolation calculation coefficient at this time is given by the reciprocal of the greatest common divisor of Ra and (n × Ra). For example, if the sampling rate of the A / D conversion circuit 101 and the oversampling rate are the same, the period of the interpolation calculation coefficient is the reciprocal of the sampling rate, that is, a constant value.

  Specifically, for example, when the sampling rate of the A / D conversion circuit 101 is 60 MHz, the chip rate is 11 MHz, and the number of oversampling is 4, the interpolation circuit 103 can output the data sampled at 60 MHz. It is converted into 44 MHz sampling data and output. The period of the interpolation calculation coefficient at this time is 0.25 μs.

  If the digital circuit is operating with a 60 MHz clock, 0.25 μs is 15 clocks. In this case, the interpolation calculation coefficient generation circuits 204 and 205 prepare and circulate 15 types of interpolation calculation coefficients. At this time, since the ratio of the number of output data to the number of input data per unit time in the interpolation circuit 103 is 15:11, four of the 15 interpolation calculation coefficients are dummy data. Therefore, if a measure such as generating an enable signal indicating that valid data other than the dummy is output, the subsequent processing becomes simple.

  Also, if phase shift information is input to the interpolation calculation coefficient generation circuits 204 and 205, an interpolation calculation coefficient that shifts the phase of the interpolation output at that moment is generated. The interpolation calculation coefficient is cyclically generated so as to maintain the same phase, or the interpolation calculation coefficient selection order of the interpolation output is skipped to an appropriate order at that moment, and thereafter, from the skipped order. Select interpolation coefficient. Detailed operation when phase shift information is input will be described later.

  Next, the operation of the synchronous tracking circuit 100 according to the first embodiment will be described with reference to FIGS. FIGS. 3 and 4 show the relationship between the baseband analog signal, the sample timing of the A / D conversion circuit, and the interpolation process. FIG. FIG. 4 is a diagram for explaining the synchronization tracking operation performed when the phase shift detection circuit 105 detects a phase shift amount exceeding a predetermined phase shift amount. FIG. It is a figure explaining the synchronous follow-up operation | movement performed at any time based on the phase shift amount which the phase shift detection circuit 105 detected.

  3 and 4, a, b, c, and d shown on the horizontal axis are sample timings when the A / D conversion circuit 101 performs oversampling four times. A, B, C, and D shown on the waveform of the baseband analog signal 300 are sampling data output by the A / D conversion circuit 101 at corresponding sample timings of a, b, c, and d. 3A, 3B and 4C, and FIGS. 4A and 4B, the maximum amplitude timing of the baseband analog signal 300 and the sample timings a, b, c in the A / D conversion circuit 101 are shown. , D and various relationships are shown.

  In the interpolation circuit 103, the sampling data A, B, C, and D are input to the shift register 201 in this order in FIG. If the multiplication coefficient p is 0 and the multiplication coefficient q is 1, the multiplication result of the multiplication circuit 203 is 0, and the multiplication result of the multiplication circuit 204 is A, B, C, and D.

  In FIG. 3, it is assumed that the timing indicating the maximum value of the baseband analog signal 300 coincides with the timing giving the maximum S / N ratio, and the timing coincides with the sample timing b of the A / D conversion circuit 101. In the case of the relationship shown in (a), if the interpolation calculation coefficient (p, q) is, for example, (p, q) = (0, 1), the interpolation data output by the interpolation circuit 103 is output. A, B, C, and D are data sampled at sample timings a, b, c, and d.

  In the present example, the secondary sampling circuit 104 detects the relationship of B> A = C from the amplitude comparison of the interpolation output data A, B, and C, and detects the phase shift information of B> A = C as a jitter removal filter. It is given to the interpolation circuit 103 via 106. Since the interpolation circuit 103 receives the phase shift information at the regular sample timing, it maintains the interpolation calculation coefficient (p, q) = (0, 1). As a result, the demodulation circuit 110 can capture the maximum value B of the baseband analog signal 300, so that demodulation can be performed based on a good SN ratio.

  As time elapses from this state, the relationship between the maximum value of the baseband analog signal 300 and the sample timing b gradually begins to shift due to a slight shift in the master clock frequency between the transceivers, and the state shown in FIG. Suppose that FIG. 3B shows a case where the maximum value of the baseband analog signal 300 is located at the center between the sample timings b and c, and the amplitudes of the interpolation output data B and C are equal. Compared with the interpolation output data B showing the maximum amplitude in FIG. 3A, the interpolation output data B and C in FIG. 3B are both out of sample timing, so the SN ratio is It is low.

  As the time elapses, when the maximum value of the baseband analog signal 300 passes the center position between the sample timings b and c and approaches the sample timing c as much as possible, the amplitude of the interpolation output data C becomes interpolated. Output data B. At this time, the phase shift detection circuit 105 outputs phase shift information notifying that the timing data at the sample timing c has the largest amplitude. This phase shift information is input to the interpolation circuit 103 through the jitter removal filter 106.

  Since the interpolation circuit 103 receives the phase shift information notifying that the late timing data has the largest amplitude, the interpolation calculation coefficient is changed. For example, (p, q) = (0, 1) is changed to (p, q) = (0.5, 0.5). As a result, in the interpolation circuit 103, as shown in FIG. 3B, (A + B) / 2, (B + C) / 2, and (C + D) / 2 from the input sampling data A, B, C, D. The interpolation output data is generated and output to the secondary sampling circuit 104. By doing so, the demodulation circuit 110 can take in the interpolation output data (B + C) / 2 that has been secondarily sampled by the recovered clock.

  Here, as shown in FIG. 3B, the interpolation output data (B + C) / 2 is generated as data at a timing at which the SN ratio of the baseband analog signal 300 becomes the largest by the interpolation calculation. Therefore, the data has the highest SN ratio. Therefore, the demodulation circuit 110 can perform demodulation with a good S / N ratio even when a phase shift occurs.

  Thereafter, as shown in FIG. 3 (c), when the maximum value of the baseband analog signal 300 eventually coincides with the position of the sample timing c and further time elapses, the interpolation calculation coefficient is (p, q). = (0.5, 0.5) is maintained, the phase shift detection circuit 105 uses the interpolation output data (A + B) / 2 that is secondarily sampled with the early clock and the second sampling with the recovered clock. The interpolated output data (B + C) / 2 and the interpolated output data (C + D) / 2 secondarily sampled by the late clock are received.

  In this case, since the interpolation output data (C + D) / 2 has the largest amplitude, the phase shift detection circuit 105 outputs the phase shift information notifying that the late timing data has the largest amplitude as the jitter removal filter 106. And output to the interpolation circuit 103.

  The interpolation circuit 103 sets the interpolation calculation coefficient to (p, q) = (0, 1) again so that the late timing data is changed to the timing data of the reproduction clock. Thereby, interpolation output data A, B, C, and D are output.

  At this time, the interpolation circuit 103 adjusts the timing so that the data C is output at the timing of the reproduction clock. By doing so, the demodulation circuit 110 can capture the maximum value C of the baseband analog signal 300, and can perform demodulation based on a good SN ratio.

  As described above, when the synchronization with the timing at which the S / N ratio becomes maximum occurs, the interpolation calculation coefficient is changed so that data at the timing at which the S / N ratio becomes maximum is generated and demodulated. Thus, the demodulation operation can be stably performed under a good S / N ratio, and the reception sensitivity can be improved.

  Next, referring to FIG. 4, when the synchronization phase is shifted even a little, the phase shift detection circuit 105 provides the phase shift information to the interpolation circuit 103 via the jitter removal filter 106 as necessary to perform the synchronization tracking operation. The case will be described.

  FIGS. 4A and 4B show a state where the phase is slightly shifted from the state shown in FIG. 4A shows a case where the sampling data C has a slightly larger amplitude than the sampling data A, and FIG. 4B shows a case where the sampling data C has a slightly smaller amplitude than the sampling data A. Show.

  As described above, in the state shown in FIG. 3A, the phase shift detection circuit 105 recognizes that the sample timing currently used for demodulation is the sample timing b. In the interpolation circuit 103, since the interpolation calculation coefficient (p, q) is (p, q) = (0, 1), the interpolation data A, B, C output from the interpolation circuit 103 is used. , D are data sampled at sample timings a, b, c, d.

  The phase shift detection circuit 105 compares the amplitudes of the three timing data from the secondary sampling circuit 104, generates phase shift information indicating how much data has become, and an interpolation circuit through the jitter removal filter 106. 103.

  The interpolation circuit 103 changes the values of the interpolation calculation coefficients p and q according to the input phase shift information.

  Specifically, in the case illustrated in FIG. 4A, the interpolation circuit 103 receives phase shift information indicating that the sampling data C has a slightly larger amplitude than the sampling data A. The calculation coefficient p is a value slightly larger than 0, and the interpolation calculation coefficient q is a value slightly smaller than 1. For example, (p, q) = (0.125, 0.875). As a result, the output of the interpolation circuit 103 becomes α, β, γ... Shown in FIG. Here, the timing position of the interpolation data β is a timing position that gives the maximum value of the actual baseband analog signal 300 although it is on the near phase advance side of the sampling timing b of the sampling data B. The interpolation circuit 103 adjusts the timing so as to sample the interpolation data β with the reproduction clock and outputs the interpolation data.

  In the case shown in FIG. 4B, the interpolation circuit 103 receives phase shift information indicating that the sampling data A has a slightly larger amplitude than the sampling data C. Therefore, the interpolation calculation coefficient p Is a value slightly smaller than 1, and the interpolation calculation coefficient q is a value slightly larger than 0. For example, (p, q) = (0.875, 0.125). As a result, the output of the interpolation circuit 103 becomes α, β, γ... Shown in FIG. The timing position of the interpolation data α here is a timing position that gives the maximum value of the actual baseband analog signal 300 although it is on the near-lag side of the sampling timing b of the sampling data B. The interpolation circuit 103 adjusts the timing so as to sample the interpolation data α with the reproduction clock and outputs the interpolation data.

  As described above, when the phase shift is detected at any time and the interpolation processing is performed, the phase shift can be followed with a shorter time delay than that described in FIG. Synchronized tracking is possible.

(Embodiment 2)
FIG. 5 is a block diagram showing a configuration of the synchronization tracking circuit according to the second embodiment of the present invention. In FIG. 5, the same reference numerals are given to components that are the same as or equivalent to the components shown in FIG. 1 (Embodiment 1). Here, the description will be focused on the portion related to the second embodiment.

  That is, as shown in FIG. 5, the synchronous follow-up circuit 500 according to the second embodiment has the same structure as that shown in FIG. 1 (first embodiment), but instead of the interpolation circuit 103 and the secondary sampling circuit 104. A poration circuit 501 is provided, and a phase shift detection circuit 502 is provided instead of the phase shift detection circuit 105. Further, a demodulation circuit 510 is provided instead of the demodulation circuit 110.

  The interpolation circuit 501 performs interpolation processing (interpolation processing) on the sampling data input from the band limiting filter 102, for example, with the configuration shown in FIG. (Phase shift information) is input, the interpolation calculation coefficient (multiplication coefficient) is changed, the interpolation process is performed, and it is output as interpolation data. A demodulation enable signal and a phase shift detection enable signal are generated from the recovered clock and output.

  In the enable period indicated by the phase shift detection enable signal output from the interpolation circuit 501, the phase shift detection circuit 502 detects the phase shift by comparing the amplitude of each piece of interpolation data output from the interpolation circuit 501. In addition to detecting the timing at which the maximum amplitude exists, the phase shift information indicating the content of the detected phase shift (phase shift amount and phase shift direction) and the maximum amplitude timing information are interleaved via the jitter removal filter 106. This is given to the poration circuit 501.

  Note that the demodulation enable signal and the interpolation output data output from the interpolation circuit 501 are input to the demodulation circuit 510, and data demodulation at the time of synchronization tracking is performed.

  FIG. 6 is a block diagram showing a configuration example of the interpolation circuit shown in FIG. For example, as shown in FIG. 6, the interpolation circuit 501 includes a counter 601 and a decoder 602 added to the interpolation circuit 103 shown in FIG. That is, the interpolation circuit 501 includes an interpolation calculation unit (201 to 206) and an enable signal generation unit (601, 602).

  The counter 601 repeatedly counts one period of the reproduction clock inputted from the outside at the time of synchronization acquisition, and gives the count value to the decoder 602.

  The decoder 602 decodes the count value from the counter 601, and an enable signal (phase shift detection enable signal) for the phase shift detection circuit 105 that uses the three sample timing period in the A / D conversion circuit 101 as an enable period. And an enable signal (demodulation enable signal) for the demodulation circuit 510 indicating the middle timing of the 3-sample timing period in the A / D conversion circuit 101 is output.

  Next, the operation of the synchronous tracking circuit 500 according to the second embodiment will be described with reference to FIGS. FIG. 7 shows the synchronization tracking performed by applying the interpolation process when the phase shift detection circuit 502 detects a phase shift amount exceeding a predetermined phase shift amount as the operation (part 1) of the synchronization tracking circuit 500. It is a figure explaining operation | movement. FIG. 8 is a diagram for explaining a synchronization tracking operation performed by applying interpolation processing as needed based on the phase shift amount detected by the phase shift detection circuit 502 as the operation (part 2) of the synchronization tracking circuit 500.

  7 corresponds to FIG. 3 and FIG. 8 corresponds to FIG. 4. Similarly, the relationship between the maximum value of the baseband analog signal to be phase-synchronized and the sample timing of the A / D converter circuit and the phase shift And the interpolation process are shown. For convenience of explanation, FIG. 7 has the same expression as FIG. 3, and FIG. 8 has the same expression as FIG. In the interpolation circuit 501, the interpolation calculation units (201 to 206) are the same as those of the interpolation circuit 103. Here, the description will be focused on the portion related to the second embodiment.

  First, in FIG. 7, when the maximum value of the baseband analog signal 300 matches the sample timing b of the A / D conversion circuit 101 as shown in FIG. Interpolation output data is captured with the period from a to c as the enable period. In the interpolation calculation unit (201 to 206) of the interpolation circuit 501, the interpolation data A, B, C, D is set as (p, q) = (0, 1), for example, as in the first embodiment. Is output.

  The phase shift detection circuit 502 detects the relationship B> A = C from the amplitude comparison of the interpolation output data A, B, and C, and the amplitude of the data at the middle timing that is currently demodulated is the largest. That is, it is determined that no synchronization deviation has occurred, and the interpolation circuit 501 is notified via the jitter removal filter 10 that no synchronization deviation has occurred. Therefore, the interpolation calculation unit (201 to 206) maintains the interpolation calculation coefficient (p, q) = (0, 1). As a result, the demodulation circuit 510 can capture the maximum value B of the baseband analog signal 300, so that demodulation can be performed under a good S / N ratio.

  Next, the case where the relationship between the maximum value of the baseband analog signal 300 and the sample timing b starts to gradually shift due to a slight shift in the master clock frequency between the transmitter and receiver, and the state shown in FIG. To do.

  FIG. 7B shows a case where the maximum value of the baseband analog signal 300 is located at the center between the sample timings b and c and the amplitudes of the interpolation output data B and C are equal. Since the interpolation output data B and C in FIG. 7B are both out of timing with the maximum value of the baseband analog signal 300, the SN ratio is low.

  As the time further elapses, when the maximum value of the baseband analog signal 300 passes through the center position between the sample timings b and c and approaches the sample timing c as much as possible, the amplitude of the interpolation output data C becomes interpolated. It becomes larger than the poration output data B.

  At this time, the phase shift detection circuit 502 outputs phase shift information notifying that the timing data (late timing data) at the sample timing c has the largest amplitude. This phase shift information passes through the jitter removal filter 106 and is input to the interpolation circuit 501.

  Since the interpolation circuit 501 receives the phase shift information notifying that the late timing data has the largest amplitude, the interpolation calculation coefficient is changed. For example, (p, q) = (0, 1) is changed to (p, q) = (0.5, 0.5). As a result, in the interpolation circuit 501, from the input sampling data A, B, C, D, as shown in FIG. 7B, (A + B) / 2, (B + C) / 2, (C + D) / 2 Interpolation output data is generated and output. At this time, the timing for outputting the interpolation output data (B + C) / 2 and the timing for outputting the demodulation enable signal are matched. By doing so, the demodulation circuit 510 can capture the interpolation output data (B + C) / 2.

  Here, as shown in FIG. 7B, the interpolation output data (B + C) / 2 is generated as data at the timing at which the SN ratio of the baseband analog signal 300 is maximized by the interpolation calculation. Therefore, the data with the highest SN ratio is obtained. Therefore, the demodulation circuit 510 can perform demodulation with a good S / N ratio even when a phase shift occurs.

  After that, as shown in FIG. 7C, when the maximum value of the baseband analog signal 300 eventually coincides with the position of the sample timing c and further time elapses, the interpolation circuit 501 performs interpolation calculation. Since the coefficients are maintained at (p, q) = (0.5, 0.5), the phase shift detection circuit 502 uses (A + B) / 2, (B + C) / 2, depending on the phase shift detection enable signal. Interpolation output data of (C + D) / 2 is received.

  In this case, since the interpolation output data (C + D) / 2 has the largest amplitude, the phase shift detection circuit 502 has the largest amplitude of data captured at the last timing of the phase shift detection enable signal period. The phase shift information to notify this is output to the interpolation circuit 501 via the jitter removal filter 106.

  The interpolation circuit 501 again sets the interpolation calculation coefficient (p,) so that the data at the last timing of the phase shift detection enable signal period is changed to the data at the middle timing of the phase shift detection enable signal period. q) = (0, 1). Thereby, interpolation output data A, B, C, and D are output. At this time, the interpolation circuit 501 adjusts the timing so that the data C is output at the timing of the demodulation enable signal. By doing so, the demodulation circuit 510 can capture the maximum value C of the baseband analog signal 300, and thus can perform demodulation under a good S / N ratio.

  As described above, when the synchronization deviation from the timing at which the SN ratio is maximized is detected, the interpolation calculation coefficient is changed, and data at the timing at which the SN ratio is maximized is generated and demodulated. The demodulation operation can be stably performed under a good S / N ratio, and the reception sensitivity can be improved.

  Next, referring to FIG. 8, when the synchronization phase is shifted even a little, the phase shift information detected by the phase shift detection circuit 502 is given to the interpolation circuit 501 via the jitter removal filter 106 to perform the synchronization tracking operation. The case of performing will be described.

  FIGS. 8A and 8B show a state where the phase is slightly shifted from the state shown in FIG. 8A shows a case where the amplitude of the sampling data C is slightly larger than the amplitude of the sampling data A, and FIG. 8B shows a case where the amplitude of the sampling data C is slightly smaller than the amplitude of the sampling data A. Show.

  As described above, in the state shown in FIG. 7A, the phase shift detection circuit 502 recognizes that the sample timing currently used for demodulation is the sample timing b. In the interpolation circuit 501, since the interpolation calculation coefficient is (p, q) = (0, 1), the interpolation data A, B, C, and D output from the interpolation circuit 501 are sampled. This is the data itself sampled at timings a, b, c, and d.

  The phase shift detection circuit 502 compares the amplitudes of the interpolation data captured during the phase shift detection enable signal period, generates phase shift information indicating how much data has increased, and passes through the jitter removal filter 106. To the interpolation circuit 501.

  The interpolation circuit 501 changes the values of the interpolation calculation coefficients p and q according to the input phase shift information.

  Specifically, in the case shown in FIG. 8A, the interpolation circuit 501 receives phase shift information indicating that the sampling data C has a slightly larger amplitude than the sampling data A. The calculation coefficient p is set to a value slightly larger than 0, and the interpolation calculation coefficient q is set to a value slightly smaller than 1. For example, (p, q) = (0.125, 0.875). As a result, the output of the interpolation circuit 501 becomes α, β, γ... Shown in FIG. The timing position of the interpolation data β here is a timing position that gives the maximum value of the actual analog baseband signal, although it is on the near phase advance side of the sampling timing b of the sampling data B. The interpolation circuit 501 adjusts the timing so as to sample the interpolation data β with the reproduction clock and outputs the interpolation data.

  Further, in the case shown in FIG. 8B, the interpolation circuit 501 receives phase shift information that the sampling data A has a slightly larger amplitude than the sampling data C. Therefore, the interpolation calculation coefficient p Is a value slightly smaller than 1, and the interpolation calculation coefficient q is a value slightly larger than 0. For example, (p, q) = (0.875, 0.125). As a result, the output of the interpolation circuit 501 becomes α, β, γ... Shown in FIG. The timing position of the interpolation data α here is a timing position that gives the maximum value of the actual baseband analog signal 300 although it is on the near-lag side of the sampling timing b of the sampling data B. The interpolation circuit 501 adjusts the timing so as to sample the interpolation data α with the reproduction clock and outputs the interpolation data.

  As described above, when the phase shift is detected at any time and the interpolation process is performed, the phase shift can be followed with a shorter time delay than that described with reference to FIG. Synchronized tracking is possible.

  As described above, the synchronization tracking circuit according to the present invention maintains the synchronization state at the phase that gives the maximum S / N ratio with high accuracy, realizes a stable demodulation operation under a good S / N ratio, and receives the sensitivity. This is useful for improving the above.

The block diagram which shows the structure of the synchronous tracking circuit by Embodiment 1 of this invention. 1 is a block diagram showing a configuration example of an interpolation circuit shown in FIG. The figure explaining the operation | movement (the 1) of the synchronous tracking circuit shown in FIG. The figure explaining the operation | movement (the 2) of the synchronous tracking circuit shown in FIG. The block diagram which shows the structure of the synchronous tracking circuit by Embodiment 2 of this invention. FIG. 5 is a block diagram showing a configuration example of the interpolation circuit shown in FIG. The figure explaining the operation | movement (the 1) of the synchronous tracking circuit shown in FIG. The figure explaining the operation | movement (the 2) of the synchronous tracking circuit shown in FIG. Block diagram showing a configuration example of a conventional synchronous tracking circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 100,500 Synchronization tracking circuit 101 A / D conversion circuit 102 Band-limiting filter 103,501 Interpolation circuit 104 Secondary sampling circuit 105,502 Phase shift detection circuit 106 Jitter removal filter 110,510 Demodulation circuit 201 Shift register 202,203 Multiplication circuit 204, 205 interpolation calculation coefficient generation circuit 206 addition circuit 601 counter 602 decoder

Claims (8)

An A / D conversion circuit for converting a baseband analog signal into a digital signal;
An interpolation circuit that adjusts an interpolation calculation coefficient based on phase shift information when phase shift information is input when performing interpolation calculation processing on a digital signal input from the A / D conversion circuit. When,
Sampling the interpolation data output by the interpolation circuit using three clocks: a recovered clock regenerated at the time of synchronization acquisition and two clocks of which the phase of one processing clock is advanced or delayed with respect to the recovered clock. A secondary sampling circuit that outputs
A phase shift detection circuit that monitors the shift from the phase that gives the maximum S / N ratio using the three sampling data output by the secondary sampling circuit, and outputs the phase shift information when a predetermined phase shift is detected;
A demodulation circuit that performs demodulation processing using data sampled by a reproduction clock output from the secondary sampling circuit;
A synchronous tracking circuit comprising: An A / D conversion circuit for converting a baseband analog signal into a digital signal;
When the phase shift information is input when performing the interpolation calculation process on the digital signal input from the A / D conversion circuit and outputting the digital signal to the demodulation circuit, the interpolation calculation coefficient is calculated based on the phase shift information. An interpolation circuit that adjusts and generates a phase shift detection enable signal that indicates a period of one processing clock before and after the recovered clock recovered at the time of synchronization acquisition;
Deviation from the phase that gives the maximum S / N ratio is monitored using the interpolation data output from the interpolation circuit within the period of the phase shift detection enable signal output from the interpolation circuit, and a predetermined phase is detected. A phase shift detection circuit that outputs the phase shift information when a shift is detected;
A demodulation circuit that takes in the interpolation data with the recovered clock and performs demodulation processing;
A synchronous tracking circuit comprising: 3. The synchronous tracking circuit according to claim 1, wherein the phase shift detection circuit generates and outputs the phase shift information when the detected phase shift amount exceeds a predetermined phase shift amount. . The synchronous tracking circuit according to claim 1, wherein the phase shift detection circuit generates and outputs the phase shift information based on the detected phase shift amount as needed. The synchronous tracking circuit according to claim 1, wherein the interpolation circuit selects a coefficient used for an interpolation calculation performed on the phase shift information from preset values. . The synchronous tracking according to claim 1, wherein the interpolation circuit calculates a coefficient used for an interpolation calculation performed on the phase shift information as needed according to the phase shift amount. circuit. The synchronous tracking circuit according to claim 1, wherein a band limiting filter that performs a band limiting process is inserted between the A / D conversion circuit and the interpolation circuit. The synchronous tracking circuit according to claim 11, wherein a jitter removal filter for removing jitter is inserted between the phase shift detection circuit and the interpolation circuit.

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