JPH08317007A - Data receiver - Google Patents

Abstract

PURPOSE: To recover a bit clock with digital signal processing. CONSTITUTION: Oversampling is carried out for a reception signal by using a self-running clock with a frequency being an integral multiple of a symbol rate. The receiver is provided with an A/D converter means 24 digitizing a sample value and an adder means 25 adding digitized sample values with synchronization over a prescribed period for a symbol interval, a detection means 26 detecting a symbol identification point from the result of synchronization addition, a decoding means 27 decoding data based on a sample value at a symbol identification point, a detection means 28 detecting a displacement of the symbol identification point timewise as a phase shift, a variable frequency divider means 30 frequency-dividing the frequency of the self-running clock to recover the bit clock, a control means 29 controlling a frequency division ratio of the variable frequency divider means to correct the phase shift, and frame synchronizing signal generating means 31, 32 extracting a known synchronization word from decoded data to acquire frame synchronization and generating a frame synchronization timing based thereon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving device for recovering a bit clock from a received signal, generating a frame synchronization signal and decoding data, and more particularly to a device capable of reproducing the bit clock by digital processing. Is.

[0002]

2. Description of the Related Art In digital wireless communication, when a receiving side receives a modulated signal, the receiving side detects the demodulated signal and demodulates it into a baseband signal, and then captures the amplitude at a symbol identification point of this signal to obtain a digital signal. The data is converted and the data is decoded based on this digital signal. Then, a known synchronization word is extracted from the decoded data to establish frame synchronization.

As shown in FIG. 32, this conventional data receiving apparatus outputs from an oscillator 1 that outputs a signal of a constant frequency, a frequency divider 2 that divides the output frequency of the oscillator 1, and a frequency divider 2. Detection means 3 for detecting the received signal Sa using the generated free-running clock, clock extraction means 4 for extracting a reference bit clock from the output of the detection means 3, and a digital PLL (for suppressing the jitter amount of the reference bit clock). In the phase-locked loop) means 5 and the digital PLL means, the variable frequency dividing means 6 capable of varying the frequency division ratio of the free-running clock by the control signal, the reference clock output from the clock extracting means 4 and the variable frequency dividing means 6 Phase for outputting a control signal for setting a variable frequency division ratio to the variable frequency dividing means 6 by comparing the phase with the clock output from And compare means 7, further digital PL
A / D conversion means 8 for performing analog-to-digital conversion using the reproduced bit clock output from the L means 5 as a sampling clock, and data decoding means 9 for performing data decoding from the reception signal digitized by the A / D conversion means 8. And a frame synchronizing means 10 for extracting a synchronization word from the decoded data and generating a timer reset signal in synchronization with a frame, and a timer having a reproduced bit clock output from the digital PLL means 5 as a timer clock. And a frame synchronization timing generation means 11 for generating a timing signal synchronized with the frame to the receiving device by resetting the signal with a timer reset signal output from the frame synchronization means 10.

The operation of this apparatus will be described with reference to the block diagram of FIG.

First, the clock reproducing operation in this apparatus will be described. FIG. 33 is a timing example schematically showing the timing of clock reproduction. Clock extraction means 4
Extracts from the output of the detection means 3 a reference clock that is in phase with the symbol identification point and that is synchronized with the bit clock. However, the reference clock has jitter due to Rayleigh fading on the line, noise generated by the radio section of the receiving device, and the like. The bit clock is reproduced by minimizing this jitter component by the digital PLL means 5.

Next, the reception operation and the frame synchronization operation will be described. The A / D conversion means 8 converts the received signal at the symbol identification point into a digital signal by the reproduced bit clock phase-synchronized with the symbol identification point, and the data decoding circuit 9 decodes the decoded data from the converted digital signal. To get FIG. 34 shows a frame configuration example showing the configuration of decoded data. The decoded data is composed of a data part and a sync word part which is known data as shown in FIG.
Data is periodically received by this frame structure.
The data receiving device acquires frame synchronization by taking the bit correlation of the synchronization word from the received signal Sa. FIG.
5 is a timing chart showing a timing example of the frame synchronization timing signal. The frame synchronization means 10 is
When the acquisition of the frame synchronization is detected, a timer reset signal is sent to the frame synchronization timing generating means 11.
The frame synchronization timing generation means 11 has a timer having the same cycle as the TDMA frame, starts a timer count operation in synchronization with the TDMA frame by a timer reset signal, and outputs a frame synchronization timing signal in accordance with the count value of the timer. appear.

[0007]

However, in the conventional data receiving apparatus, a dedicated circuit such as the clock extracting means 4 and the digital PLL means 5 is required to reproduce the bit clock, and the clock extracting means 4 is
Since analog signals are handled, there is a problem in that the circuit becomes complicated and the circuit scale increases when configuring the receiving device. Further, when the phase of the reference clock and the variable frequency dividing means 6 in the digital PLL means 5 deviates by a value close to π at the time of initial synchronization pull-in, there is a problem that the synchronization pull-in takes time.

The present invention solves these conventional problems, eliminates the need for clock extraction means, simplifies the configuration of the digital PLL means, and facilitates these functions with a small amount of calculation by digital signal processing. It is an object of the present invention to provide a data receiving device that can be realized and can perform initial synchronization pull-in at high speed.

[0009]

Therefore, in the present invention, in a data receiving apparatus which decodes data from a received signal, generates a frame synchronization timing signal, and reproduces a bit clock, the received signal is multiplied by N times the symbol rate. A / D conversion means for oversampling with a free-running clock having a frequency of (N is an integer) and digitizing the sample value, and synchronous adding means for synchronously adding the digitized sample value for each symbol interval over a certain period. And a symbol identification point detecting means for detecting a symbol identification point from the synchronous addition result obtained by the synchronous adding means, and a data decoding means for performing data decoding based on a sample value at the symbol identification point detected by the symbol identification point detecting means. And the time-dependent displacement of the symbol identification point detected by the symbol identification point detection means as the phase shift. Phase shift detecting means for outputting, variable frequency dividing means for reproducing the bit clock by dividing the frequency of the free-running clock, and variable frequency dividing means for controlling the frequency dividing ratio of the variable frequency dividing means so as to correct the phase shift. A ratio control means and a frame synchronization timing signal generation means for extracting a known synchronization word from the data decoded by the data decoding means to acquire frame synchronization and generating a frame synchronization timing signal based on the frame synchronization are provided.

Further, the frame synchronization timing signal generating means has a frame synchronization timer using a bit clock as a timer clock, and frame synchronization timing generating means for generating a frame synchronization timing signal based on the count value of the frame synchronization timer, A frame synchronization means for extracting a synchronization word from the decoded data and outputting a timer reset signal of a frame synchronization timer.

Further, in order to synchronize the phase of the variable frequency dividing means, there is provided a phase synchronization control means for resetting the frequency division of the variable frequency dividing means based on the symbol identification points detected by the symbol identification point detecting means.

When the variable frequency division ratio control means sets the normal frequency division ratio of the variable frequency division means to 1 / L, the frequency division ratio of the variable frequency division means is 1 / (L-1), 1 / L. If the phase shift detected by the phase shift detection means cannot be corrected by one control by controlling to either L or 1 / (L + 1), the frequency division ratio of the variable frequency division means is divided into a plurality of times. To control.

Further, the synchronous addition means performs the synchronous addition during the slot reception period of the TDMA frame, and the variable frequency division ratio control means updates the frequency division ratio control of the variable frequency division means at the cycle of the TDMA frame.

Further, the synchronous addition means, the symbol identification point detection means, the phase shift detection means, the variable frequency division ratio control means, the data decoding means and the frame synchronization means are constituted by using a general-purpose DSP (digital signal processor). ing.

Further, the received signal is oversampled by a free-running clock having a frequency of N times the symbol rate (N is an integer), and A / D conversion means for digitizing the sample value, and the digitized sample value With a synchronous addition means for performing synchronous addition over a fixed period at each symbol interval, a symbol identification point detection means for detecting a symbol identification point from the synchronous addition result obtained by the synchronous addition means, and a symbol identification point detected by the symbol identification point detection means. Data decoding means for performing data decoding based on the sample value of, a phase shift detecting means for detecting the displacement of the symbol identification point detected by the symbol identification point detecting means with time as a phase shift, and a free-running clock as a timer clock. It has a frame synchronization timer to enable frame synchronization based on the count value of this frame synchronization timer. A frame synchronization timing generation means for outputting an imming signal and a bit clock, a frame synchronization means for extracting a synchronization word from decoded data and outputting a timer reset signal of a frame synchronization timer, and a phase shift detected by the phase shift detection means. Timer initial value setting means for controlling the initial value of the frame synchronization timer.

Further, the synchronous addition means is configured to perform the synchronous addition on the samples at the three points of the symbol identification point detected based on the immediately preceding synchronous addition result and the sample points before and after the symbol identification point.

Further, there is provided clock generation means for receiving the reception timing signal generated from the frame synchronization timing generation means and supplying the A / D conversion means with the free-running clock as the sampling clock only during the slot reception period.

Further, when the timer initial value setting means changes the initial value of the frame synchronization timer within the range of ± 1 of the timer clock and the phase shift detected by the phase shift detecting means cannot be corrected by one change, The initial value of the frame synchronization timer is changed by dividing the time into multiple times.

Further, the synchronous addition means, the symbol identification point detection means, the phase shift detection means, the timer initial value setting means, the data decoding means and the frame synchronization means are configured by using a general-purpose DSP (digital signal processor). There is.

[0020]

Therefore, the sample point indicating the maximum value of the synchronous addition result obtained by the synchronous addition means becomes the symbol identification point, and the data is decoded based on the digital value at that point. Further, the difference between the previous symbol identification point and the current symbol identification point is a phase shift, and the frequency division ratio of the variable frequency dividing means is varied based on this difference value to reproduce the bit clock. This apparatus does not require the clock extracting means and the phase comparing means in the digital PLL means as in the conventional example, and can regenerate the bit clock by digital signal processing.

Further, in the case where the phase synchronization control means is provided, the frequency division of the variable frequency division means is reset according to the symbol identification point so that the synchronization of the reproduced bit clock can be performed at high speed at the initial synchronization. You can

Further, in the device in which the variable frequency dividing ratio control means controls the frequency dividing ratio of the variable frequency dividing means to any one of 1 / (L-1), 1 / L, and 1 / (L + 1), once. The amount of change in the frequency division ratio of the variable frequency dividing means in the control of 1 is small. When the phase shift is large, this control is performed several times in time. By doing so, the amount of jitter of the reproduced bit clock can be suppressed within one clock supplied to the variable frequency dividing means, and the highly accurate bit clock can be reproduced.

Further, when the synchronous addition period in the synchronous addition means is set in units of one receiving slot, the amount of calculation in phase shift detection and frequency division ratio control can be reduced, and jitter is generated in one TDMA frame. Not able to regenerate the bit clock.

Further, when each means of the data receiving device is realized by using a general-purpose DSP (digital signal processor), the development of hardware is not required and it can be realized only by the software of the DSP. The circuit scale can be reduced and the number of components can be reduced.

Further, in the apparatus provided with the timer initial value setting means, the initial value of the frame synchronization timer of the frame synchronization timing generating means is controlled so as to realize the correction of the phase shift, and based on the count value of this timer. Bit clock and frame sync timing signals are generated. Since this device does not require the clock extracting means, the phase comparing means in the digital PLL means, and the variable frequency dividing means, the circuit scale can be reduced.

Further, when the number of synchronous addition samples in the synchronous addition means is performed only with three samples of the symbol identification point detected by the immediately preceding synchronous addition and the sample points before and after the symbol identification point, the maximum value in the synchronous addition with the three samples is performed. Is a symbol identification point, and next time, synchronous addition is performed on the three samples of the symbol identification point and the sample points before and after the symbol identification point. In this case, the amount of calculation in synchronous addition can be reduced.

In the device provided with the clock generation means, the sampling clock is supplied to the A / D conversion means only while the reception timing signal is being output from the frame synchronization timing generation means, that is, only during the slot reception period. . The A / D conversion means operates intermittently and outputs sampling data to a necessary minimum. Therefore, low power consumption can be achieved.

When the timer initial value setting means controls the timer initial value once within the range of ± 1 count, when the phase shift is large, the timer initial value is temporally divided into a plurality of frames. Control. By doing so, the amount of jitter of the reproduced bit clock can be suppressed within one clock for operating the frame synchronization timer of the frame synchronization timing generating means, and a highly accurate bit clock can be reproduced.

[0029]

【Example】

(First Embodiment) As shown in FIG. 1, a signal generator according to a first embodiment of the present invention outputs an auto-running clock by dividing an oscillator 21 that outputs a signal of a constant frequency and an oscillator 21 output. Frequency divider 22, a detection means 23 for detecting the received signal Sa by a free-running clock, and I, output from the detection means 23.
A / D conversion means 24 for oversampling the Q signal at a sampling frequency N times the symbol rate (N is an integer) by a free-running clock and digitizing it, and one symbol interval is divided into N and oversampled. Value is M symbol periods for each symbol interval (M is an integer)
Synchronous addition means 25 for synchronously adding over and obtaining N synchronous addition results every M symbol periods, and symbol identification point detection means 26 for detecting symbol identification points based on the synchronous addition results output by the synchronous addition means 25. , A data decoding means 27 for performing data decoding at the detected symbol identification point and a phase shift detecting means 28 for detecting a phase shift by comparing the synchronous addition results output from the synchronous adding means 25 before and after in time.
A variable division ratio control means 29 for generating a signal for controlling the variable division ratio to correct the detected phase shift, and a variable division ratio control signal output from the variable division ratio control means 29. A variable frequency dividing means 30 for reproducing a bit clock by varying the frequency division ratio of the free-running clock, and a timer reset signal for synchronizing a frame by extracting a known synchronization word from the decoded data output from the data decoding means 27. The generated frame synchronizing means 31 and the reproduced bit clock generated by the variable frequency dividing means 30 are used as timer clocks, and the frame synchronizing means 31
Frame synchronization timing generating means 32 for holding a timer reset by a timer reset signal output from the device and generating a timing signal synchronized with the frame for the receiving device.

Next, the operation of the data receiving apparatus of the first embodiment will be described. First, the operations of the synchronous addition means 25, the symbol identification point detection means 26, and the data decoding means 27 will be described. Figure 2
FIG. 4 is a diagram schematically showing symbol waveforms of I and Q signals after detection. The calculation contents of the synchronous addition means are as shown in the following (Equation 1).

[Equation 1] Here, for ease of explanation, the sampling rate N of the A / D conversion means 24 is set to 10, and the number of synchronous addition symbols is set to M symbols.

When the detection means 23 detects the reception signal Sa using the free-running clock obtained by dividing the output of the oscillator 21 by the frequency divider 22, the A / D conversion means 24 is detected as shown in FIG. The I and Q signals are analog-digital converted at a sampling rate 10 times the symbol rate. Synchronous addition means 25 is a number 1 for the digitized I and Q signals.
A synchronous addition operation as shown in is performed. The ten results A0 to A9 obtained by the synchronous addition operation have a waveform having a peak as shown in the example of FIG. In FIG.
A5 indicates the maximum value, and at this time, the symbol identification point detecting means 26 determines that the symbol identification point number is 5. The data decoding means 27 performs data decoding at the symbol identification point based on this information.

Next, the operations of the phase shift detection means 28, the variable frequency division ratio control means 29, and the variable frequency division means 30 will be described. FIG. 4 is an explanatory diagram for explaining the operation. FIG. 4 shows an example in which the symbol identification point numbers obtained by the symbol identification point determination for each M symbol change to 5, 5, 6, and 6. The phase shift detecting means 28 outputs the difference between the symbol identification point number based on the synchronous addition of the immediately preceding M symbols and the symbol identification point number based on the current synchronous addition of the M symbols. In FIG. 4, 0, +1 and 0 are output. The variable frequency division ratio control means 29 sets the variable frequency division ratio based on the difference signal obtained from the phase shift detection means 28. Assuming that the normal frequency division ratio is 1 / L, when the difference signal is 0, frequency division is performed by 1 / L, and when it is +1 as shown in FIG. Divide by L + 1). Similarly, when it is -1, the frequency is divided by 1 / (L-1) to regenerate the bit clock.

The operations of the frame synchronization means 31 and the frame synchronization timing generation means 11 of this apparatus are the same as those of the conventional apparatus (FIG. 32).

As described above, in the data receiving apparatus of the first embodiment, the phase shift is detected from the synchronous addition result obtained by the synchronous adding means 25, and the variable frequency dividing means is based on this detection result.
The bit clock is reproduced by changing the division ratio of 30. Therefore, the clock extraction means and the phase comparison means in the digital PLL means provided in the conventional device are unnecessary, and the bit clock can be regenerated through digital signal processing.

(Second Embodiment) The signal generator of the second embodiment can perform the synchronization of the bit clock at a high speed. This apparatus, as shown in FIG. 6, is a phase synchronization control for performing frequency division reset for phase synchronization with the variable frequency division means 61 based on the symbol identification point detected by the symbol identification point detection means 26. A means 60 is provided. The other configuration is the same as that of the data receiving apparatus (FIG. 1) of the first embodiment.

The operation of the data receiving apparatus of the second embodiment is shown in FIG.
Will be explained. For ease of explanation, in the example of the explanatory diagram of FIG. 7, one symbol is sampled at a clock of 10 times, and the modulation method is QPSK, and 1-symbol 2-bit data is put. Further, the bit clock and the symbol clock when the phase synchronization is established have a symbol identification point at the rising position of the clock. The M symbol synchronous addition means 25 performs the synchronous addition of the oversampled sample values over the M symbols up to the symbol number SN, and the symbol identification point detection means 26 determines the position of the symbol identification point based on this synchronous addition result. When information is output, phase synchronization control means
60 is a variable frequency dividing means for adjusting the control signal output timing to control the control signal at the symbol identification point position of the symbol number SN + 1.
Output to 61. The variable frequency dividing means 61 establishes the phase synchronization of the reproduced clock by resetting the frequency division output in accordance with this signal.

This operation is carried out when phase synchronization is established, such as during initial synchronization pull-in.

(Third Embodiment) The data receiving apparatus of the third embodiment performs the correction in a plurality of times when the phase shift is large. As shown in FIG. 8, this device includes a variable frequency dividing means 221 for varying the frequency dividing ratio into three types of 1 / (L-1), 1 / L, and 1 / (L + 1), and a phase shift detecting means 28. And the variable frequency division ratio control means 220 for controlling the variable frequency division ratio of the variable frequency division means 221 in a plurality of times when the detection result is ± 2 or more. This variable division ratio control means 220,
As shown in FIG. 9, the frequency division ratio of the variable frequency dividing means 221 is 1 /
A variable frequency division ratio setting unit 222 that controls either (L-1), 1 / L, or 1 / (L + 1), and the number of times the variable frequency division is performed is counted, and the number of times performs the phase shift correction. A variable frequency division counter 223 is provided for instructing the variable frequency division ratio setting unit 222 to stop the variable frequency division when the number of times is satisfied. The other configuration is the same as that of the data receiving apparatus (FIG. 1) of the first embodiment.

The operations of the phase shift detection means 28, the variable frequency division ratio control means 220, and the variable frequency division means 221 in the data receiving apparatus of the third embodiment will be described with reference to FIGS. 10 and 11. FIG. 10 shows an example in which the symbol identification point numbers obtained by the symbol identification point determination for each M symbol have changed to 5, 8, 8, and 8. In this case, the phase shift detecting means 28 sequentially outputs the difference +3, 0, 0 between the previous symbol identification point number and the current symbol identification point number.

When the value of the output of the phase shift detection circuit is +3,
The variable frequency division ratio setting unit 222 of the variable frequency division ratio control circuit 220 sets the variable frequency division ratio of the variable frequency dividing means 221 to 1 / (L + 1) and causes the variable frequency division counter 223 to perform the variable frequency division. 3 is set as the number-of-times setting value. Variable divider counter 223
Counts the number of times the variable frequency dividing is performed by watching the output of the variable frequency dividing means 221. When the number of times becomes 3,
A variable frequency division stop signal is output to the variable frequency division ratio setting unit 222. In response to this, the variable frequency division ratio setting unit 222 returns the variable frequency division ratio to the normal frequency division 1 / L. FIG. 11 shows the output of the variable frequency dividing means 221 at this time, which is 1 / (L + 1).
After performing the frequency division three times with the frequency division ratio of
Dividing by L.

As described above, in the data receiving apparatus according to the third embodiment, when the absolute value of the output of the phase shift detection circuit is 2 or more, the frequency division number is changed in a plurality of times to change the reproduction bit clock. Correct gently. Therefore, a highly accurate bit clock with little jitter can be reproduced.

(Fourth Embodiment) As shown in FIG. 12, the data receiving apparatus of the fourth embodiment is provided with a synchronous adding means 40 having a synchronous addition period of one reception slot. The other structure is the same as that of the device of the first embodiment.

In this apparatus, as shown in FIG. 13, the synchronous addition means 40 performs the synchronous addition for each reception slot, and the symbol identification point detection means 26 detects the synchronization addition result for each reception slot. The symbol discrimination point determination result is output. The phase shift detection means 28 outputs the difference between the symbol identification points of the previous reception slot and the current reception slot, and when the difference signal is other than 0, the variable frequency division ratio control means 29 immediately after the reception slot, A signal for controlling the frequency division ratio of the variable frequency dividing means 30 is output.

Therefore, in this apparatus, control of the variable frequency division ratio is performed with a period of 1 TDMA frame, and 1 TDM
A jitter-free bit clock is reproduced in the A frame.

(Fifth Embodiment) The data receiving apparatus of the fifth embodiment reduces the amount of calculation in the synchronous addition of samples. As shown in FIG. 14, this apparatus is provided with a synchronous addition means 50 for performing synchronous addition by focusing on three samples. The other structure is the same as that of the apparatus of the first embodiment (FIG. 1).

In this apparatus, the synchronous addition means 50 has a total of three samples of the sample of the symbol identification point detected by the synchronous addition of the immediately preceding M symbol period and the samples of the sample points before and after the symbol identification point over the M symbol period. The symbol identification point detecting means 51 performs the synchronous addition, and
The sample position of the sample showing the maximum value in the synchronous addition results of two samples is determined as the symbol identification point. Then, the synchronous addition means 50 next performs the synchronous addition of three samples at the sample point determined as the symbol identification point and the sample points before and after the sample point over M symbols.

FIG. 15 shows the result of the synchronous addition means 50 performing the synchronous addition of 3 samples. The middle value K of the three samples is the symbol identification point determined by the result of synchronous addition of the previous reception slot. FIG. 9A shows an example in which the same symbol identification point K as that detected by the immediately preceding M symbol is obtained. In this case, the variable frequency dividing means 30 gives a normal 1 / L.
The division is performed according to the division ratio of. Figures (b) and (c) show an example in which a symbol identification point result different from the symbol identification point K detected in the immediately preceding M symbol is obtained.
K- before the sample is detected, and (c) is an example in which K + after the one sample is detected. In the case of the diagram (b), the frequency division is performed once at a frequency division ratio of 1 / (L-1) immediately after K- is detected, and in the case of the diagram (c), immediately after the detection of K +. 1
The frequency division is performed only at a frequency of 1 / (L + 1). Other operations are the same as those of the data receiving apparatus of the first embodiment.

This data receiving device can reduce the amount of calculation in the synchronous addition in a transmission environment in which the phase shift is small, reduce the calculation load on the device, and perform bit clock regeneration at high speed. You can

(Sixth Embodiment) In the data receiving apparatus of the sixth embodiment, as shown in FIG. 16, the synchronous addition means 801 performs synchronous addition by focusing on three samples over one reception slot. The other structure is the same as that of the device of the first embodiment (FIG. 1).

In this apparatus, as shown in FIG. 17, the synchronous addition means 80 performs synchronous addition for three symbols for each reception slot. At this time, when the symbol identification point detection means 81 outputs the symbol identification point K based on the result of the synchronous addition in the previous reception slot, the synchronous addition means 80, in the synchronous addition in the next reception slot, the sample point K and the sample points K before and after it. The synchronous addition is performed for the three samples at the sample points K-1 and K + 1. As a result, when K + 1 is output from the symbol identification point detection means 81 as the symbol identification point, the phase shift detection means 28 outputs 1 as the phase shift, and the variable frequency division ratio control means 29 controls the variable frequency division means 30. The variable frequency division ratio is controlled to 1 / (L + 1). Variable division ratio control means
The control unit 29 controls the variable frequency division ratio for each TDMA frame.

Next, the synchronous addition means 80 determines the sampling point K + 1.
And sample addition at the sample points K and K + 2 before and after that are performed synchronously. Such a procedure is repeated, and in FIG. 17, the symbol identification point detection means output 81 is K, K + 1,
.. are output as symbol identification points.
At this time, the output of the phase shift detecting means 28 is +1, 0, -1.
And the variable division ratios are 1 / (L + 1), 1 / L, 1 /
(L-1). Other operations are the same as those of the data receiving apparatus of the first embodiment.

(Seventh Embodiment) The data receiving apparatus of the seventh embodiment executes the A / D conversion only during the slot receiving period of the TDMA frame. This device, as shown in FIG.
A clock generation means 71 is provided for supplying the free-running clock input from the frequency divider 22 to the A / D conversion means 24 only while the data reception timing signal is sent from the frame synchronization timing generation means 70. The other structure is the same as that of the device of the fourth embodiment (FIG. 12).

When the timer reset signal is input from the frame synchronization means 31 which secures the frame synchronization, the frame synchronization timing generation means 70 of this apparatus resets the possessed timer and generates the timing signal synchronized with the frame. As one of the signals, a data reception timing signal that is turned on only from the start time of the TDMA frame to the counting of a fixed number of clocks corresponding to the slot reception period is generated and output to the clock generation means 71.
The clock generating means 71, as shown in FIG.
A sampling clock that operates only at the time of data reception is generated based on the sampling clock that is an integer multiple of the symbol rate divided by and the data reception timing signal that is sent from the frame synchronization timing generation means 70.
It outputs to the D conversion means 24. The sampling clock has a fixed number of clocks during one reception slot, and is a phase-synchronized clock. A / D conversion means
The 24 samples the received data by this sampling clock and converts it into digital data.

Therefore, in this device, once the frame synchronization is secured, the A / D conversion is intermittently performed only during the reception slot of the TDMA frame. Therefore A
Since the sampling data in the / D conversion can be minimized, power consumption can be reduced.

(Eighth Embodiment) The data receiving apparatus of the eighth embodiment is constructed by using a DSP (digital signal processor). This device, as shown in FIG.
I and Q digitized by A / D conversion means 204
Parallel-serial conversion means 205 for converting signals into serial signals, and I, Q multiplexing means 206 for multiplexing I and Q signals
And I / Q signal separation means 207 for separating the multiplexed I / Q signals, synchronous addition means 208, symbol identification point detection means 209, phase shift detection means 210, variable frequency division ratio control. The means 211, the data decoding means 212, and the frame synchronization means 213 are configured by using a general-purpose DSP 214.

In this device, the parallel-serial conversion means 205 digitizes the I and Q of the A / D conversion means 204.
The signal is converted into a serial signal, and the I, Q multiplexing means 206 multiplexes these I, Q signals. The DSP 214 takes in the serially multiplexed I and Q signals through the serial port, and the I and Q separation means 207 separates them into I and Q signals.

The operations of the synchronous addition means 208, the symbol identification point detection means 209, the phase shift detection means 210, the variable frequency division ratio control means 211, the data decoding means 212, and the frame synchronization means 213 in the DSP 214 are the same as those of the first embodiment. Is the same as. The multiple-bit variable frequency division ratio setting signal obtained by the variable frequency division ratio control means 211 is output to the variable frequency division means 215 via the general-purpose output port of the DSP 214. The timer reset signal obtained by the frame synchronization means 213 in the DSP 214 is output to the frame synchronization timing generation means 216 via the general-purpose output port.

Since this apparatus uses the DSP, no hardware development is required and it can be realized only by the software of the DSP.

(Ninth Embodiment) The data receiving apparatus of the ninth embodiment has a structure in which the initial value of the timer of the frame synchronization timing generating means is directly corrected instead of using the variable frequency dividing means. This apparatus, as shown in FIG. 21, is a timer initial value setting means for correcting and controlling the initial value of the frame synchronization timer possessed by the frame synchronization timing generating means 111 based on the phase shift information obtained by the phase shift detecting means 108.
It has 109. The other structure is the same as that of the data receiving apparatus (FIG. 12) of the fourth embodiment.

The frame synchronization timer of the frame synchronization timing generation means 111 operates with a clock N times the symbol rate. By correcting the initial value of this timer, the reproduced bit clock is output from the frame synchronization timing generating means 111.

The operation of the data receiving apparatus of the ninth embodiment will be described with reference to FIGS. 22 and 23. In FIG. 22, the received I and Q signals are oversampled data at 10 times the symbol rate for ease of explanation. Figure 2
2, the symbol addition point detection means 106 performs symbol identification point detection on the result of the synchronous addition performed by the synchronization addition means 105, and it is determined to be 5, 5, 6, 6, ... Outputs the difference from the previous reception slot, 0, +1, 0, .... The frame synchronization timer in the frame synchronization timing generating means 111 is 1T.
Assuming that the DMA frame is down-counted by a count number T, the output of the timer initial value setting means 109 is output as T, T + 1, T, ... And the frame synchronization timer changes the initial value of the timer. Then, the counting operation as shown in FIG. 23 is performed. Other operations are the same as those of the data receiving apparatus of the fourth embodiment.

Therefore, by adopting this configuration, it is possible to regenerate the bit clock by digital signal processing without requiring the clock extracting means and the phase comparing means in the digital PLL means as in the conventional example.
Furthermore, since the variable frequency dividing means in the first embodiment can also be deleted, it is possible to realize a circuit scale smaller than that in the first embodiment.

(Tenth Embodiment) The data receiving apparatus of the tenth embodiment corrects the initial value of the timer of the frame synchronization timing generating means by dividing it into plural times when the phase shift is large.

As shown in FIG. 24, this apparatus is provided with a timer initial value setting means 224 for correcting the initial value of the frame synchronization timer of the frame synchronization timing generating means 225 by ± 1 count each. This timer initial value setting means 224
As shown in FIG. 25, even when the detection result of the phase shift detecting means is 2 or more, the timer initial value setting control unit 226 that changes the initial value of the timer by ± 1 count and the change of the timer initial value are A frame number counter 227 that counts the number of frames performed and, when the number reaches a number that satisfies the correction of the phase shift, instructs the timer initial value setting control unit 226 to stop changing the timer initial value. There is. The other structure is the same as that of the data receiving apparatus (FIG. 21) of the ninth embodiment.

The operation of the data receiving apparatus of the tenth embodiment will be described with reference to FIG. FIG. 26 shows an example in which the symbol identification point numbers obtained by the symbol identification point determination for each reception slot are changed to 5, 7, 7, 7. The phase shift detecting means 108 outputs the difference between the symbol identification point number of the previous reception slot and the symbol identification point number of the current reception slot. The output of the phase shift detecting means 108 is +2, 0, 0. From the phase shift detection means 108 +
The timer initial value control unit 226 that has received the notification of the phase shift of 2
Notifies the frame number counter 227 of 2 as the initial value change frame number, and sets the timer initial value of the frame synchronization timing generating means 225 to T + 1.

The frame synchronization timer of the frame synchronization timing generation means 225 repeats the down count with the set T + 1 as a cycle. The frame counter 227
The number of frames in which the timer initial value is changed is counted, and when the number becomes 2, the timer initial value setting control unit 226
To the timer initial value variable stop. In response to this, the timer initial value setting control unit 226 returns the timer initial value to the normal T.

In this way, when the absolute value of the output of the phase shift detection circuit is 2 or more, TDMA is performed a plurality of times in time.
The initial value of the timer is changed for each frame.

Further, if the symbol identification point number becomes 5 in the first reception slot, and then 7, 9, 9 and 2TD
In the MA frame, if the symbol identification point changes by 4 samples, at this time, the timer initial value is T + for 4 consecutive slots.
Set to 1. Other operations are the same as those of the data receiving apparatus of the ninth embodiment.

Therefore, by adopting this configuration, the jitter amount of the reproduced bit clock can be suppressed within one clock for operating the frame synchronization timer in the frame synchronization timing generating means, and the highly accurate bit clock can be reproduced. . Further, the variable frequency dividing means in the third embodiment can be eliminated, and the circuit scale can be further reduced as compared with the third embodiment.

(Eleventh Embodiment) As shown in FIG. 27, the data receiving apparatus of the eleventh embodiment replaces the synchronous adding means in the apparatus of the ninth embodiment (FIG. 21) with 3 reception slots. A synchronous addition means 120 is used for performing synchronous addition by focusing on one sample. The other structure is the same as that of the data receiving apparatus of the ninth embodiment. This synchronous addition means 120 is the same as that used in the device of the sixth embodiment (FIG. 16), and in each reception slot period, the symbol identification point obtained by the synchronous addition of the preceding reception slot period. And synchronous addition is performed on three samples of the sample points before and after.

The operation of the data receiving apparatus of the 11th embodiment will be described with reference to FIG. The synchronous addition means 120 performs addition operation of samples at the symbol identification point K obtained by the symbol identification point detection means 106 in the previous reception slot and the sample points before and after the symbol identification point K over the reception slot period,
The symbol discriminating point detecting means 106 is a sample point K-, K or K showing the maximum value in the synchronous addition result of the three samples.
+ Is output as the detection result. Here, K is a symbol identification point in the previous reception slot, K− represents a sample point one sample before, and K + represents a sample point one sample after that. In the example of FIG. 28, the output 106 of the symbol identification point detection means is K, K + 1, K, K−1, ..., At this time, the phase shift detection means 108 outputs 0, +1,
0, -1, ... Are output and under the control of the timer initial value setting means 109, the frame synchronization timing output control means 111
The initial value of the frame synchronization timer is T, T + 1, T, T
-1, ... The other operations are the same as those of the data receiving apparatus of the ninth embodiment.

Therefore, by using this configuration, the amount of calculation can be reduced because the calculation in the synchronous addition means needs to be performed for only three samples. Further, the variable frequency dividing means in the sixth embodiment can be eliminated, and the circuit scale can be further reduced as compared with the sixth embodiment.

(Twelfth Embodiment) As shown in FIG. 29, the data receiving apparatus according to the twelfth embodiment is similar to the data receiving apparatus according to the ninth embodiment (FIG. 21) in that the A / D conversion means 104 performs sampling. A clock generation means 131 for supplying a clock is added. This clock generation means 131 is the same as that used in the seventh embodiment (FIG. 18), and the clock is generated from the frequency divider 102 only while the data reception timing signal is sent from the frame synchronization timing generation means 130. The input free-running clock is supplied to the A / D conversion means 104.

The frame synchronization timing generation means 130 of this apparatus is the frame synchronization means 110 which secures the frame synchronization.
When a timer reset signal is input from, and a signal for setting an initial value is input from the timer initial value setting means 109,
Generate a timing signal that is synchronized with the frame. As one of the signals, a data reception timing signal that is turned on only from the start time of the TDMA frame to the count of a fixed number of clocks corresponding to the slot reception period is generated and output to the clock generation means 131. The clock generation means 131, as shown in FIG. 30, has a sampling clock that is an integral multiple of the symbol rate divided by the frequency divider 102,
Based on the data reception timing signal sent from the frame synchronization timing generation means 130, a sampling clock that operates only at the time of data reception is generated and output to the A / D conversion means 104. The sampling clock has a fixed number of clocks during one reception slot, and is a phase-synchronized clock. The A / D conversion means 104 is
The received data is sampled by this sampling clock and converted into digital data.

Therefore, in this device, once the frame synchronization is secured, the A / D conversion is intermittently performed only during the reception slot of the TDMA frame. Therefore A
Since the sampling data in the / D conversion can be minimized, power consumption can be reduced.
Further, the circuit scale can be further reduced as compared with the seventh embodiment.

(Thirteenth Embodiment) As shown in FIG. 31, the data receiving apparatus of the thirteenth embodiment has a synchronous adding means 141 and a symbol identification point detecting means 142 in the data receiving apparatus of the ninth embodiment (FIG. 21). The phase shift detection means 143, the timer initial value setting means 144, the data decoding means 140, and the frame synchronization means 145 are configured by using a general-purpose DSP (digital signal processor) 146.

In this device, as in the device of the eighth embodiment using the DSP, the parallel-serial conversion means 147.
Is I digitized by the A / D conversion means 104.
And Q signals are converted into serial signals, and I and Q multiplexing means 14
8 multiplexes the I and Q signals. I and Q of DSP146
The separating means 149 takes in the serially multiplexed I and Q signals from the serial port and separates them into I and Q signals.

The operations of the synchronous addition means 141, the symbol identification point detection means 142, the phase shift detection means 143, the timer initial value setting means 144, the data decoding means 140, and the frame synchronization means 145 in the DSP 146 are the same as those in the ninth embodiment. It is no different from the case of the receiving device. The timer initial value setting signal output from the timer initial value setting means 144 is input to the frame synchronization timing generating means 111 via the general-purpose output port of the DSP 146, and the timer reset signal output from the frame synchronization means 145 is also general-purpose output. It is input to the frame synchronization timing generating means 111 via the port. The operation of the frame synchronization timing generation means 111 that receives these signals is as follows.
There is no difference from the case of the embodiment.

This device does not require dedicated hardware and can be realized only by the software of the DSP.
The circuit scale of the data receiving device can be reduced, and the number of parts can be reduced.

[0080]

As is apparent from the above description of the embodiments, the data receiving apparatus of the present invention has the following effects.

(1) In the data receiving apparatus of the present invention, the phase shift is detected based on the synchronous addition result obtained by the synchronous adding means, the frequency division ratio of the variable frequency dividing means is varied, and the bit clock is reproduced. There is. Therefore, unlike the conventional example, the clock extraction means and the phase comparison means in the digital PLL means are not required, and the bit clock can be reproduced by the digital signal processing.

(2) In the apparatus provided with the phase synchronization control means for resetting the frequency division of the variable frequency division means based on the symbol identification point obtained by the symbol identification point detection means, the synchronization pull-in is performed at high speed at the initial synchronization pull-in. Can be done.

(3) The frequency division ratio of the variable frequency dividing means is 1 / (L-
1), 1 / L, 1 / (L + 1), and when the detection result of the phase shift detecting means is 2 or more, it is configured to perform variable frequency division in a plurality of times. Then, the jitter amount of the reproduced bit clock can be suppressed within one clock supplied to the variable frequency dividing means, and the highly accurate bit clock can be reproduced.

(4) In a device in which the synchronous addition period in the synchronous addition means is set in units of one receiving slot, the amount of calculation in phase shift detection and frequency division ratio control can be reduced, and jitter is reduced within the receiving slot period. It is possible to regenerate the bit clock that does not occur.

(5) In an apparatus which reduces the number of synchronous addition samples in the synchronous addition means to 3 samples, the amount of calculation in the synchronous addition can be reduced.

(6) In an apparatus in which the synchronous addition period in the synchronous addition means is one reception slot, the frequency division ratio of the variable frequency division means is controlled in one TDMA frame cycle, and the number of synchronous addition samples is narrowed down to three samples, Phase shift detection,
The amount of calculation in variable frequency division control and synchronous addition can be reduced.

(7) In the device provided with the clock generation means for supplying the sampling clock to the A / D conversion means according to the data reception timing signal, the A / D conversion is intermittently performed only during the data reception period. Therefore, low power consumption can be achieved.

(8) A device in which the synchronous addition means, the symbol identification point detection means, the phase shift detection means, the variable frequency division ratio control means, the data decoding means, and the frame synchronization means are constituted by a general-purpose DSP (digital signal processor). In this case, since the hardware development is not required and the software can be realized only by the DSP, the circuit scale of the data receiving device can be reduced and the number of parts can be reduced.

(9) In the device which controls the initial value of the frame synchronization timer of the frame synchronization timing generating means based on the phase shift information, the variable frequency dividing means can be deleted, so that the circuit scale is further reduced. Can be realized.

(10) Based on the phase shift information, the initial value of the frame synchronization timer of the frame synchronization timing generating means is controlled, and when the phase shift is large, the timer initial value is divided into a plurality of times in time. In the device for controlling (1), it is possible to reproduce the bit clock with high accuracy while reducing the circuit scale.

(11) In an apparatus which controls the initial value of the frame synchronization timer of the frame synchronization timing generating means based on the phase shift information and performs the synchronous addition for obtaining the phase shift information by confining to 3 samples, The amount of calculation can be reduced, the variable frequency dividing means can be eliminated, and the circuit scale can be further reduced.

(12) A clock which controls the initial value of the frame synchronization timer of the frame synchronization timing generation means based on the phase shift information and supplies the sampling clock to the A / D conversion means in accordance with the data reception timing signal. In the device provided with the generation means, the A / D conversion is performed intermittently to realize low power consumption and further reduce the circuit scale.

(13) A device for controlling the initial value of the frame synchronization timer of the frame synchronization timing generation means based on the phase shift information, which is a synchronization addition means, a symbol identification point detection means, a phase shift detection means, and a timer. In the device in which the initial value setting means, the data decoding means, and the frame synchronization means are configured by using a general-purpose DSP, dedicated hardware is not required and can be realized only by the software of the DSP. Therefore, the circuit scale of the data receiving device Can be reduced, and the number of parts can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data receiving apparatus according to a first embodiment,

FIG. 2 is an explanatory view for explaining the operation of the synchronous addition means of the device of the first embodiment,

FIG. 3 is an explanatory view for explaining the operation of a symbol identification point detecting means of the apparatus of the first embodiment,

FIG. 4 is an explanatory view for explaining the operation of the phase shift detection means and the variable frequency division ratio control means of the device of the first embodiment;

FIG. 5 is an explanatory view explaining the operation of the variable frequency dividing means of the device of the first embodiment;

FIG. 6 is a block diagram showing a configuration of a data receiving device according to a second embodiment,

FIG. 7 is an explanatory view for explaining the operation of the phase synchronization control means of the apparatus of the second embodiment,

FIG. 8 is a block diagram showing a configuration of a data receiving device according to a third embodiment,

FIG. 9 is a block diagram showing a configuration of a variable frequency division ratio control means of an apparatus according to a third embodiment,

FIG. 10 is an explanatory view explaining the operation of the variable frequency division ratio control means of the device of the third embodiment;

FIG. 11 is an explanatory view for explaining the operation of the variable frequency division ratio control means of the device of the third embodiment;

FIG. 12 is a block diagram showing a configuration of a data receiving apparatus according to a fourth embodiment,

FIG. 13 is an explanatory view explaining the operation of the apparatus of the fourth embodiment,

FIG. 14 is a block diagram showing a configuration of a data receiving device according to a fifth embodiment,

FIG. 15 is an explanatory view explaining the operation of the synchronous addition means of the device of the fifth embodiment;

FIG. 16 is a block diagram showing a configuration of a data receiving device according to a sixth embodiment,

FIG. 17 is an explanatory view explaining the operation of the apparatus of the sixth embodiment,

FIG. 18 is a block diagram showing the configuration of a data receiving device according to a seventh embodiment.

FIG. 19 is an explanatory view explaining the operation of the apparatus of the seventh embodiment,

FIG. 20 is a block diagram showing the configuration of a data receiving device according to an eighth embodiment,

FIG. 21 is a block diagram showing the configuration of a data receiving device according to a ninth embodiment,

FIG. 22 is an explanatory view explaining the operation of the apparatus of the ninth embodiment,

FIG. 23 is an explanatory view explaining the operation of the device of the ninth embodiment;

FIG. 24 is a block diagram showing the configuration of a data receiving device according to a tenth embodiment.

FIG. 25 is a block diagram showing the configuration of variable frequency division ratio control means of the device of the tenth embodiment.

FIG. 26 is an explanatory view explaining the operation of the apparatus of the tenth embodiment.

FIG. 27 is a block diagram showing the structure of a data receiving device according to an eleventh embodiment.

FIG. 28 is an explanatory view explaining the operation of the apparatus of the eleventh embodiment.

FIG. 29 is a block diagram showing the structure of a data receiving device according to a twelfth embodiment.

FIG. 30 is an explanatory view explaining the operation of the apparatus of the twelfth embodiment.

FIG. 31 is a block diagram showing the structure of a data receiving device according to a thirteenth embodiment.

FIG. 32 is a block diagram showing a configuration of a conventional data receiving device,

FIG. 33 is a timing chart for explaining the operation of the bit clock recovery unit of the conventional device,

FIG. 34 is an explanatory diagram showing a frame structure of received data;

FIG. 35 is a timing chart explaining generation of a frame synchronization timing signal of a conventional device.

[Explanation of symbols]

1, 21, 101, 201 Oscillator 2, 22, 102, 202 Frequency divider 3, 23, 103, 203 Detector 4 Clock extraction circuit 5 Digital PLL 6 Variable frequency divider 7 Phase comparator 8, 24, 104, 204 A / D converter 9, 27, 107 Data decoding circuit 10, 31, 110 Frame synchronization circuit 11, 32, 70, 111, 130, 216, 225 Frame synchronization timing generation circuit 25 M symbol synchronization addition circuit 26, 51, 81 , 106 Symbol identification point detection circuit 28, 52, 108 Phase shift detection circuit 29, 53, 220 Variable frequency division ratio control circuit 30, 61, 215, 221 Variable frequency division circuit 40, 105 1 Receive slot synchronous addition circuit 50 M symbol 3 sample synchronous adder circuit before and after 60 Phase synchronous control circuit 71, 131 Clock generating circuit 80, 120 1 receive slot 3 sample synchronous adder circuit before and after 109, 224 Timer initial value setting circuit 140, 212 Data decoding section 141, 208 M symbol synchronous adder Part 142, 209 Symbol identification point detector 143, 210 Phase shift detection unit 144 Timer initial value setting unit 145, 213 Frame synchronization unit 146, 214 DSP 147, 205 Parallel-serial conversion circuit 148, 206 IQ multiplexing circuit 149, 207 IQ separation unit 211 Variable division ratio control unit 222 Variable division Frequency ratio setting unit 223 Variable frequency division counter 226 Timer initial value setting control unit 227 Frame number counter

Claims (11)

[Claims] 1. A data receiving apparatus for decoding data from a received signal, generating a frame synchronization timing signal, and recovering a bit clock, wherein the received signal has a frequency N times (N is an integer) the symbol rate. A / D conversion means for oversampling with a running clock to digitize the sampled value, synchronous addition means for synchronously adding the digitized sample value for each symbol interval over a certain period, and the synchronous addition means Symbol identification point detection means for detecting a symbol identification point from the result of synchronous addition, data decoding means for performing data decoding based on the sample value at the symbol identification point detected by the symbol identification point detection means, and the symbol identification check Phase that detects displacement with time of symbol identification point detected by output means as phase shift Frequency detecting means, variable frequency dividing means for reproducing the bit clock by dividing the frequency of the free-running clock, and variable frequency dividing means for controlling the frequency dividing ratio of the variable frequency dividing means so as to correct the phase shift. A ratio control means and a frame synchronization timing signal generation means for extracting a known synchronization word from the data decoded by the data decoding means to acquire frame synchronization and generating a frame synchronization timing signal based on the frame synchronization timing are provided. Characteristic data receiving device. 2. The frame synchronization timing signal generation means has a frame synchronization timer using the bit clock as a timer clock, and generates the frame synchronization timing signal based on the count value of the frame synchronization timer. 2. The data receiving apparatus according to claim 1, comprising means and frame synchronization means for extracting the synchronization word from decoded data and outputting a timer reset signal of the frame synchronization timer. 3. Phase synchronization control means for resetting the frequency division of the variable frequency dividing means based on the symbol identification point detected by the symbol identification point detecting means in order to achieve phase synchronization of the variable frequency dividing means is provided. The data receiving apparatus according to claim 1, wherein the data receiving apparatus is provided. 4. When the variable frequency division ratio control means sets the normal frequency division ratio of the variable frequency division means to 1 / L, the frequency division ratio of the variable frequency division means is 1 / (L-1). , 1 / L or 1 / (L
+1), and when the phase shift detected by the phase shift detection means cannot be corrected by the single control, the frequency division ratio of the variable frequency dividing means is controlled in a plurality of times. The data receiving device according to claim 1, wherein 5. The synchronous addition means performs the synchronous addition during the slot reception period of the TDMA frame, and the variable frequency division ratio control means controls the frequency division ratio of the variable frequency division means in the cycle of the TDMA frame. The data receiving device according to claim 1, which is updated. 6. The general-purpose DSP (digital signal processor) is used for the synchronous addition means, the symbol identification point detection means, the phase shift detection means, the variable frequency division ratio control means, the data decoding means and the frame synchronization means. The data receiving device according to claim 1, wherein 7. A data receiving apparatus that decodes data from a received signal, generates a frame timing signal, and recovers a bit clock. The received signal is free-running with a frequency N times (N is an integer) the symbol rate. A / D conversion means for oversampling with a clock to digitize the sample value, synchronous addition means for synchronously adding the digitized sample value for each symbol interval over a fixed period, and synchronization obtained by the synchronous addition means Symbol identification point detection means for detecting a symbol identification point from the addition result, data decoding means for performing data decoding based on the sample value at the symbol identification point detected by the symbol identification point detection means, and the symbol identification point detection Phase shift that detects displacement with time of symbol identification point detected by means as phase shift Output means, a frame synchronization timer having the free-running clock as a timer clock, and a frame synchronization timing generation means for outputting a frame synchronization timing signal and a bit clock based on the count value of the frame synchronization timer; Frame synchronization means for extracting a synchronization word and outputting a timer reset signal of the frame synchronization timer, and timer initial value setting means for controlling the initial value of the frame synchronization timer based on the phase shift detected by the phase shift detection means. And a data receiving device. 8. The synchronous addition means performs synchronous addition on samples at three points of a symbol identification point detected based on the immediately preceding synchronous addition result and sample points before and after the symbol identification point. The data receiving device according to 5 or 7. 9. The A / D receiver receives a reception timing signal generated from the frame synchronization timing generating means.
8. The data receiving apparatus according to claim 5, wherein the conversion means is provided with clock generation means for supplying the free-running clock as a sampling clock only during a slot reception period. 10. The timer initial value setting means changes the initial value of the frame synchronization timer within a range of ± 1 of a timer clock, and the phase shift detected by the phase shift detecting means is corrected by one change. The data receiving apparatus according to claim 7, wherein when it is not possible, the initial value of the frame synchronization timer is changed in a plurality of times in terms of time. 11. The general-purpose DSP includes the synchronous addition means, the symbol identification point detection means, the phase shift detection means, the timer initial value setting means, the data decoding means and the frame synchronization means.
The data receiving apparatus according to claim 7, wherein the data receiving apparatus is configured by using a (digital signal processor).