JPH11354523A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH11354523A
JPH11354523A JP11141082A JP14108299A JPH11354523A JP H11354523 A JPH11354523 A JP H11354523A JP 11141082 A JP11141082 A JP 11141082A JP 14108299 A JP14108299 A JP 14108299A JP H11354523 A JPH11354523 A JP H11354523A
Authority
JP
Japan
Prior art keywords
film
forming
oxide film
resist
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11141082A
Other languages
Japanese (ja)
Inventor
Kazutoshi Koshihisa
和俊 越久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11141082A priority Critical patent/JPH11354523A/en
Publication of JPH11354523A publication Critical patent/JPH11354523A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the uniformity of gate dimension by providing an oxide film to flatten a substrate and form a reflection prevention film thereon. SOLUTION: A polycrystalline silicon 9 is formed by the CVD method and a liquid oxide film 12 is formed thereon to flatten the substrate, and further a nitride film 13 as a reflection prevention film is formed thereon by the CVD method. Next, a resist 11 is applied thereon. Since the uniformity of resist film is kept during mask matching and the reflection prevention film is provided, influence of stationary wave effect is not given, thereby obtaining a pattern having less variation of finishing dimension of resist. A nitride film 13, an oxide film 12 and a polycrystalline silicon 9 are dry-etched thereafter, and the nitride film 13 and oxide film 12 are removed, so that a gate pattern having less variation of dimension can be realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、半導体装置の製
造方法に関するものであり、特にパターンの寸法精度向
上に係る半導体装置の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for improving pattern dimensional accuracy.

【0002】[0002]

【従来の技術】半導体基板上に形成されるレジストパタ
ーンは、一般に半導体基板上にゲート電極等のパターン
を形成するためのエッチングマスクとして使用されてい
る。以下に第2図のゲート形成方法を例にして、従来の
レジストパターンをマスクとした半導体装置の製造方法
を説明する。第2図は、従来の半導体装置のゲート形成
工程を示す。断面図において、(1)は基板、(2)は
窒化膜(3)によるストレス緩和のための酸化膜、
(3)は酸化膜(4)を選択酸化するための窒化膜、
(4)は酸化膜、(5)は窒化膜(6)のストレス緩和
のための酸化膜、(6)は分離酸化膜(7)を選択酸化
するための窒化膜、(7)は活性領域間を分離するため
の分離酸化膜、(8)はNウエル領域、(9)はゲート
となるシリコン酸化膜、(10)はゲート酸化膜、(1
1)はレジストである。
2. Description of the Related Art A resist pattern formed on a semiconductor substrate is generally used as an etching mask for forming a pattern such as a gate electrode on the semiconductor substrate. A method of manufacturing a semiconductor device using a conventional resist pattern as a mask will be described below with reference to the gate forming method of FIG. 2 as an example. FIG. 2 shows a gate forming process of a conventional semiconductor device. In the cross-sectional view, (1) is a substrate, (2) is an oxide film for stress relaxation by a nitride film (3),
(3) a nitride film for selectively oxidizing the oxide film (4);
(4) is an oxide film, (5) is an oxide film for relaxing stress of the nitride film (6), (6) is a nitride film for selectively oxidizing the isolation oxide film (7), and (7) is an active region. (8) is an N-well region, (9) is a silicon oxide film serving as a gate, (10) is a gate oxide film, (1)
1) is a resist.

【0003】次に、従来の半導体装置のゲート形成工程
について説明する。始めに第2図(a)において、P型
基板(1)上に熱酸化膜(2)を形成し、その上に窒化
膜(3)をCVD法で形成し、Nウエル領域(8)を形
成するためにマスク合わせを行い、窒化膜(3)をエッ
チングする。次に(b)図において、リンを注入し、熱
拡散を行いながら、熱酸化膜(4)を形成する。つい
で、(c)図の如く、窒化膜(3)を除去し、酸化膜を
ウエットエッチングで除去することにより、Nウエル領
域が形成される。この時次工程とのマスク合わせを行う
ために段差が必要なため、酸化膜(4)の形成が必要で
ある。
Next, a gate forming process of a conventional semiconductor device will be described. First, in FIG. 2 (a), a thermal oxide film (2) is formed on a P-type substrate (1), a nitride film (3) is formed thereon by a CVD method, and an N-well region (8) is formed. Mask formation is performed to form the nitride film, and the nitride film (3) is etched. Next, in FIG. 2B, a thermal oxide film (4) is formed while phosphorus is implanted and thermal diffusion is performed. Next, as shown in FIG. 3C, the nitride film (3) is removed, and the oxide film is removed by wet etching to form an N-well region. At this time, an oxide film (4) needs to be formed because a step is required for mask alignment with the next step.

【0004】次に、(d)図のように、酸化膜(5)を
形成し、その上に窒化膜(6)を形成し、活性領域の分
離を行うためのマスク合わせを行い、窒化膜(6)をエ
ッチングする。さらに(e)図のように、熱酸化を行
い、酸化膜(7)を形成し、窒化膜(6)を除去し、酸
化膜(5)を除去するウエットエッチングを行い分離酸
化膜(7)が形成される。
Next, as shown in FIG. 1D, an oxide film (5) is formed, a nitride film (6) is formed thereon, and a mask alignment for separating an active region is performed. (6) is etched. Further, as shown in FIG. 7E, thermal oxidation is performed to form an oxide film (7), the nitride film (6) is removed, and wet etching is performed to remove the oxide film (5). Is formed.

【0005】次に(f)図のように、ゲート酸化膜(1
0)を熱酸化で形成した後、多結晶シリコンン膜(9)
をCVD法で形成する。さらに(g)図の如く、レジス
ト(11)を塗布し、さらに(h)図のように、多結晶
シリコン膜(9)をドライエッチングし、レジスト除去
し、ゲートが形成される。
[0005] Next, as shown in FIG.
0) is formed by thermal oxidation, and then a polycrystalline silicon film (9) is formed.
Is formed by a CVD method. Further, as shown in (g), a resist (11) is applied, and as shown in (h), the polycrystalline silicon film (9) is dry-etched and the resist is removed to form a gate.

【0006】[0006]

【発明が解決しようとする課題】従来の半導体装置の製
造方法は以上のように形成されていたので、Nウエル領
域の活性領域と基板上の活性領域の高さが異なるため、
それぞれの領域の活性領域上で、レジスト膜厚が異な
り、そのため、マスク合わせ時に定存波効果により、レ
ジストの寸法がNウエル領域上とウエル以外の領域で異
なってしまい、従ってゲートの寸法の均一性が悪くなっ
てしまうという問題点があった。この発明は、上記のよ
うな問題点を解消するためになされたもので、ゲート寸
法の均一性を向上できるような半導体装置の製造方法を
得ることを目的とする。
Since the conventional method for manufacturing a semiconductor device is formed as described above, the active region in the N-well region and the active region on the substrate have different heights.
The resist film thickness on the active region in each region is different. Therefore, the resist dimension differs between the N-well region and the region other than the well due to the standing wave effect at the time of mask alignment. There was a problem that the property became worse. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a method of manufacturing a semiconductor device capable of improving the uniformity of gate dimensions.

【0007】[0007]

【課題を解決するための手段】第1の発明に係る半導体
装置の製造方法は、半導体基板上にパターン被形成膜を
形成する工程と、前記パターン被形成膜上に酸化膜を形
成する工程と、前記酸化膜上に窒化膜を形成する工程
と、前記窒化膜上にレジストを形成する工程と、前記レ
ジストにレジストパターンを形成する工程と、前記窒化
膜、前記酸化膜、前記パターン被形成膜をエッチングし
て、第1および第2のパターン被形成膜のパターンを形
成する工程とを有する半導体装置の製造方法において、
前記半導体基板の裏面から第1のパターン被形成膜の表
面までの高さと前記半導体基板の裏面から第2のパター
ン被形成膜の表面までの高さが異なるようにしたもので
ある。
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a pattern forming film on a semiconductor substrate; and forming an oxide film on the pattern forming film. Forming a nitride film on the oxide film, forming a resist on the nitride film, forming a resist pattern on the resist, forming the nitride film, the oxide film, and the film on which the pattern is formed. Forming a pattern of the first and second pattern formation films by etching the film.
The height from the back surface of the semiconductor substrate to the surface of the first pattern formation film is different from the height from the back surface of the semiconductor substrate to the surface of the second pattern formation film.

【0008】第2の発明に係る半導体装置の製造方法
は、半導体基板上に活性領域と分離領域を形成する工程
と、前記活性領域上および前記分離領域上にパターン被
形成膜を形成する工程と、前記パターン被形成膜上に酸
化膜を形成する工程と、前記酸化膜上に窒化膜を形成す
る工程と、前記窒化膜上にレジストを形成する工程と、
前記レジストにレジストパターンを形成する工程と、前
記窒化膜、前記酸化膜、前記パターン被形成膜をエッチ
ングして、パターン被形成膜のパターンを形成する工程
とを有する半導体装置の製造方法において、前記パター
ン被形成膜は前記活性領域と前記分離領域により段差を
有するようにしたものである。
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an active region and an isolation region on a semiconductor substrate; and forming a pattern formation film on the active region and the isolation region. Forming an oxide film on the pattern formation film, forming a nitride film on the oxide film, and forming a resist on the nitride film;
Forming a resist pattern on the resist; and etching the nitride film, the oxide film, and the pattern-formed film to form a pattern of the pattern-formed film. The pattern formation film has a step due to the active region and the isolation region.

【0009】[0009]

【発明の実施の形態】以下、この発明の一実施例を図を
用いて説明する。第1図(a)〜(f)は、この発明の
半導体装置のゲート形成工程を示す断面図である。な
お、図中符号(1)〜(11)は、前記従来のものと同
一につきその説明は省略する。図において(12)は塗
布装置で塗布される液体酸化膜、(13)は反射防止膜
として働く窒化膜である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. 1 (a) to 1 (f) are cross-sectional views showing a gate forming step of the semiconductor device of the present invention. The reference numerals (1) to (11) in the figure are the same as those of the related art, and the description thereof is omitted. In the figure, (12) is a liquid oxide film applied by a coating apparatus, and (13) is a nitride film acting as an antireflection film.

【0010】次に製造工程について説明する。多結晶シ
リコン(9)をCVD法で形成した第2図(f)までは
前記従来のものと同一であり、始めに第1図(b)にお
いて、多結晶シリコン(9)上に基板上の平坦化を図る
ための液化酸化膜(12)を塗布し、さらにその上に反
射防止膜として窒化膜(13)をCVD法で形成する。
次にこの上に(c)図のようにレジスト(11)を塗布
する。
Next, the manufacturing process will be described. 2 (f), in which the polycrystalline silicon (9) is formed by the CVD method, is the same as the conventional one. First, in FIG. 1 (b), the polycrystalline silicon (9) is A liquefied oxide film (12) for flattening is applied, and a nitride film (13) is formed thereon by a CVD method as an antireflection film.
Next, a resist (11) is applied thereon as shown in FIG.

【0011】この後、(d)図の如くマスク合わせを行
う時、レジスト膜厚の均一性が良く、また反射防止膜を
備えているため定存波効果の影響を受けなくなり、レジ
ストの仕上り寸法ばらつきの少ないパターンが得られ
る。この後、(e)図の如く窒化膜(13)、酸化膜
(12)、多結晶シリコン(9)をドライエッチング
し、さらに(f)図のように窒化膜(13)、酸化膜
(12)を除去することにより、寸法ばらつきの少ない
ゲートパターンを得ることができる。
Thereafter, when mask alignment is performed as shown in FIG. 1D, the uniformity of the resist film thickness is good, and since the anti-reflection film is provided, the resist is not affected by the standing wave effect. A pattern with little variation can be obtained. Thereafter, the nitride film (13), the oxide film (12) and the polycrystalline silicon (9) are dry-etched as shown in FIG. (E), and the nitride film (13) and the oxide film (12) as shown in FIG. By removing (), a gate pattern with small dimensional variation can be obtained.

【0012】なお、上記実施例では、反射防止膜とし
て、窒化膜(13)を設け場合を示したが、多結晶シリ
コンや、金属シリサイドたとえば、モリブデンシリコ
ン、タングステンシリコンでも同様の効果を奏する。ま
た、平坦性を向上させるための酸化膜(12)自身が、
反射防止膜として働くものであれば、酸化膜上の反射防
止膜(13)は不要にしても同様の効果を奏する。
In the above embodiment, the case where the nitride film (13) is provided as the antireflection film has been described. However, the same effect can be obtained with polycrystalline silicon or metal silicide such as molybdenum silicon or tungsten silicon. Further, the oxide film (12) itself for improving flatness is
As long as it functions as an anti-reflection film, the same effect can be obtained even if the anti-reflection film (13) on the oxide film is unnecessary.

【0013】[0013]

【発明の効果】以上のように、この発明によれば、平坦
性向上のための酸化膜を備え、その上に反射防止膜を形
成したので、ゲートパターニングのためのレジスト膜厚
の均一性が良くなり、また反射防止膜は、パターンニン
グ時に、平坦性向上のための酸化膜の影響がレジストに
及ばないので、定存波効果によりゲートレジストパター
ンの寸法のばらつきを小さくできる。
As described above, according to the present invention, the oxide film for improving the flatness is provided, and the antireflection film is formed thereon. In addition, the antireflection film does not affect the resist at the time of patterning because of the oxide film for improving the flatness. Therefore, the variation in the size of the gate resist pattern can be reduced by the standing wave effect.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 この発明の一実施例である半導体装置のゲー
ト形成工程を示す断面図である。
FIG. 1 is a cross-sectional view showing a gate forming step of a semiconductor device according to one embodiment of the present invention.

【図2】 従来の半導体装置のゲート形成工程を示す断
面図である。
FIG. 2 is a cross-sectional view illustrating a gate forming step of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 基板 7 分離酸化膜 8 Nウエル領域 9 多結晶シリコン膜 10 ゲート酸化膜 11 レジスト 12 液体酸化膜 13 窒化膜 DESCRIPTION OF SYMBOLS 1 Substrate 7 Separation oxide film 8 N well region 9 Polycrystalline silicon film 10 Gate oxide film 11 Resist 12 Liquid oxide film 13 Nitride film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上にパターン被形成膜を形成
する工程と、前記パターン被形成膜上に酸化膜を形成す
る工程と、前記酸化膜上に窒化膜を形成する工程と、前
記窒化膜上にレジストを形成する工程と、前記レジスト
にレジストパターンを形成する工程と、前記窒化膜、前
記酸化膜、前記パターン被形成膜をエッチングして、第
1および第2のパターン被形成膜のパターンを形成する
工程とを有する半導体装置の製造方法において、前記半
導体基板の裏面から第1のパターン被形成膜の表面まで
の高さと前記半導体基板の裏面から第2のパターン被形
成膜の表面までの高さが異なることを特徴とする半導体
装置の製造方法。
A step of forming a pattern formation film on a semiconductor substrate; a step of forming an oxide film on the pattern formation film; a step of forming a nitride film on the oxide film; Forming a resist thereon, forming a resist pattern on the resist, etching the nitride film, the oxide film, and the pattern formation film to form a pattern of first and second pattern formation films. Forming a height from the back surface of the semiconductor substrate to the surface of the first pattern formation film and the height from the back surface of the semiconductor substrate to the surface of the second pattern formation film. A method for manufacturing a semiconductor device, wherein the heights are different.
【請求項2】半導体基板上に活性領域と分離領域を形成
する工程と、前記活性領域上および前記分離領域上にパ
ターン被形成膜を形成する工程と、前記パターン被形成
膜上に酸化膜を形成する工程と、前記酸化膜上に窒化膜
を形成する工程と、前記窒化膜上にレジストを形成する
工程と、前記レジストにレジストパターンを形成する工
程と、前記窒化膜、前記酸化膜、前記パターン被形成膜
をエッチングして、パターン被形成膜のパターンを形成
する工程とを有する半導体装置の製造方法において、前
記パターン被形成膜は前記活性領域と前記分離領域によ
り段差を有することを特徴とする半導体装置の製造方
法。
A step of forming an active region and an isolation region on the semiconductor substrate, a step of forming a pattern formation film on the active region and the separation region, and forming an oxide film on the pattern formation film. Forming, forming a nitride film on the oxide film, forming a resist on the nitride film, forming a resist pattern on the resist, forming the nitride film, the oxide film, Forming a pattern of the pattern formation film by etching the pattern formation film, wherein the pattern formation film has a step due to the active region and the separation region. Semiconductor device manufacturing method.
JP11141082A 1999-05-21 1999-05-21 Manufacture of semiconductor device Pending JPH11354523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11141082A JPH11354523A (en) 1999-05-21 1999-05-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11141082A JPH11354523A (en) 1999-05-21 1999-05-21 Manufacture of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP02337458A Division JP3080400B2 (en) 1990-11-30 1990-11-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH11354523A true JPH11354523A (en) 1999-12-24

Family

ID=15283801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11141082A Pending JPH11354523A (en) 1999-05-21 1999-05-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH11354523A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008166704A (en) * 2006-12-26 2008-07-17 Dongbu Hitek Co Ltd High-voltage c-mos element and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008166704A (en) * 2006-12-26 2008-07-17 Dongbu Hitek Co Ltd High-voltage c-mos element and method of manufacturing the same

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