JPH11353817A - Id number detection protecting method and circuit therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a correction block to be correctly written into a memory by allowing a correct ID number to be always loaded into an ID number interpolation counter even when an ID number has not been detected in addition to occurrence of false detection and false correction of the ID number in a normal operation. SOLUTION: In both a pulling-in operation, in which transition from an ID error condition to an ID detection condition occurs, and a normal operation, following the pulling-in operation, to be performed after the detected ID number has been loaded into an ID number interpolation counter, a correct ID number is always loaded into the ID number interpolation counter even when an ID number has not been detected in addition to occurrence of false detection and false correction of the ID number. Thus, a block switching timing pulse and an address within a block are always correctly generated from its counter value and a correction block is correctly written into a memory. At the time when the correct ID number is detected, it can be determined that this ID number is correct, thereby a pulling-in operation in which the number of sectors to be passed is minimized can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ID number detection and protection method and a circuit thereof, and more particularly to an ID number detection protection method which is added for each recording unit and is necessary for accessing a basic unit (for example, a sector or a frame) recorded on a recording medium. The present invention relates to a method of detecting and protecting an ID number and a circuit thereof.

[0002]

2. Description of the Related Art Conventionally, a CD-ROM is used as an example of a system for detecting an ID number included in a reproduction signal of a recording medium, specifying a target recording unit from the ID number, and reproducing the data contained therein. (Compact Disk−Read Only M
emory). The reproduction of this CD-ROM is described in "CD: From Audio to Personal Computer", edited by Kenji Hayashi and edited by Kenji Hayashi, Corona Publishing Co., Ltd., p. As described in this kind of publication, in order to reproduce a CD-ROM, a plurality of frame data which are recording units on a recording medium are collected to form subcode data, and an ID number included in the subcode is included. According to the detection of (time information), a desired frame on the recording medium is accessed. Further, a plurality of frames constitute a sector which is a signal processing unit of the CD-ROM.
The data transfer control is performed by detecting the D number (in this case, the physical address), specifying the sector to be transferred to the connected device such as the host computer.

[0003]

However, the signal read from the recording medium may not be able to detect the ID number due to scratches on the recording medium, signal deterioration during transmission, etc. There are cases where numbers are detected. If the ID number cannot be detected, access to the recording medium becomes impossible, and the reliability of the data transferred to the connected device itself decreases. Further, when an incorrect ID number is detected, there is a possibility that an erroneous frame is accessed, and there is a problem that sector data different from the original target sector is transferred to the connected device.
When the ID number is erroneously detected or not detected, a protection function for the ID number is required. In particular, when an erroneous detection occurs in the ID number, there is a problem that a large number of elapsed sectors or elapsed frames are required in order to output a highly reliable correct detected ID number again. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and circuit for performing protection of correct ID number detection even when erroneous detection of an ID number has occurred and minimizing the number of elapsed sectors necessary for the detection protection operation.

[0004]

According to the present invention, in order to achieve the above object, a step of generating a first predicted value based on a detected first detection ID number; Generating a second prediction value based on a different second detection ID number, and generating the first and second prediction values and the third detection ID
The method includes a step of determining a match with the number, and a step of employing the third detection ID number as a detection protection output when the match is established. Further, in the present invention, the first
Counter means, second counter means, detection protection output means, a microprocessor for generating a control instruction,
A readable recording medium storing a program section, wherein the microprocessor reads out the program code from the storage medium and operates using an ID number detection and protection circuit to detect and protect the ID number. A first program section for issuing an instruction to load a detection ID number to the first counter means, a second detection ID number detected next, and a first prediction obtained by the first counter means. A second program section for determining a match with a value, and a third program for issuing a load instruction of a second detection ID number to the second counter means when a match is not established in the second program section. Section, the next detected third detection ID number and the first
And a fourth program section for determining whether the first predicted value and the third detection ID number obtained from the counter means match the second predicted value obtained from the second counter means, and a fourth program section. And a fifth program section for generating an instruction to load the third detection ID number into the detection protection output means when a match is established.

[0005] Further, in the match determination in the fourth program section, the third ID number for which the match is established is assigned to the first, first and second ID numbers.
An instruction to load one of the second counter means is generated, and a match between the third predicted value generated based on the third detected ID number and the fourth detected ID number detected next is determined. When a match is not established between the sixth program section and the sixth program section, a fourth detection ID is output to the other counter means to generate a fourth predicted value.
When a match is not established between the seventh program section for generating a number load instruction and the sixth program section, an eighth instruction for generating an interpolation instruction to the detection protection output means.
Program section and the next detected fifth ID
A fifth ID number is loaded into the detection protection output means in accordance with a match in the ninth program section and a ninth program section for determining whether the numbers match the third predicted value and the fourth predicted value. And a tenth program section for generating instructions.

[0006] Still further, there is provided a microprocessor which performs an operation including detection and protection processing of an ID number, and a readable recording medium storing a program section, wherein the microprocessor reads out a program code from the storage medium and operates the ID. Using the number detection protection circuit, ID
In order to detect and protect the numbers, the program section stores a first detection ID number and generates a first predicted value based on the first detection ID number. A second program section for determining a match between the detected ID number of the first program and the first predicted value, and when the match is not established in the second program section, the second detected ID number is stored. A third program section for generating a second predicted value, and a third detected
A fourth program section for performing a match determination between the detection ID number and the first predicted value and the second predicted value, and a third detection ID number when a match is established between the fourth program section and the fourth program section. And a fifth program section for storing as a detection protection output,
Of the first and second predicted values for which a match is established in the match determination in any one of the program sections of the program section, and a detection ID number detected next to the one predicted value. When a match is not established between the sixth program section to be executed and the sixth program section, an ID number detected next to the one predicted value is stored, and a third predicted value is generated based on the ID number. When a match is not established between the seventh program section and the sixth program section, a match is established in one of the second and fourth program sections, and the stored detection ID number is interpolated to detect the detection. An eighth program section to be output as an output, a ninth program section for judging the coincidence between the third predicted value and the detected ID number detected next to the third predicted value. And a tenth program section that stores a detection ID number detected next to the third predicted value when a match is established in the ninth program section, and outputs the detection ID number as a detection protection output. ing.

[0007] In order to solve the above problem, in the present invention, the first detection ID number detected earlier is loaded,
First counter means for generating a first predicted value by an increment operation on the loaded first detection ID number, and loading a second detection ID number different from the first predicted value, and loading the second detection ID Second counter means for generating a second predicted value by an increment operation on the ID number, detection protection output means for performing the loading of the detection ID number and interpolation operation, and the third detection ID number and the first or second A match with the predicted value is determined, and if they do not match, a load instruction is issued to the first and second counter means, and an interpolation instruction is issued to the detection protection output means. Control means for generating a load instruction only for the output means. Further, in the present invention, a digital processing circuit which operates according to the output of the detection protection output means is provided, and a first counter means, a second counter means, a detection protection output means, a digital processing circuit, Are provided on the same semiconductor chip. Still further, in the present invention, a digital processing circuit operating in accordance with the detection protection output, a microprocessor provided in the control means for generating an instruction, and an instruction generated by the control means are transmitted to the microprocessor. A recording medium storing a program section to be generated, wherein the first counter means, the second counter means, the third counter means, the detection protection output means, the microprocessor, The recording medium and the digital processing circuit are provided on the same semiconductor chip.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the ID detection protection method and the ID detection protection circuit according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a first embodiment of an ID number detection protection circuit according to the present invention. In FIG. 1, reference numeral 1 denotes an optical disk on which digital signals are recorded in frame units. The digital signal in frame units is constituted by data-modulating sector-unit data composed of data to be recorded, a sector ID, and an error correction code, and adding a synchronization pattern thereto.

The recording signal of the optical disk 1 is transmitted to the pickup 2
, And is supplied to a data demodulation circuit 4 through a preamplifier 3, and the data demodulation circuit 4 performs a demodulation process on the digital signal after PLL synchronization. Reference numeral 5 denotes a SY0 to SY7 (frame synchronization signal) detection circuit for detecting a synchronization signal indicating the beginning of a frame included in the reproduction signal of the optical disk 1. The output of the SY0 to SY7 detection circuit 5 is an intra-sector address generation circuit. 6. The generation circuit 6 generates a memory transfer address within one sector according to the detected code information of the synchronization signals SY0 to SY7. The SY0 to SY7 detection circuit 5 is a sector ID detection circuit 7.
, Where a sector head synchronization signal SYO recorded at the head of data in sector units is detected. , SYO timing protection circuit 8 outputs a SY0 timing pulse when SY0 is not detected in the outputs of the SY0 to SY7 detection circuits. The second ID number counter 9 and the second first ID number counter 11 are operated by a command from the counter control circuit 10. Further, ID number interpolation counter 1
2 protects the detected ID number by the control command of the counter control circuit 10. The block switching circuit 14 detects, from the output of the ID number interpolation counter 12, the head of a correction block which is composed of a plurality of sectors and is a unit for performing error correction. The block address generation circuit 15 generates a memory transfer address in one correction block from the ID number and the generated address in the sector. Reference numeral 16 denotes a system controller for controlling the entire reproduction system of the optical disk 1. A data transfer control circuit 17 transfers demodulated data to a memory controller 18 according to a transfer enable signal from the system controller 16. The memory controller 18 controls writing and reading of demodulated data to and from the memory 19. The demodulated transfer data is temporarily stored in the memory 19. Reference numeral 20 denotes a detection of a synchronization signal for reproduced data,
A synchronization lock detection circuit that determines the L synchronization state and detects the synchronization lock state of the reproduced data.

Next, an example of the configuration of a sector which is a recording unit of a digital signal recorded on the optical disc 1 will be described with reference to FIG. FIG. 2A is a configuration diagram of sector data,
FIG. 2B is a configuration diagram of a correction block, and FIG. 2C is a configuration diagram of a sector to be recorded. As shown in FIG. 2A, the sector data, which is a unit of data before modulation, has 17 sectors.
2 bytes x 12 data amount as 1 unit, 4 bytes of sector ID added to each sector, 2 bytes of IED code for ID detection and ID error determination for 4 bytes of sector ID, and error correction of 1 byte And the main data 1
To 12, and additional data A and additional data B. The 4-byte sector ID is composed of 1-byte sector information and a 3-byte ID number indicating the physical address of the sector to be recorded on the optical disk 1. Additional data A
Is a reserved bit, and the additional data B is a parity bit.

A correction block, which is a unit for performing error correction on sector data, collects 16 sector data, and
A PI correction code of 10 bytes for correcting the data in the horizontal direction and a PO correction code of 16 bytes for correcting the data in the vertical direction are located as shown in FIG. 2B. Since error correction is performed in units of blocks, the unit of transfer to the memory is one correction block. The sector ID included in the 16 sector data that constitutes the correction block is the ID number lower 4 for the first sector data of the correction block.
Bits are always assigned 0 (hex), and sequentially from 1, 2, 3,..., And the ID number of the last sector data is always assigned F (hex), that is, 15 (dec).
When transferring the corrected block to the memory, for example, it is detected that the lower 4 bits of the ID number are 0, and the data is transferred from that sector. When data having the above-described configuration is recorded on the optical disc 1, PI and PO correction codes are included (1).
An 8/16 modulation process is performed in which a data amount of (72 + 10) bytes × 13 is defined as one unit, and data of one byte (8 bits) in the data amount is modulated into 16 bits. As shown in FIG. 2C, a recording sector, which is a recording unit on the optical disc 1,
Modulated data is composed of 26 frames in which frame synchronization signals SY0 to SY7 are added to each frame data in units of 1456 bits. A special synchronization signal SY0 is added only to the frame corresponding to the head of the sector data, and SY5, SY1, SY5,
. SY2... Are added. Therefore, the modulation data immediately after the frame synchronization signal SY0 corresponds to the sector ID. The addresses in the sector are assigned, for example, addresses 0 (hex) to C (hex), that is, 12 (dec), for two frames in the row direction. Can be generated. The address in the correction block unit can be obtained from the lower 4 bits of the ID number and the address in the sector described above.

Hereinafter, the operation of detecting and protecting the ID number when reproducing the optical disk 1 on which the data having the recording sector configuration described in FIG. 2C is recorded will be described with reference to FIG. In FIG. 1, the reproduced digital signal after passing through the preamplifier 3 is subjected to detection of a frame synchronization signal included in the reproduced signal by an SY0 to SY7 detection circuit 5, and SY (frame synchronization signal) for all of the synchronization signals SY0 to SY7. A timing pulse, each detection code of SY0 to SY7, a SY0 timing pulse for only the synchronization signal SY0, and a SY detection and non-detection timing pulse for which detection and non-detection determination are performed for all of the synchronization signals SY0 to SY7 are generated. The data demodulation circuit 4 synchronizes on a frame basis in accordance with the SY timing pulse among them, and performs demodulation processing on the frame data. The intra-sector address generation circuit 6 generates an intra-sector address corresponding to each reproduction frame from each of the detection codes SY0 to SY7, and outputs the generated address to the block address generation circuit 15. The sector ID detection circuit 7 detects the sector ID number, fetches 4 bytes of the sector ID and 2 bytes of the IED code from the data demodulated by the data demodulation circuit 4 in accordance with the SY0 timing pulse, and detects the data by calculating the IED code. The error of the sector ID is checked. The check result is output as a detection status, that is, a determination signal as to whether the ID has been detected or cannot be detected. Further, in some cases, the sector ID
Is subjected to a one-byte error correction process. The SY0 timing protection circuit 8 performs synchronization on a sector basis according to the SY0 timing pulse, and generates a SY0 timing pulse and a protection timing pulse on the assumption that SY0 has not been detected. The synchronization lock detection circuit 20 generates the SY
The number of times the (frame synchronization signal) is continuously detected or the number of consecutive undetected timings is counted to detect the SY synchronization lock state. For example, when the number of consecutive SY detections is set, if the number is equal to or higher than the lock-in level, it is determined that the data is synchronized with PLL synchronization, and the SY synchronization locked state is detected and output to the counter control circuit 10. When the number of consecutive SY undetections is set, if the lockout level is equal to or higher than the lockout level, it is determined that the data state is out of PLL synchronization, and the SY synchronization lock state is not detected. The system controller 16 monitors the detection status (determination of whether the ID has been detected or cannot be detected) from the sector ID detection circuit 7, and takes in the detected sector ID and sector detection information at that time when the ID is detected. If the difference between the target ID number and the detected ID number for the sector for transferring data to the memory is within one correction block,
A transfer enable signal is generated for the data transfer control circuit 17. The data transfer control circuit 17 starts data transfer from the first sector of the correction block by the transfer enable signal and the block switching timing pulse detected by the block switching detection circuit 14, and transfers the demodulated data to the memory 19 via the memory controller 18. I do. The block switching detection circuit 14 outputs the output I of the ID number interpolation counter 12.
Detects the lower 4 bits of 0 in the D number and generates a block switching timing pulse. The block address generation circuit 15 generates a block address in the correction block according to the value of the lower 4 bits of the ID number and the address in the sector, and outputs the block address to the memory controller 18. The memory controller 18 writes the demodulated data into the memory 19 using the block address.

If the ID number interpolation counter 12 does not always match the correct ID number originally recorded on the optical disk 1, that is, if the ID numbers are not synchronized, the block switching detection circuit 14 that operates accordingly and the block address generation The circuit 15 malfunctions. That is, when an erroneous block switching timing pulse is generated, the transfer of the corrected block to the memory 19 is not performed correctly. Also,
If an erroneous block address is generated, demodulated data will be written to an erroneous position on the memory map. That is, the error correction process performed after the demodulation process cannot be performed, and correct data cannot be transferred to a peripheral device such as a host computer.

In order to synchronize the output of the ID number interpolation counter 12 with the correct ID number recorded on the optical disk, the pickup moves and the pull-in operation immediately after the signal reproduction and the steady operation after the pull-in operation. Will be described separately. FIGS. 3A to 3C are schematic diagrams for explaining a state of pulling in the sector ID. FIGS. 3A to 3C show the pull-in operation from when the pickup moves, the signal reproduction is started, and the detection of the sector ID is started until the detected ID number is loaded into the ID number interpolation counter 12. , The first ID number counter 9, the second ID
An example of each operation of the number counter 11 and the ID number interpolation counter 12 is shown. In the first pull-in operation example of FIG. 3A, it is assumed that the reproduction sectors sequentially change as n, n + 1,... N + 4 (n is a natural number). In this example I
After the D detection status transitions from the ID error to the ID detection state, and the SY synchronization lock state is detected by the synchronization lock detection circuit 20, the ID number detected for the first time is n + 1,
Next, it is assumed that the detected number is erroneously detected as m (m is a natural number) or erroneously corrected. When the SY synchronization lock state is detected and the ID detection status transits from the ID error to the ID detection state, the counter control circuit 10
An instruction to load the detected ID number n + 1 into the first ID number counter 9 is generated, and the first ID number counter 9 outputs n +
Load 1 Thereafter, according to the SY0 detection and protection timing pulse generated by the SY0 timing protection circuit 8,
Increment the counter value based on n + 1, that is, add only one reproduction sector number, and
Predict the number. The counter control circuit 10 determines the next detected ID number m and the value n of the first ID number counter 9.
A determination is made as to whether or not it matches the predicted value of n + 2 after incrementing +1. In this case, since they do not match, an instruction to load the detected ID number m into the second ID number counter 11 is generated, and the second ID number counter 11 loads m.
The second ID number counter 11 also increments the counter value according to the SY0 detection protection timing pulse, and
Is predicted on the basis of the following. The counter control circuit 10 determines the next detected ID number n + 3 and the first I
A match between the predicted value n + 3 and the ID number n + 3 of the D number counter 9 and the predicted value m + 1 of the second ID number counter 11 is determined. In this embodiment, a match between the predicted value of the first ID number counter 9 and the detected ID number is established. Therefore, the counter control circuit 10 issues an instruction to load the detected ID number n + 3 into the ID number interpolation counter 12, and ends the pull-in operation.

In the third example of the pull-in operation shown in FIG. 3B, after the ID detection status transits to the detection state, and the SY synchronization lock state is detected by the synchronization lock detection circuit 20, the ID number n + 1 is changed to the detection state. It is assumed that the detected ID number m has been detected, and then an ID error has occurred, and the detection ID number m at the time of transition to the ID detection is erroneously detected or erroneously corrected. The counter control circuit 10 loads the detected ID number n + 1 into the first ID number counter 9 when the detection status becomes ID detection, and predicts the ID numbers of the next sector and the subsequent sectors based on n + 1. The counter control circuit 10 then determines whether the predicted value n + 3 of the first ID number counter 9 matches the detected ID number m when the detection status becomes ID detection. In this case, since they do not match, the detected ID number m is loaded into the second ID number counter 11 and the I
Predict the D number. The counter control circuit 10 determines whether the detected ID number n + 4 detected next matches the predicted value n + 4 of the first ID number counter 9 and the detected ID number n + 4 matches the predicted value m + 1 of the second ID number counter 11. In this case, a match between the predicted value of the first ID number counter 9 and the detected ID number is established. Therefore, the counter control circuit 10 issues a command to load the detected ID number n + 4 into the ID number interpolation counter 12, and ends the pull-in operation.

FIG. 3C shows that in the third example of the pull-in operation, after the ID detection status transits to the detection state and the SY synchronization lock state is detected by the synchronization lock detection circuit 20, the ID number m is incorrect. Detected or incorrectly corrected, then ID
It is assumed that an ID error occurs after the detection of the number n + 2, and the state transits to the ID detection state again. The counter control circuit 10 loads the ID number m into the first ID number counter 9 when the detection status becomes ID detection, and the counter 9 predicts the ID numbers of the next sector and thereafter based on m.
The counter control circuit 10 determines whether or not the predicted value m + 1 of the first ID counter 9 matches the detected ID number n + 2. In this case, since the values do not match, the second ID number counter 11
Is loaded with the detection ID number n + 2, and the ID numbers of the next sector and thereafter are predicted based on n + 2. After transiting again from the ID error to the ID detection state, the counter control circuit 10 determines the next detected ID number n + 4, the predicted value m + 3 of the first ID number counter 9, the detected ID number n + 4, and the second I
The coincidence of the predicted value n + 4 of the D number counter 11 is determined.
In this case, since the match between the predicted value of the second ID number counter 11 and the detected ID number is established, the counter control circuit 10
Indicates the detected ID number n + 4 as the ID number interpolation counter 12
Is issued, and the pull-in operation ends.

The pull-in operation flow including the operation example described above will be described with reference to the flowchart of FIG. FIG.
5 is a flowchart showing an embodiment of an ID number detection protection method and circuit according to the present invention. Step 301
Then, the pickup 2 accesses the optical disc 1 to start signal reproduction. When the reproduction of the signal is started, as shown in step 302, the SY0 to SY7 detection circuit 5 and the sector ID detection circuit 7 detect the synchronization signal SY0 and the sector ID based thereon. When the synchronizing signal SY0 is detected, in step 303, the SY0 timing pulse is synchronized by the SY0 timing protection circuit 8 based on the detection. To load. When the ID number is loaded into the first ID number counter 9, a sector ID detection process for the next sector is performed as shown in step 304. If it is determined in step 305 that the ID detection status of the next sector is an ID error, then in step 317, the SY synchronization lock detection state is determined. The value of the first ID number counter 9 is incremented by the protection timing pulse, the process returns to step 304, and the sector ID detection process is performed again. If the SY synchronization lock has not been detected in step 317, the process proceeds to step 302 again, and the pull-in operation is performed again. In step 305, the ID detection status is ID
If the detection is determined, the process proceeds to step 307 to synchronize the SY0 detection protection timing pulse with the SY0 timing pulse detected in the sector, and increments the value of the first ID number counter 9. Then, in step 308, it is determined whether or not the incremented counter value matches the detection ID number.
The process then proceeds to step 16, where the detected ID number at that time is loaded into the ID number interpolation counter 12, and the pull-in operation ends.
In step 308, the value of the first counter 9 and the detected ID
If the numbers do not match, the detected ID number at that time is loaded into the second ID number counter 11 in step 309, and a sector ID detection process for the next sector is performed in step 310. If it is determined in step 311 that the ID detection status of the next sector is an ID error, the process proceeds to step 318. Here, the SY synchronization lock detection state is determined. SY0 generated from detection
After the values of the first ID number counter 9 and the second ID number counter 11 are respectively incremented by the protection timing pulse, the process returns to the sector ID detection processing of step 310. If the SY synchronization lock has not been detected in step 318, the process returns to step 302 and the pull-in operation is performed again.

In step 311, the sector status is ID.
If the detection is determined, the process proceeds to step 313 to synchronize the SY0 detection protection timing pulse with the SY0 timing pulse detected in the sector, and the values of the first ID number counter 9 and the second ID number counter 11 are read. Are respectively incremented. Then, in step 314, it is determined whether or not the value of the first counter 9 after the increment matches the detection ID number, and in step 315, it is determined whether the value of the second counter 11 matches the detection ID number. I do. If the detected ID number and the value of the first ID number counter 9 or the value of the second ID number counter 11 match, then in step 316, the detected ID number is loaded into the ID number interpolation counter 12 and pulled in. End the operation. If the detection ID number does not coincide with the value of the first or second counter 9 or 11, the process returns to step 3
02, and the pull-in operation is performed again.

In the following, in the pull-in operation described with reference to FIGS. 3 and 4, the detection ID number is loaded into the ID number interpolation counter 12 when the detection ID number matches the predicted value of the first ID number counter 9. An example of the normal operation in such a case will be described with reference to FIG. FIGS. 5A to 5C are schematic diagrams showing an embodiment of ID number detection protection in a steady state. FIG. 5 (a)
In the first steady-state operation example shown in the above, the ID detection status is always the ID detection state, and the SY synchronization lock is always the detection state, but the ID number detected next to the detection ID number n + 1 is erroneously detected as m, Alternatively, it is assumed that an error is corrected. The first ID number counter 9 is in a state where the detection ID number and the counter value are synchronized by the pull-in operation described above, and the second ID number counter 11 is in a state where the detection ID number does not match. Misdetection or miscorrection ID number m
Is detected, the counter control circuit 10 determines that the value of the first ID number counter 9 does not match the detected ID number,
The second ID number counter 11 generates a load instruction of the detected ID number m, and the ID number interpolation counter 12 generates a counter value increment instruction. The second according to the order
ID number counter 11 loads detection ID number m,
The ID number interpolation counter 12 increments the counter value according to the SY0 timing pulse. The counter control circuit 10 calculates the next detected ID number n + 3, the predicted value n + 3 of the first ID number counter 9, the second ID number counter 1
A determination is made as to whether or not each of them matches the prediction value m + 1 of 1. In this embodiment, the predicted value of the first ID number counter 9 matches the detected ID number again,
An instruction to load the detection ID number n + 3 to the D number interpolation counter 12 is generated. Therefore, the detection ID number and ID
The synchronization of the number interpolation counter value is performed again.

The first steady state operation example shown in FIG.
It is assumed that the Y synchronization lock is always in the detection state, the ID detection status changes to an ID error in the middle, and the detection ID number m that has changed to the ID detection again is erroneously detected or erroneously corrected. When the detection status is determined to be an ID error, the ID number interpolation counter 12 performs an interpolation operation by incrementing the counter value with the SY0 protection timing pulse.
When the detection of the ID number m is performed, the counter control circuit 10 determines that the predicted value of the first ID number counter 9 and the detected ID number do not match from each other, and the second ID number counter 1
1 and a command to load the detection ID number m, and an increment command to the ID number interpolation counter 12 are generated. The counter control circuit 10 calculates the next detected ID number n + 4 and the predicted value n + 4 of the first ID number counter 9,
A match is determined for each predicted value m + 1 of the second ID number counter 11. In this embodiment, since the match between the predicted value of the first ID number counter 9 and the detection ID number is established, the detection number ID n
Generate an instruction to load +4.

The third example of the normal operation shown in FIG.
It is assumed that the Y synchronous lock is always in the detection state, the detection ID number m is erroneously detected or erroneously corrected, and an ID error occurs in the detection status for the next sector. When the detection of the ID number m is performed, the counter control circuit 10 determines that the prediction value of the first ID number counter 9 and the detected ID number do not match from each other, and determines the detection ID number m in the second ID number counter 11. A load instruction is generated, and an increment instruction for the ID number interpolation counter 12 is generated. If the detection status is determined to be an ID error in the next sector, the ID number interpolation counter 12 sets SY0
Increment is performed by the protection timing pulse to perform the interpolation operation. The counter control circuit 10 determines the next detection ID number n +
4 and the predicted value n + 4 of the first ID number counter 9 and the predicted value m + 2 of the second ID number counter 11, respectively. In this embodiment, since the match between the predicted value of the first ID number counter 9 and the detected ID number is established, I
An instruction is issued to the D number interpolation counter 12 to load the detection ID number n + 4.

FIG. 6 is a second flowchart showing an ID number detection and protection operation in a steady state according to the present invention, and FIG. 7 is a first flowchart showing an ID number detection and protection operation in a steady state according to the present invention. FIG. 7 is a flowchart illustrating the steady-state operation when the detected ID number is loaded into the ID number interpolation counter 12 when the detection ID number matches the predicted value of the second ID number counter 11. An operation flow including the operation example in the normal state described with reference to the schematic diagrams of FIGS. 5A to 5C will be described. FIG. 6 shows a steady state operation after the detection ID number and the first ID number counter 9 are determined to coincide with each other and the detected ID number is loaded into the ID number interpolation counter 12 at the time of the start-up operation. After detecting the sector ID in step 501, the process proceeds to step 502, where the ID detection status is I
If it is determined that the error is a D error, S 515 is executed in step 515.
The Y synchronous lock detection state is determined. If the synchronous lock is detected, in step 503, the first ID number counter 9 and the ID number interpolation counter 12 are supplied to the SY0 protection timing pulse generated from the SY0 detection of the previous sector. Increment and return to step 501. Step 5
If the SY synchronization lock is not detected at 15, the process proceeds to the pull-in operation described with reference to FIG. If it is determined in step 502 that the sector status is ID detection, step 504 synchronizes the SY0 detection protection timing pulse with the SY0 timing pulse in that sector, and outputs the first ID number counter 9
Increments the value of. At step 505, it is determined whether or not the value of the first counter 9 after the increment is equal to the detection ID number.
, The detected ID number is assigned to the ID number interpolation counter 1
After reloading to step 2, the process returns to step 501. If the match is not established in step 505, the detected ID number is loaded into the second ID number counter 11 in step 507, and the process proceeds to the sector ID detection processing for the next sector in step 508. If the detection status of the next sector is determined to be an ID error in step 509, the SY synchronization lock detection state is determined in step 516. If the synchronization lock is detected, the SY0 protection generated from the SY0 detection of the previous sector is detected in step 510. The first ID number counter 9, the second ID number counter 11 and I
Each of the D number interpolation counters 12 is incremented,
The process returns to the step 508 for detecting the sector ID. If the SY synchronization lock has not been detected in step 516, the process proceeds to the pull-in operation described with reference to FIG. If it is determined in step 509 that the sector status is ID detection, the flow shifts to step 511 to synchronize the SY0 detection protection timing pulse with the SY0 timing pulse of the sector, and the first ID number counter 9 and the second ID The number counters 11 are each incremented. At step 512, it is determined whether the value of the first counter 9 after the increment matches the ID number, and at step 513, it is determined whether the value of the second counter 11 matches the detected ID number. . If the detected ID number and the value of the first ID number counter 9 match, the process proceeds to step 50.
Move to processing of 6. If the detected ID number and the value of the second ID number counter 11 match, step 51
In step 4, the detected ID number is loaded into the ID number interpolation counter 12, and the process proceeds to the second steady-state operation (FIG. 7) for determining whether the value of the second ID number counter 11 matches the detected ID number. If the detected ID numbers do not match the values of the first and second counters 9 and 11, the process proceeds to the pull-in operation of FIG.

Next, the flowchart of FIG. 7 will be described. FIG. 7 shows a steady operation after the coincidence determination between the detected ID number and the second ID number counter 11 is established at the time of the start-up operation, and the detected ID number is loaded into the ID number interpolation counter 12. After the detection of the sector ID in step 601, if the ID detection status is determined to be an ID error in step 602, the SY synchronization lock detection state is determined in step 615. SY0 generated by SY0 detection
With the protection timing pulse, the second ID number counter 11,
It increments for each of the ID number interpolation counters 12 and returns to step 601. S in step 615
If the Y synchronization lock has not been detected, the process proceeds to the pull-in operation described with reference to FIG. In step 602, the sector status is ID
If the detection is determined, in step 604, the SY0 detection protection timing pulse is synchronized with the SY0 timing pulse in the sector, and the value of the second ID number counter 11 is incremented. At step 605, a match between the value of the second counter 11 after the increment and the detected ID number is determined, and if a match is established, the detected ID number is reloaded into the ID number interpolation counter 12 at step 606. Return to If the match is not established in step 605, the detection I is detected in step 607.
Load the D number into the first ID number counter 9;
In step 608, the process proceeds to a sector ID detection process for the next sector. If it is determined in step 609 that the detection status of the next sector is an ID error, the SY synchronization lock detection state is determined in step 616. Each of the first ID number counter 9, the second ID number counter 11, and the ID number interpolation counter 12 is incremented by the protection timing pulse.
The process returns to the 08 sector ID detection process. S in step 616
If the Y synchronization lock has not been detected, the process proceeds to the pull-in operation described with reference to FIG. In step 609, the sector status is ID
If the detection is determined, the SY of the sector is determined in step 611.
The SY0 detection protection timing pulse is synchronized with the 0 timing pulse, and the first ID number counter 9 and the second I
The D number counter 11 is incremented, and in steps 612 and 613, it is determined whether each of the incremented counter value matches the detected ID number. If a match between the detected ID number and the value of the second ID number counter 11 is established, the process proceeds to step 606. If the detection ID number and the value of the first ID number counter 9 match, the detection ID number is loaded into the ID number interpolation counter 12 in step 614, and the value of the first ID number counter 9 is compared with the value of the first ID number counter 9. The process proceeds to the process of the regular operation 1 (FIG. 6) for performing the match determination using the detection ID number. If the detection ID numbers do not match the values of the counters 1 and 2, the flow proceeds to the pull-in operation of FIG.

As described above, in the first embodiment of the present invention, at the time of the pull-in operation in which the state transitions from the ID error state to the ID detection state, and the detection ID number after the pull-in operation is temporarily set to the ID.
During normal operation after loading into the number interpolation counter 12, erroneous detection and correction of the ID number are included, and the ID number interpolation counter 12 is always loaded with the correct ID number even if ID non-detection is added thereto. Therefore, the block switching timing pulse and the address in the block generated from the counter value are always generated correctly, and the correct block writing to the memory can be performed correctly. Further, in a detection state in which erroneous ID number detection, erroneous correction, or undetected ID is included, the ID number can be determined to be correct at the time of detection of a correct ID number. It is possible to perform a pull-in operation in which the required number of elapsed sectors is minimized. Further, during the steady operation, the ID number interpolation counter 12 can perform the steady operation in which the number of elapsed sectors in which the interpolation operation is performed is minimized. The operation can be performed with high reliability according to the detection ID number.

FIG. 8 is a block diagram showing a second embodiment of the ID number detection and protection circuit according to the present invention. In FIG.
1 in that an ID number counter and a detection ID number match interrupt signal are added to the embodiment of FIG. In FIG. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. First from the detection of the sector ID,
Operation of the second ID number counters 9 and 11, operation of the ID number interpolation counter 12, block switching timing pulse,
The operations of generating addresses in blocks and transferring demodulated data in block units are the same as those in FIG. At the time of the retracting operation or the steady operation, the detection ID number and the first ID number counter 9
Alternatively, when a match with the second ID number counter 11 is determined, the counter control circuit 10 generates an instruction to load the detected ID number into the ID number interpolation counter 12, and generates an ID number counter value and a detected ID number match interrupt. The signal is output to the system controller 16. In response to this interrupt signal, the system controller 16 responds to this interrupt signal by detecting the current detected sector I detected by the sector ID detection circuit 7.
D (sector information, ID number) and the detection status are read, and a transfer enable signal is generated to the data transfer control circuit 17 based on a comparison with the target ID number for the sector to be accessed. The data transfer control circuit 17 transfers the demodulated data in correction block units to the memory 19 via the memory controller 18 according to the transfer enable signal and the block switching timing pulse.

As described above, in the second embodiment of the present invention, the transfer of the demodulated data after the correct ID number is loaded into the ID number interpolation counter 12 and the block switching timing pulse and the address in the block are correctly generated. Since the control is started, the transfer of the corrected block data to the memory 19 can be performed correctly. Further, the system controller 16 generates a transfer enable signal only by comparing the detected sector ID and the target sector ID in accordance with the interrupt signal, and enables the transfer of the demodulated data. , The processing load is reduced. That is, the processing occupancy of the system controller 16 can be reduced. Further, the amount of software description for controlling the system controller 16 is reduced, and the capacity of a storage unit such as a ROM for storing the software can be reduced.

FIG. 9 is a block diagram showing a third embodiment of the ID number detection and protection circuit according to the present invention.
Reference numeral 21 denotes a third ID number counter. The same reference numerals as in FIGS. 1 and 8 denote the same parts, and a description thereof will be omitted. In FIG. 9, as in the case of FIG. 1, the loading of the detection ID number to the ID number interpolation counter 12 and the interpolation operation will be described separately for the pull-in operation and the normal operation after the pull-in. FIGS. 10A to 10C are schematic diagrams showing another embodiment of ID number detection protection during a pull-in operation. FIG. 10 shows an example of each operation of the first ID number counter 9, the second ID number counter 11, the third ID number counter 21, and the ID number interpolation counter 12 in the pull-in operation. The first pull-in operation example shown in FIG.
The detection status changes from the ID error to the ID detection state, and the ID number detected for the first time after the SY synchronization lock state is detected by the synchronization lock detection circuit 20 is n + 1, and the next detected ID number is m, k (k (Natural numbers) are assumed to be continuously detected or corrected. The counter control circuit 10 determines that the ID detection status is I
When the state transits to the D detection state, an instruction to load the detection ID number n + 1 into the first ID number counter 9 is generated, and the first I
The D number counter 9 loads n + 1. The counter control circuit 10 determines the next detected ID number m and the first ID.
A match is determined from the predicted value n + 2 of the number counter 9. In this example, since they do not match, an instruction to load the detected ID number m into the second ID number counter 11 is generated, and the second ID number
The number counter 11 loads m. The counter control circuit 10 further detects the next detected ID number k and the first I
A match is determined from the predicted value n + 3 of the D number counter 9 and the predicted value m + 1 of the second ID number counter 11, but in this case also, the control instruction loads the detected ID number k to the third ID number counter 21 because they do not match. And the third ID number counter 21 loads k. Counter control circuit 1
0 is the next ID number n + 4, the predicted value n + 4 of the first ID number counter 9, and the predicted value m of the second ID number counter 11
+2, a match is determined from the predicted value k + 1 of the third ID number counter 21. In this case, the first ID number counter 9
And the detection ID number match, the detection I
An instruction to load the D number n + 4 into the ID number interpolation counter 12 is generated, and the pull-in operation ends.

In the second example of the pull-in operation shown in FIG. 10B, when the ID detection status transits to the detection state and the synchronous lock detection circuit 20 detects the SY synchronous lock state, the ID number is set to m. It is assumed that erroneous detection or correction is performed, the next detection ID number is n + 2, and the next detection ID number is erroneously detected or corrected as k. The counter control circuit 10 loads the detection ID number m into the first ID number counter 9 when the detection status becomes ID detection. Next, the predicted value m + 1 of the first ID number counter 9
And the detection ID number n + 2 are determined to be coincident with each other.
Load D number n + 2. Further, at the next detection ID number k, the predicted value m + 2 of the first ID number counter 9 and the second ID
A match between the predicted value n + 3 of the number counter 11 and the detected ID number k is determined. Also in this case, there is no match, so the third ID
The detection ID number k is loaded into the number counter 21. The counter control circuit 10 determines the next detection ID number n + 4 and the first I
The predicted value m + 3 of the D number counter 9, the predicted value n + 4 of the second ID number counter 11, the third ID number counter 21
Of the predicted value k + 1 is determined. In this case, the second I
Since the coincidence between the predicted value of the D number counter 11 and the detected ID number is established, an instruction to load the detected ID number n + 4 into the ID number interpolation counter 12 is generated, and the pull-in operation ends.

In the third example of the pull-in operation shown in FIG. 10C, the ID after the ID detection status transits to the detection state.
It is assumed that erroneous detection or erroneous correction is performed on the numbers m and k, and after detecting the ID number n + 3, an ID error occurs and the state transits to the ID detection state again. Counter control circuit 10
Is the first ID when the detection status becomes ID detection.
The detection ID number m is loaded into the number counter 9. The counter control circuit 10 determines the next detected ID number k and the first I
A match with the predicted value m + 1 of the D number counter 9 is determined.
In this example, there is no match, so the second ID number counter 11
Is loaded with the detection ID number k. Counter control circuit 10
Further determines whether the next detected ID number n + 3, the predicted value m + 2 of the first ID number counter 9 and the predicted value k + 1 of the second ID number counter 11 match. The detection ID number n + is stored in the number counter 21.
Load 3. When the state transitions from the ID error to the ID detection state again and the detection ID number n + 5 is detected, the counter control circuit 10 determines the detection ID number n + 5, the predicted value m + 4 of the first ID number counter 9, and the second ID number counter 1
A value match is determined from the predicted value k + 3 of 1 and the predicted value n + 5 of the third ID number counter 21. In this case, the prediction value of the ID counter 3 matches the detected ID number, so that
An instruction to load the detected ID number n + 5 into the ID number interpolation counter 12 is generated, and the pull-in operation ends.

Next, the normal operation will be described with reference to FIGS. 11 (a) and 11 (b).

FIGS. 11 (a) to 11 (c) are schematic diagrams showing another embodiment of ID number detection protection during normal operation. FIG. 11 shows the detection ID number and the first ID during the pull-in operation.
The first ID number counter 9 and the second ID number counter 1 in the steady state when the detected ID number is loaded into the ID number interpolation counter 12 in accordance with the predicted value of the number counter 9
1, an example of each operation of the third ID number counter 21 and the ID number interpolation counter 12 is shown. In the first normal operation example shown in FIG. 11A, the ID detection status is always ID.
In the detection state and the SY synchronization lock is always in the detection state,
ID numbers detected next to the detection ID number n + 1 are m and k
It is assumed that error detection or error correction is continuously performed. The first ID number counter 9 is in a state where the detection ID number and its counter value are synchronized by the pull-in operation described above, and the second ID number counter 11 and the third I
The D number counter 21 is in a state where it does not match the detection ID number. When the detection of the ID number m is performed, the counter control circuit 10 determines whether or not the prediction value n + 2 of the first ID number counter 9 matches the detected ID number m. 11, the detection ID number m is loaded, an increment instruction is issued to the ID number interpolation counter 12, and the ID number interpolation counter 12
The value of the interpolation counter is incremented according to the timing pulse to perform interpolation. The counter control circuit 10 has the following ID
When the number k is detected, the predicted value n + 3 of the first ID number counter 9 and the predicted value m of the second ID number counter 11
A match between +1 and the detection ID number k is determined. In this example, since there is a mismatch, the detection ID is stored in the third ID number counter 21.
The number k is loaded, and an increment instruction is issued to the ID number interpolation counter 12. When the next ID number n + 4 is detected, the counter control circuit 10 predicts the predicted value n + 4 of the first ID number counter 9, the predicted value m + 2 of the second ID number counter 11, and predicts the predicted value m + 2 of the third ID number counter 21. A determination is made as to whether the value k + 1 matches the detection ID number n + 4. In this case, since the value matches the predicted value of the first ID number counter 9, an instruction to load the detected ID number n + 4 to the ID number interpolation counter 12 again is generated.

In the second normal operation example shown in FIG. 11B, an ID error occurs in the sector status in the middle of the continuous detection of the ID detection status, and an erroneous detection is performed when the operation transits to the ID detection again. Alternatively, it is assumed that ID numbers m and k of erroneous correction are continuously detected. When the detection status is determined to be an ID error, the counter control circuit 10 issues an increment command for the ID number interpolation counter 12. The counter control circuit 10 determines the next erroneous correction or erroneous detection ID number m and the predicted value n + 2 of the first ID number counter 9.
Is determined, but in this case, there is no match.
The detection ID number m is loaded into the ID number counter 11 of
An increment instruction is issued to the ID number interpolation counter 12. The counter control circuit 10 further calculates the next incorrectly corrected or erroneously detected ID number k, the predicted value n + 3 of the first ID number counter 9, and the predicted value m + 1 of the second ID number counter 11.
Is determined, and in this case also, the third I
The detection ID number k is loaded into the D number counter 21 and the ID
An instruction to increment the number interpolation counter 12 is generated. The counter control circuit 10 determines the next detection ID number n
+4 and the predicted value n + 4 of the first ID number counter 9, the second
Of the predicted value m + 2 of the ID number counter 11 and the predicted value k + 1 of the third ID number counter 21 are determined. In this example, since the value matches the predicted value of the first ID number counter 9, an instruction is issued to the ID number interpolation counter 12 to load the detected ID number n + 4 again.

In the third steady state operation example shown in FIG. 11C, erroneous detection or erroneous correction m and k are continuously detected in the detection ID number in the middle of the continuous detection state of the ID detection status. It is assumed that an ID error occurs in the subsequent sector status, and the process transits to ID detection again. The counter control circuit 10 has an erroneous correction or erroneous detection ID number m.
Is determined to match the predicted value n + 2 of the first ID number counter 9. In this case, the detected ID number m is loaded into the second ID number counter 11, and an increment instruction is issued to the ID number interpolation counter 12. Occurs. The counter control circuit 10 further detects the erroneous correction or erroneous detection I
D number k and predicted value n + 3 of first ID number counter 9,
A match with the predicted value m + 1 of the second ID number counter 11 is determined. In this case as well, there is no match, so that the detection ID number k is loaded into the third ID number counter 21 and an instruction to increment the ID number interpolation counter 12 is generated. The counter control circuit 10 further issues an increment command to the ID number interpolation counter 12 when the detection status is determined to be an ID error in the next sector. The counter control circuit 10 sets the next detection ID number n + 4 and the first I
The predicted value n + 4 of the D number counter 9, the predicted value m + 2 of the second ID number counter 11, the third ID number counter 21
Is determined to match the predicted value k + 1. In this case, since the coincidence with the predicted value of the first ID number counter 9 is established,
The detection ID number n + 4 is again supplied to the D number interpolation counter 12.
Generate an instruction to load

As described above, in the third embodiment of the present invention, at the time of the pull-in operation in which the ID error state transits to the ID detection state, and the detection ID number after the pull-in operation is temporarily set to the ID.
In the normal operation after loading into the number interpolation counter 12, the ID number interpolation counter 12 always has the correct ID even if the ID number erroneous detection and erroneous correction are included twice and the ID undetection is added thereto. Since the numbers are loaded, the performance can be further improved as compared with the first and second embodiments. 1 and 8, two ID number counters are provided. In the embodiment of FIG. 9, three ID number counters are provided. However, the number of ID number counters is two. The present invention is not limited to three systems, but may include any number of systems such as four systems and five systems. I
When the number of D number counters is increased, even if the number of erroneous detections and erroneously corrected ID numbers included in a series of detected ID numbers increases,
The D number interpolation counter 12 is always loaded with the correct detection ID number. Further, the function of comparing the detected sector and the detected status in the system controller 16 shown in the embodiment of the present invention with the target ID number and generating the transfer enable signal is constituted by dedicated hardware (circuit). Data transfer control may be performed.

Further, when the digital signal processing circuit of the optical disk including the configuration of the present invention is constituted by a semiconductor chip,
The exchange of signals with the system controller 16 displays a detected sector ID and a detection status via an interface register provided on the semiconductor chip. For example, an ID number counter value and a detected ID number match interrupt signal shown in FIG. To display the interrupt factor or output via a pin of the semiconductor chip. As a result, this interrupt signal becomes clear by referring to the interface register map with the system controller and the description of the pin function described in the user's manual of the semiconductor chip.

The counter control circuit 10 for generating a control command for each of the first to third ID number counters 9, 11, and 21 and the ID number interpolation counter 12 shown in FIGS. Not only the circuit (hardware) shown in the embodiment of FIG.
Program code of the control flow shown in
After storing in a readable storage medium such as M (Read Only Memory), each control instruction may be generated by reading out the program code by a dedicated microprocessor or the system controller 16. Further, in this case, a microprocessor for generating a control instruction, a storage means for storing a program code, a circuit including first to third ID number counters 9, 11, 21 and an ID number interpolation counter 12, an ID number detection protection output May be realized on the same semiconductor chip.

The first to third I shown in FIGS.
The ID number detection protection processing performed by using the D number counters 9, 11, 21 and the ID number interpolation counter 12, and the counter control circuit 10 that generates a control command for each of the counters 9, 11, 21 is an embodiment of the present invention. Not only a circuit (hardware) as shown in the example, but also an ID as shown in a control flow shown in FIGS. 4, 6, and 7, for example.
The number detection protection operation itself is converted into a program code and read out from a readable storage medium such as a ROM storing the program code by a dedicated microprocessor or a system controller according to the embodiment of the present invention, and the ID is read.
The number detection protection operation may be realized. In this case, the microprocessor for realizing the operation, the storage means for storing the program code, and the circuit operating at least in accordance with the detection protection output of the ID number can be realized on the same semiconductor chip.

[0038]

According to the present invention, at the time of reproducing a recording medium, when detecting an ID number included in the recording unit, at the time of a pull-in operation for transitioning from an ID error state to an ID detection state, and at the time of detecting a ID after a pull-in operation During normal operation after the number has been once loaded into the ID number interpolation counter, erroneous detection and correction of the ID number are included, and even when ID detection is not added, the correct ID number is always loaded into the ID number interpolation counter. Therefore, the block switching timing pulse and the address in the block generated from the counter value are always generated correctly, so that the correction block can be correctly written in the memory. Further, in a detection state in which erroneous ID number detection, erroneous correction, or undetected ID is included, the ID number can be determined to be correct at the time of detection of a correct ID number. It is possible to perform a pull-in operation in which the required number of elapsed sectors is minimized. Further, during the steady operation, the ID number interpolation counter 12 can perform the steady operation in which the number of elapsed sectors in which the interpolation operation is performed is minimized. The operation can be performed with high reliability according to the detection ID number.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an ID number detection and protection circuit according to the present invention.

FIG. 2 is a configuration diagram of sector data, a correction block, and a recorded sector.

FIG. 3 is a schematic diagram for explaining a state of pulling in a sector ID.

FIG. 4 is a flowchart showing one embodiment of an ID number detection protection method and a circuit thereof according to the present invention.

FIG. 5 is a schematic diagram showing an embodiment of ID number detection protection in a steady state.

FIG. 6 is a first flowchart showing an ID number detection protection operation in a normal state according to the present invention.

FIG. 7 is a first flowchart showing an ID number detection protection operation in a normal state according to the present invention.

FIG. 8 is a block diagram showing a second embodiment of the ID number detection and protection circuit according to the present invention.

FIG. 9 is a block diagram showing a third embodiment of the ID number detection and protection circuit according to the present invention.

FIG. 10 is a schematic diagram showing another embodiment of detection protection of an ID number during a pull-in operation.

FIG. 11 is a schematic diagram showing another embodiment of detection protection of an ID number during a normal operation.

[Explanation of symbols]

1: optical disk, 2: pickup, 3: preamplifier,
4 data demodulation circuit, 5 SY0 to SY7 detection circuit, 6
... Sector address generation circuit, 7 ... Sector ID detection circuit, 8 ... SY0 timing protection circuit, 9 ... First ID number counter 9, 10 ... Counter control circuit, 11 ... Second ID number counter 11 Second ID Number counter 11, 1
2 ... ID number interpolation counter, 14 ... Block switching detection circuit, 15 ... Block address generation circuit, 16 ... System controller, 17 ... Data transfer control circuit, 18 ... Memory controller, 19 ... Memory, 20 ... Synchronous lock detection circuit, 21 ... third ID number counter.

Claims (24)

[Claims] 1. An ID number that does not have continuity with a series of ID numbers originally to be detected in a start state in which detection of an ID number included in the data recording unit is started by reproduction of a recording medium. Generating a first predicted value based on the first detected ID number in order to detect and protect the ID number with respect to the detection state including Generating a second predicted value based on the detection ID number; determining whether the first and second predicted values match the third detection ID number; Third detection I
Adopting a D number as a detection protection output. 2. In a steady state in which detection of an ID number included in a data recording unit is continuously performed due to reproduction of a recording medium, number continuity is not established with a series of ID numbers to be originally detected. In order to detect and protect the ID number in the detection state including the ID number, the first prediction is performed based on the first detection ID number for which the coincidence determination between the detected ID number and the predicted value of the ID number has been established at least once. Generating a value and a second detection ID different from the first predicted value
Generating a second predicted value based on the ID number; determining whether or not the first and second predicted values match the third detection ID number; Adopting an ID number as a detection protection output. 3. In a steady state in which the detection of an ID number included in a data recording unit is continuously performed by reproducing a recording medium, the continuity of the number with a series of ID numbers to be originally detected is considered. In order to detect and protect the ID number in the detection state including the ID number that is not satisfied, the first detection ID number is determined based on the first detection ID number for which the coincidence determination between the detected ID number and the ID number predicted value has been established at least once. Generating a predicted value of the first detection value, and detecting an interpolated value of the ID number generated based on the first detection ID number when detecting a second detection ID number different from the first predicted value. Adopting as a protection output. 4. A first counter means for loading a first detection ID number and performing an increment operation on the loaded first detection ID number to generate a first predicted value; A second counter means for loading a second detection ID number different from the first prediction value, and generating a second prediction value by an increment operation on the loaded second ID number; A detection protection output unit that performs an interpolation operation on the loaded detection ID number, and determines whether or not a third detection ID number matches the first and second predicted values; A load instruction is issued to one of the first and second counter means, an interpolation instruction is issued to the detection protection output means, and if they match, a load instruction is issued only to the detection protection output means. Control hands If, ID number detecting protection circuit, characterized in that they are composed of. 5. The ID number detection and protection circuit according to claim 4, further comprising a digital processing circuit which operates in accordance with an output of said detection and protection output means, wherein said first counter means and said second counter are provided. Means, the detection protection output means, and the digital processing circuit are provided on the same semiconductor chip. 6. An ID number detection / protection circuit using an ID number detection / protection circuit having first counter means, second counter means, detection protection output means, and control means for generating a control instruction. A first step of generating a load instruction of a first detection ID number from the control means to the first counter means, and a first detection ID number detected next to the first detection ID number. Detection I of 2
A second step of determining a match between the D number and a first predicted value obtained by the first counter means, and if the match is not determined in the match determination, the second detection ID number is set to the second A third step of generating an instruction to load the counter means, and a third detection I detected next to the second detection ID number.
D number and the first number obtained from the first counter means.
And a fourth determining unit that determines whether the third detection ID number matches the second detection value obtained by the second counter unit.
And a fifth step of generating an instruction to load the third detection ID number into the detection protection output means when a match is established in the fourth step. Number detection protection method. 7. The ID number detection and protection method according to claim 6, further comprising the step of determining whether or not the third detection ID number that has been matched in the match determination in the fourth step is the first or second one. A third predicted value is generated based on the third detected ID number in which the match is established, and a match is determined with the next detected fourth detected ID number. A step of generating a fourth predicted ID value by generating a load instruction of a fourth detection ID number to the other counter means when the match is not established in the sixth step; An eighth step of generating an interpolation command for the detection protection output means when a match is not established in step 6, an fifth detection ID number detected next, a third predicted value,
A ninth step of performing a match determination of each of the fourth predicted values;
And a tenth step of generating an instruction to load the detection ID number detected in the step (c) into the detection protection output means. 8. A method for detecting and protecting an ID number using an ID number detection and protection circuit having first counter means, second counter means, and interpolation means, comprising the steps of: Loading into the first counter means, and a second detection I detected next to the first detection ID number.
A second step of determining a match between the D number and a first predicted value obtained by the first counter means; and if the match is not determined in the match determination, the second detection ID number is set to A third step of loading the second detection ID number, and a third detection I detected next to the second detection ID number.
D number and the first number obtained from the first counter means.
And a fourth determining unit that determines whether the third detection ID number matches the second detection value obtained by the second counter unit.
And a fifth step of, when a match is established in the fourth step, loading the third detection ID number for which the match is established into the detection protection output means. Number detection protection method. 9. The ID number detection and protection method according to claim 8, further comprising the step of determining whether or not the third ID number that has been matched in the match determination in the fourth step is one of the first and second ID numbers. A sixth step of loading the data into the counter means, generating a third predicted value based on the third detected ID number in which the coincidence is established, and determining a coincidence with a fourth ID number detected next; And if the match is not established in the sixth step, the fourth detection ID number is loaded into the other counter means and
A seventh step of generating a predicted value of the following; an eighth step of performing interpolation in the detection protection output means when a match is not established in the sixth step; and a fifth detection ID detected next A ninth judgment is made to determine whether each of the numbers matches the third predicted value and the fourth predicted value.
And a tenth step of loading the fifth detection ID number detected in the ninth step into the detection protection output means when a match is established in the ninth step. ID number detection protection method. 10. A microcontroller comprising: a first counter means; a second counter means; a detection protection output means; a microprocessor for generating a control instruction; and a readable recording medium storing a program section. The first program section loads a first detected ID number to detect and protect an ID number using an ID number detection and protection circuit that operates by reading a program code from the storage medium. A first program section for generating an instruction for the first counter means, a second detection ID number detected next, and a coincidence determination between a first predicted value obtained from the first counter means. Second to do
And a third program section for generating a load instruction of the second detection ID number to the second counter means when a match is not established in the second program section. A fourth program for determining whether the third ID number matches the first predicted value obtained from the first counter means, and the third ID number matches the second predicted value obtained from the second counter means. And a fifth program section that issues an instruction to load the third detection ID number into the detection protection output means when a match is established in the fourth program section. ID number detection and protection circuit. 11. The ID number detection protection circuit according to claim 10, further comprising:
An instruction to load the third ID number for which a match has been established into one of the first and second counter means is generated, and a third predicted value generated based on the third ID number is A sixth program section for determining a match with the fourth ID number detected in the second program section; and a counter means for generating a fourth predicted value when a match is not established in the sixth program section. And a seventh program section for generating a load instruction with the fourth detection ID number, and an eighth instruction for generating an interpolation instruction to the detection protection output means when a match is not established in the sixth program section. A program section, a fifth ID number detected next, and the third predicted value,
A ninth program section for determining a match of each of the fourth predicted values; and a tenth instruction for loading the fifth ID number into the detection protection output means according to a match in the ninth program section. And an ID number detection protection circuit. 12. The ID number detection and protection circuit according to claim 10, further comprising a digital processing circuit operable in accordance with a detection and protection output from said microprocessor, said first counter means and said second counter means. ID detection, wherein the detection protection output means, the microprocessor for generating an instruction including the control instruction, and the recording medium storing the program section are provided on the same semiconductor chip. Protection circuit. 13. A computer comprising: a first counter means; a second counter means; an interpolation means; a microprocessor for generating control instructions; and a readable recording medium storing a program section. In order to detect and protect an ID number by using an ID number detection and protection circuit that operates by reading a program code from the storage medium, the program section stores a first detected ID number and uses the first detected ID number as a basis. A first program section for generating a first predicted value, a second program section for performing a match determination between a second detected ID number detected next and the first predicted value, and a second program section. If no match is found for a section,
A third program section for storing the second detection ID number and generating a second prediction value based on the second detection ID number; a third detection ID number detected next; a first prediction value;
A fourth program section for performing a match determination with each of the second predicted values; and if the fourth program section matches, the third detection ID number is stored and output as a detection protection output. A fifth program section; one of the first and second predicted values that have been matched by a match determination in any one of the second and fourth program sections;
A sixth program section for determining a match with a detection ID number detected next to the one predicted value; and a sixth program section that is detected next to the one predicted value when a match is not established in the sixth program section. A seventh program section that stores the ID number obtained and generates a third predicted value based on the ID number; and a second program section and a fourth program section when a match is not established in the sixth program section. An eighth program section for which a match is established in one of them, interpolating the stored detection ID number and outputting it as a detection protection output, a detection ID number detected next to the third predicted value, A ninth program section for determining a match between the third predicted value and a ninth program section in which a match is established in the ninth program section; Detection ID
A tenth program section for storing the number and outputting it as a detection protection output. I characterized by having
D number detection protection circuit. 14. The ID number detection and protection circuit according to claim 13, further comprising a digital processing circuit that operates in accordance with the detection and protection output from said microprocessor, and performing an operation including said ID number detection and protection processing; A recording medium storing a program section including the first to tenth program sections;
An ID number detection protection circuit, wherein the digital processing circuit is provided on the same semiconductor chip. 15. A first detection ID number included in a data recording unit is loaded by reproducing a recording medium, and a first predicted value is generated by an increment operation on the loaded first detection ID number. A first counter unit, a second detection ID number different from the first prediction value is loaded, and a second prediction value is generated by an increment operation on the loaded second detection ID number. Counter means, detection protection output means for loading and interpolating ID numbers, system control means for controlling reproduction of a recording medium, and a third ID number detected next and the first and second predictions A match with the value is determined, and if they do not match, a load command is issued to one of the first and second counter means, and an interpolation command is issued to the detection protection output means. Control means for generating a load instruction to the detection protection output means in the case of a match, and generating an interrupt signal in accordance with the establishment of a match to the system control means. ID number detection protection circuit. 16. The ID number detection protection circuit according to claim 15, further comprising: a digital processing circuit that operates according to the detection protection output from said control means, wherein said first counter means, said second counter means, ID number detection protection, wherein the detection protection output means, the control means, and the digital processing circuit are provided on the same semiconductor chip, and an interrupt signal to the system control means is output outside the semiconductor chip. circuit. 17. An ID number that does not have continuity with a series of ID numbers originally to be detected in a start state in which detection of an ID number included in the data recording unit is started by reproduction of the recording medium. Generating a first predicted value based on the first detected ID number detected first in order to detect and protect the ID number corresponding to the detection state including: Generating a second predicted value based on the second detected ID number; and a third detected ID different from the first and second predicted values.
A match is determined from the third predicted value generated based on the ID number and the fourth detection ID number.
Adopting the detected ID number as a detection protection output; and a method for detecting and protecting an ID number. 18. In a steady state in which detection of an ID number included in a data recording unit is continuously performed by reproduction of a recording medium, number continuity is not established with a series of ID numbers to be originally detected. In order to detect and protect the ID number for the detection state including the ID number, the first predicted value is determined at least once based on the first detected ID number for which the coincidence determination between the detected ID number and the ID number predicted value has been established. Generating; a step of generating a second predicted value based on a second detection ID number different from the first predicted value; a third different from the first and second predicted values; Detection ID
A match is determined from the third predicted value generated based on the ID number and the fourth detection ID number.
Employing the detected ID number as a detection protection output. 19. Loading a first detection ID number detected among detection ID numbers included in a data recording unit by reproduction of a recording medium, and incrementing the loaded first detection ID number by an increment operation. Loading first detection means for generating a predicted value of 1 and a second detection ID number different from the first predicted value;
Second counter means for generating a second predicted value by an increment operation on the loaded second detected ID number; and loading a third detected ID number different from the first and second predicted values. Third counter means for generating a third predicted value by an increment operation on the loaded third detection ID number, detection protection output means for loading and interpolating the detection ID number, and fourth detection. The ID number and the first, the second and the third predicted value are each determined to match, and if they do not match, the first, the second and the third counter means any one of the counters Control means for generating a load instruction, generating an interpolation instruction for the detection protection output means, and generating a load instruction for the detection protection output means if the values match. ID number detection protection circuit according to claim. 20. The ID number detection protection circuit according to claim 19, further comprising a digital processing circuit that operates in accordance with the detection protection output, wherein said first counter means, said second counter means, and said third counter are provided. ID, wherein said means, said detection protection output means, said control means, and said digital processing circuit are provided on the same semiconductor chip.
Number detection protection circuit. 21. An ID number detection and protection circuit according to claim 19, wherein: a digital processing circuit which operates according to said detection and protection output; a microprocessor provided in said control means for generating an instruction; A recording medium storing a program section for causing the microprocessor to generate a generated instruction, wherein the first counter means, the second counter means, the third counter means, and the detection protection output are provided. Means, the microprocessor, the recording medium, and the digital processing circuit are provided on the same semiconductor chip. 22. The ID number detection protection circuit according to claim 19, wherein a digital processing circuit that operates in accordance with the detection protection output and a micro-processor provided in the control means for performing ID number detection protection processing operation. A processor and a recording medium storing a program section necessary for performing the detection and protection processing by the microprocessor, wherein the microprocessor, the recording medium storing the program section, and the digital processing circuit are formed of the same semiconductor. An ID number detection protection circuit provided on a chip. 23. An I-frame included in a data recording unit of a recording medium.
First counter means for loading a first detection ID number detected earlier among the D numbers, and generating a first predicted value by an increment operation for the loaded first detection ID number; Second counter means for loading a second detection ID number different from the first prediction value and generating a second prediction value by an increment operation for the loaded second detection ID number; Third counter means for loading a third detection ID number different from the second predicted value and generating a third predicted value by an increment operation on the loaded third detection ID number; and loading the detected ID number Detection protection output means for performing an interpolation operation; system control means for controlling the reproduction of a recording medium; and performing a match determination between a fourth detection ID number and the first, second, and third predicted values. It said in the case of disagreement the first
1, a load instruction is generated for any one of the second and third counter means, an interpolation instruction is generated for the detection protection output means, and if they match, the system control means is generated. Control means for generating an interrupt signal in response to the establishment of a match. 24. The ID number detection and protection circuit according to claim 23, further comprising a digital processing circuit that operates in accordance with the detection and protection output, wherein the first counter means, the second counter means, The third counter means, the detection protection output means, the control means, and the digital processing circuit are provided on the same semiconductor chip, and an interrupt signal for the system control means is output to the outside of the semiconductor chip. And an ID number detection protection circuit.