JPH113365A - Wiring pattern generating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve wiring pattern generating efficiency by suppressing delaying defect and unwiring at the wiring designing system of a printed substrate. SOLUTION: In order to decide a wiring pattern generating order, the detour ratio of all the nets is calculated to rearrange in the increasing order of the detour ratio (steps 1 to 3). In addition, within the net group of the same detour ratio, a net is sorted in the increasing order of a delay restricting value (step 4). According to a wiring pattern generating order decided in this manner, a wiring pattern is generated (step 5) to suppress delaying defect and unwiring to improve the efficiency of wiring designing processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for processing a wiring design of a printed circuit board, and more particularly to a method for designing a printed circuit board.
The present invention relates to a wiring pattern generation method capable of reducing unwiring.

[0002]

2. Description of the Related Art In recent years, in information processing systems and the like, the performance of terminal equipment has been improved, and accordingly, the demand for wiring restrictions has been increasing for higher density and higher speed of circuits. ing. Among them, the following items can be mentioned as delay constraints.

[0003] Shortest designated wiring: measures against maximum delay failure.

[0004] Detour length designation wiring: measures against minimum delay failure.

[0005] General wiring: other wiring patterns that do not have the above-mentioned delay restrictions.

As a prior art relating to a method of generating a wiring pattern on a printed circuit board, for example, Japanese Patent Application Laid-Open No. H4-2944
A technique described in Japanese Patent Application Publication No. 58-58 is known. In this conventional technique, all the wiring patterns other than the detour length designation pattern are generated, and finally the detour length designation pattern is generated.

[0007]

In the wiring pattern generation in the prior art, the shortest designated wiring and the general wiring without delay restrictions are all terminated, and finally the detour length designated wiring is performed. However, when this conventional technique is applied to a printed circuit board having a high-density and high-speed circuit, a wiring pattern is generated without distinction between the shortest designated wiring and general wiring. Also, in the detour length designation wiring, a wiring pattern is randomly generated regardless of the magnitude of the delay constraint value.

For this reason, when the general wiring is generated first,
Since the general wiring becomes an obstacle to the shortest specified wiring, the delay constraint value of the shortest specified wiring cannot be observed, and a delay failure and unwiring occur. Further, when the detour length designation wiring is generated after the shortest designation wiring and the general wiring are completed, the wiring channel becomes insufficient, and the detour length designation wiring is not wired. Also, if a wiring pattern with a small delay constraint value is generated later,
Since it interferes with other wiring patterns, delay constraint values cannot be maintained, and there are problems such as delay failure and unwiring.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a wiring design system capable of efficiently forming a wiring pattern on a printed circuit board by solving the above-mentioned problems of the prior art, and suppressing a delay defect and a non-wiring. An object of the present invention is to provide a method for generating a substrate wiring pattern.

[0010]

According to the present invention, it is an object of the present invention to rearrange wiring nets in descending order of detour ratio, and further rearrange in a group of nets having the same detour ratio in ascending order of delay constraint value. Then, the wiring pattern generation order is determined in consideration of ranking the nets with delay constraints before the nets without constraints.
Further, this is achieved by generating a wiring pattern according to the net order determined as described above.

That is, the present invention provides a wiring for generating a wiring pattern on a printed circuit board based on a design information file in which net names and connection points are defined, and wiring constraint information in which net names and delay constraints are defined. An object of the present invention is to solve the problem by providing a means for determining a wiring pattern generation order as described above in a design system.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for generating a printed circuit board wiring pattern according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a flowchart for explaining the processing steps of the wiring design system of the present invention.

(1) Input Condition Extraction In the processing step of step 1, the net name and the connection point information, which are information necessary for determining the wiring pattern generation order, are extracted from the design information file. The delay constraint information is extracted from the wiring constraint information.

(2) Determination of wiring pattern generation order In step 2, based on the various information extracted in step 1, the specified wiring length, which is a delay constraint value, with respect to the shortest wiring length, which is the shortest distance from the start point to the end point of the net. Is calculated for all nets as a detour ratio. Further, the detour ratio is output as data together with other net restriction information.

In step 3, based on the output data of step 2, the nets and other information associated with the nets are rearranged together in ascending order of the detour ratio, and nets having the same detour ratio are grouped into the same group. The result is output for each group.

In step 4, nets are rearranged in ascending order of delay constraint value in each group output in step 3. Also,
In the case of a net having no delay constraint, the net is sorted in ascending order of the shortest wiring length, which is the shortest distance between the connection start point and the end point, and is arranged after the net having the delay constraint.

(3) Wiring pattern generation In step 5, according to the wiring pattern generation order determined in step 4 of the above-described processing step, in a group having a small detour ratio and the same detour ratio,
Wiring patterns are generated sequentially from the net having the smaller delay constraint value. After the net having the delay constraint is generated, the wiring pattern of the general wiring is generated, and the processing of the wiring design system ends when all the wiring patterns have been generated.

Next, the configuration of a wiring design system for generating a wiring pattern in the processing steps of FIG. 1 will be described with reference to the block diagram of FIG.

In FIG. 2, (201) is a design information file storing information on the names of the nets and the connection points,
(202) is wiring constraint information in which information of a net name and delay constraint is defined. From these (201, 202), the input condition extraction of the processing step 1 of FIG. 1 is performed. (2
03) executes the wiring pattern generation order determination and the wiring pattern generation in the processing steps 2 to 5 of FIG. 1 (20).
4, 206, 208, 210).

The above (204, 206, 208, 210)
(204) is a system for calculating the detour ratio shown in the processing step 2 of FIG. 1, and outputs data (205) having the detour ratio and other net information. (20
6) is a system that rearranges the nets in ascending order of the detour ratio based on the output data (205) based on the output data (205) and performs grouping when the detour ratios are the same. The data output of (207) in which the nets are sorted in ascending order of the ratio is performed. In (208), as shown in processing step 4 in FIG. 1, nets in a group having the same detour ratio in the detour ratio ordered net sort data (207) rearranged in ascending order of detour ratio are represented by (20).
This is a system in which the delay constraint values extracted from 2) are sorted in ascending order. In the case of a net having no delay constraint, the nets are sorted in ascending order of the shortest wire length, which is the shortest distance between the connection start point and the end point, and the nets having delay constraints are ranked after the nets. ) Is output. As described above, in the system (204 to 208), the wiring pattern generation order is determined. Also, it is an actual wiring pattern generation system (210).
Executes the generation of a wiring pattern according to the output data (209) in which the wiring pattern generation order is defined, as shown in processing step 5 in FIG.

Finally, (211) is a wiring pattern storage file for outputting the processing result of the wiring pattern generation,
(212) is a processing result list in which various information after the processing of the wiring design system is printed.

Next, a method of calculating the detour ratio in the detour ratio calculation system (204) shown in FIG. 3 and shown in FIG. 2 will be described.

FIG. 3 shows a formula for calculating the detour ratio executed in (204). The denominator inputs the shortest wiring length, which is the shortest distance from the connection start point to the end point, extracted from the design information file. The value obtained by subtracting the shortest wire length from the delay constraint value (designated wire length) extracted from the wire constraint information is input to the numerator and is calculated. Then, a value obtained by multiplying the calculated numerical value by 100 is set as the bypass ratio.

Next, a specific example of a processing result when a wiring pattern is generated in the wiring design system of the present invention will be specifically described with reference to FIG.

This example is a case where the processing in the processing steps 1 to 5 of FIG. 1 is performed and a case where the prior art is applied. In this example, the wiring pattern (402) has the shortest designated wiring having a small bypass ratio. , (401, 40)
3) is a general wiring without delay restriction, the wiring pattern (412) is a detour length designation wiring having a lower detour ratio, the wiring patterns (411, 413) are a detour length designation wiring having a larger detour ratio than (412), and , Wiring pattern (42
2) is a detour length designation wiring having the same detour ratio as (412),
The wiring patterns (421, 423) are general wirings without delay restrictions. The broken line indicates the result of the wiring processing according to the related art, and the solid line indicates the result of the processing according to the present invention.

First, in the wiring patterns (401 to 403), the general wiring (401) is a wiring pattern when the conventional technique is applied, and is generated without considering the shortest designated wiring. This blocks the path of the shortest designated wiring (402). Thereby, the shortest designated wiring (40
When an attempt is made to generate a wiring pattern in accordance with the delay constraint of 2), the pattern is short-circuited as indicated by the mark x in the figure, and the post-processing (402) is not wired. When the shortest designated wiring (402) is bypassed,
Violation of delay constraint occurs. However, when the processing is executed in accordance with the wiring pattern generation order according to the present invention, since the general wiring is generated after the shortest specified wiring is completed, the shortest specified wiring (402) is generated first, and the general wiring is (403).
It is generated by bypassing like. As a result, it is possible to prevent the occurrence of delay failure and unwiring.

Next, in the wiring patterns (411 to 413), a detour length designation wiring (411) having a large detour ratio.
Is a case where the prior art is applied, and since the detour ratio is not considered, the detour length designation wiring (4
When generating (12) in the post-processing, the path of (412) is blocked and becomes unwired. However, when the present invention is applied, by processing (412) having a small detour ratio first, the detour length designation wiring having a high detour ratio can be processed (413).
Since it is possible to make a detour as described above, non-wiring can be prevented.

Finally, wiring patterns (421 to 423)
In (2), the general wiring (421) is one to which the conventional technique is applied, and generates a bypass length specifying wiring after generating the wiring pattern of the shortest specifying wiring and the general wiring. In this case, a wiring channel shortage occurs as shown in the figure. Therefore, when a wiring pattern is generated in accordance with the delay constraint of the bypass length designation wiring (422), the pattern is short-circuited as shown by a mark X in the figure and the wiring is not wired. I will. However, by applying the present invention, by processing the detour-length-designated wiring (422) having the delay constraint first, the general wiring (423) is detoured and the detour-length-designated wiring (422) is bypassed. Can be prevented.

Although the present invention has been described in detail with reference to the embodiment, the present invention is not limited to the above-described embodiment, and can be variously modified without departing from the gist thereof.

[0031]

As described above, according to the present invention, when generating a wiring pattern on a printed circuit board, a wiring pattern is generated from a net having a low detour ratio and a low delay constraint value. Generate an unconstrained net last. As a result, it is possible to reduce the possibility that the wiring pattern having the delay constraint is obstructed by other wiring patterns, and to suppress delay defects and unwiring, thereby improving the efficiency of the wiring design process.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating processing steps of a wiring design system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a wiring design system according to one embodiment of the present invention.

FIG. 3 is an equation for calculating a detour ratio.

FIG. 4 is a diagram illustrating an example of a processing result of wiring pattern generation.

[Explanation of symbols]

201: design information file, 202: wiring constraint information, 2
03: Computer, 211: Wiring pattern input file, 212: Result list after completion of wiring design processing, 40
1-3 wiring patterns, 411-3 wiring patterns, 4
21 to 3... Wiring patterns.

Claims (1)

[Claims] A wiring design for generating a wiring pattern on a printed circuit board based on a design information file in which net names and connection points are defined, and wiring constraint information in which net names and delay constraints are defined. In the system, the shortest distance (shortest wiring length) from the connection start point to the end point obtained from the design information file, and the maximum delay and the minimum delay defined in the wiring constraint information are converted into the wiring length and the delay constraint value (designated wiring) ), The detour ratio is calculated for all nets. Also, nets are rearranged in ascending order of the detour ratio, and nets having the same detour ratio are grouped. Within this group, nets with the smaller delay constraint values are rearranged in order. A wiring design processing method characterized by generating wiring patterns in accordance with the wiring pattern generation order determined as described above.