JPH11161689A - Wiring pattern generating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve wiring pattern generation efficiency by preventing a delay defect and lack of wiring in wiring design, etc., of a printed wiring board. SOLUTION: To determine the generation order of a lead-out wiring pattern from connection points of a component pin, detouring rates of all nets are calculated and rearranged in the increasing order (steps 1 to 3). Further, nets having the same detouring rate are sorted in the increasing order of delay restriction values (step 4). In the wiring pattern generation order which is thus generated, a lead-out wiring pattern from wiring connection points of the component pin is reserved and generated (step 5). Between reserved and generated lead-out wiring patterns, a wiring pattern is generated in consideration of priority (step 6). Consequently, the efficiency of a wiring design processing can be improved by preventing a delay defect and lack of wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for generating a wiring pattern in a method for designing a wiring of a printed wiring board, and more particularly to a method for generating a wiring pattern capable of preventing a delay defect and reducing unwiring.

[0002]

2. Description of the Related Art In recent years, in information processing systems and the like, the performance of terminal equipment has been improved, and the demand for wiring restrictions has been increasing in order to cope with higher density and higher speed of circuits accompanying this. ing. One of the requirements for the wiring constraint is a delay constraint. For this purpose, as a wiring type, a shortest designated wire as a measure against the maximum delay failure, a detour length designated wire as a measure against the minimum delay failure, and a delay constraint as described above. There is general wiring without. Then, in the wiring design processing of the printed wiring board, the wiring is generated by dividing the wiring into the wiring types having the delay constraint as described above.

As a prior art relating to a method of generating a wiring pattern of a printed wiring board, for example, Japanese Patent Application Laid-Open No. 4-2944 is disclosed.
A technique described in Japanese Patent Application Publication No. 58-58 is known. In this conventional technique, all the wiring patterns other than the detour-length-specified wiring pattern are generated, and finally, the detour-length-specified wiring pattern is generated.

[0004]

In the above-described method of generating a wiring pattern according to the prior art, after the generation of the wiring for all of the shortest specified wiring and the general wiring having no delay restriction is completed, the detour length specifying wiring is generated. It is to do. This method according to the prior art, when applied to a printed circuit board having a high-density and high-speed circuit, requires the shortest designated wiring,
When generating a wiring pattern such as a detour length designation wiring, a drawing wiring pattern is generated from a wiring connection point of a component pin without considering a delay restriction, so that the delay restriction value cannot be strictly adhered to and a drawing wiring pattern is generated again. Has to be performed.

In the prior art described above, if a lead line from a wiring connection point of a component pin of the shortest designated wiring or general wiring is generated at random, this wiring pattern may become an obstacle to the detour length designated wiring. In addition, there is a problem that the wiring channel becomes insufficient and the detour length designation wiring becomes unwired. Further, in the above-described conventional technology, when trying to secure the wiring route of the detour length designation wiring after the wiring of the shortest designation wiring or the general wiring, the wiring route of the shortest designated wiring which becomes an obstacle may have to be changed, There is a problem that the length is fluctuated and the delay constraint value cannot be kept, thereby causing a delay defect.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art, and to provide a wiring design system capable of efficiently forming a wiring pattern on a printed circuit board and suppressing unwiring and delay defects. An object of the present invention is to provide a wiring pattern generation method for wiring.

[0007]

According to the present invention, the object is to provide a net name on a printed wiring board, design information defining wiring connection points of component pins of the net, a net name, and a net name. In a wiring pattern generation method in a wiring design system for generating a wiring pattern on a printed wiring board based on wiring restriction information in which delay constraints are defined, a wiring start point and an end point of component pins obtained from the design information And the maximum delay and minimum delay defined in the wiring constraint information,
The detour ratio is calculated for all nets from the delay constraint value converted to the wiring length, and the nets are rearranged in ascending order of the detour ratio, and this order is used as the wiring order to generate a wiring pattern drawn from the wiring connection point of the component pin It is achieved by doing.

Further, the above object is achieved by rearranging nets having the same detour ratio in the rearrangement of nets based on the detour ratio, by rearranging these nets in ascending order of delay constraint value.

The object of the present invention is to provide a method for generating a lead-out wiring pattern in the case where a lead-out wiring pattern generated from a wiring connection point of a component pin generated in accordance with the wiring order becomes an obstacle in generating another lead-out wiring pattern. This is achieved by generating the lead-out wiring pattern while changing the wiring path.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a wiring pattern generating method according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a flowchart for explaining a wiring pattern generating method according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a wiring design system using the wiring pattern generating method according to an embodiment of the present invention. Is a diagram showing a formula for calculating a detour ratio, FIG. 4 is a diagram illustrating an example of lead-out wiring of a net with wiring restrictions, FIG. 5 is a diagram illustrating an example of lead-out wiring of a general wiring net, and FIG. FIG. 9 is a diagram for explaining a change in the route of the lead wiring.
2 to 6, reference numeral 201 denotes a design information file;
2 is a wiring constraint information file, 203 is a computer, 2
04 is a detour ratio calculation system, 206 is a detour ratio order net sort system, 208 is a delay constraint value order net sort system, 210 is a drawing wiring generation system from component pin connection points, 211 is a wiring pattern input file, and 212 is a wiring design Result list after the end of the process of 40
1 is the shortest wiring, 402 is a detour length designation wiring, 501 is a general wiring net lead-out wiring, 502 is an obstructing wiring,
Reference numeral 503 denotes a path change wiring of an obstructing wiring; 601, a lead wiring of a general wiring net;
Is a route change wiring of a general wiring net.

First, the processing operation of a wiring pattern generating method according to an embodiment of the present invention applied to a wiring design system for drawing out component pins from wiring connection points will be described with reference to the flow chart shown in FIG.

(A) Input condition extraction processing (1) Net names and wiring connection point information of component pins, which are information necessary for determining the wiring pattern generation order, are extracted from the design information file. The delay constraint information is extracted from the wiring constraint information (step 1).

(B) Processing for determining the order of drawing wiring patterns from LSI (2) Based on various information extracted in the processing of step 1, the shortest wiring which is the shortest distance between the wiring connection start point and the end point of the component pin The ratio between the length and the designated wiring length, which is the delay constraint value, is calculated for each net as a bypass ratio. Further, the detour ratio is output as data together with other net constraint information (step 2).

(3) Based on the output data obtained in the processing of step 2, the nets and other information associated with the nets are arranged in ascending order of the detour ratio, and nets having the same detour ratio are extracted (step). 3).

(4) The nets having the same detour ratio extracted in the process of step 3 are arranged in ascending order of the delay constraint value, and all nets are rearranged. For general wiring nets without delay constraints, the nets are sorted in ascending order of the shortest wire length, which is the shortest distance between the wiring connection start point and the end point of the component pin, and these are arranged after the nets with delay constraints (step 4). ).

(5) In accordance with the wiring pattern generation order determined in the processing of step 4, from the net having a small detour ratio,
Further, when the detour ratios are the same, the wiring patterns are sequentially generated from the wiring connection points of the component pins, starting from the net having the smaller delay constraint value. After generating a lead wiring pattern of a net having a delay constraint, a lead wiring pattern is generated from a wiring connection point of a component pin of general wiring. Further, a wiring pattern drawn from the wiring connection point of the component pin of the detour wiring is generated (step 5).

(C) Wiring pattern generation execution processing (6) After the generation of the lead wiring patterns from the wiring connection points of all component pins in the processing up to step 5,
The wiring between the end points of the lead wiring pattern is designed for all nets. Here, the wiring patterns between the lead wiring patterns are generated in accordance with the priority net order added earlier, but if the lead wiring pattern from the wiring connection point of the component pin already generated becomes an obstacle, the priority wiring pattern is generated. While replacing the wiring patterns, such as changing the wiring path of the net (general wiring) with a low order, a wiring pattern is generated between the drawn wiring patterns of all the nets (step 6).

Next, the configuration of a wiring design system using the above-described wiring pattern generation method will be described with reference to the block diagram shown in FIG.

The wiring design system shown in FIG. 2 has information on the name of a net and the start and end points (x,
design information file 20 in which the y coordinate position) is stored.
1, a wiring constraint information file 202 in which the names of nets and information on delay constraints of the nets are defined, a computer 203 for executing the processing described with reference to FIG. 1, and a wiring pattern storage file for storing the generated wiring patterns 211. Note that the delay constraint value in the wiring constraint information file 202 is the maximum delay,
The minimum delay is defined as a value converted into a wiring length, and the wiring length a is defined as a maximum value of the wiring distance or a range of the wiring distance.

In the computer 203, a detour ratio calculation system 204, a detour ratio order net sort system 206, and a delay constraint value order net sort system 2
08, an extraction wiring generation system 210 from a component pin connection point is configured. The computer 203 extracts the input conditions in step 1 described with reference to FIG. 1 from the files 201 and 202 described above, and determines the wiring pattern generation order and wiring pattern generation in steps 2 to 5 by each of the internally configured systems. And outputs the processing result to the wiring pattern storage file 211 and, if necessary, as the processing result list 212.

In the above description, the detour ratio calculation system 20
Reference numeral 4 denotes a system for calculating a detour ratio of each net for executing the processing of step 2 described with reference to FIG. 1, and data 2 having a detour ratio of each net and other net information.
05 is output. Detour ratio order net sort system 20
6 is the data 2 output by the detour ratio calculation system 204
5, the nets are rearranged in ascending order of the detour ratio of the nets, and nets having the same detour ratio are sorted in ascending order of the detour ratios. The net sort data 207 is output.

Net system 2 for delay constraint value order
In step 08, the process of step 4 described with reference to FIG. 1 is executed, and nets having the same detour ratio are extracted from the routing constraint information file 202 in the detour ratio ordered net sort data 207 in which nets are rearranged in ascending order. Sorted in ascending delay constraint value order. Then, the delay constraint value order net sort system 208 sorts the nets having no delay constraint in ascending order of the shortest wire length which is the shortest distance between the wiring connection start point and the end point of the component pin, and has a delay constraint. Ordering is performed after the net, and information 209 on the wiring pattern generation order is output.

In addition, the lead-out wiring system 210 for connecting component pins from the wiring connection point is the same as the systems 204 to 2 described above.
Based on the output data 209 in the wiring pattern generation order determined in step 08, the process of step 5 described with reference to FIG. 1 is executed to generate a wiring pattern drawn from the wiring connection point of the component pin.

Although not shown, the computer 2
In 03, a system for executing the processing of step 6 described with reference to FIG. 1 is provided.

The detour ratio calculation system 20 shown in FIG.
The calculation of the detour ratio in 4 can be performed using the detour ratio calculation formula shown in FIG. The detour ratio is a denominator of the detour ratio calculation formula shown in FIG.
01, the shortest wiring length, which is the shortest distance between the wiring connection start point and the end point of the component pin, is input as the numerator, and the shortest wiring is determined from the delay constraint value (designated wiring length) extracted from the wiring constraint information file 202. It is calculated by inputting the value after subtracting the length. Then, a value obtained by multiplying the calculated numerical value by 100 is the bypass ratio. As shown in FIG. 3, the shortest wiring length can be obtained as the sum of the absolute value of the difference between the x-coordinate and the y-coordinate of the wiring connection start point and the end point of the component pin.

Referring now to FIG. 4, a description will be given of an example of the generation of an extraction wiring pattern when the system 210 generates an extraction wiring from a wiring connection point of a component pin for a net having a wiring restriction.

The system 210 refers to the output data 209 in the wiring pattern generation order, and allocates a wiring route toward the connection destination in such a manner that the shortest wiring is preferentially arranged in order from the net 401 having the smaller bypass ratio of the delay constraint. As a result, the reservation generation of the wiring pattern drawn from the wiring connection point is performed. As for the net 402 having a large detour ratio, a wiring route is allocated to an empty area within a range where the delay constraint can be strictly observed, and a drawn wiring pattern is generated. The reservation generation of the lead wiring pattern from these wiring connection points is performed from each wiring connection point to the wiring channel on the board as shown by a solid line in FIG. The generation of the wiring pattern up to the lead-out wiring pattern is not performed at this time. Then, the generation of the wiring pattern of the dotted line portion is executed by the processing of step 6 described with reference to FIG.

In the generation of the above-described lead-out wiring pattern, the order of the lead-out wirings is determined by the value of the delay constraint, and the lead-out wiring from the wiring connection point of the component pin in consideration of the connection destination and its direction can be considered. So
It is possible to ensure the delay constraint and prevent unwiring.

Next, with reference to FIG. 5, a description will be given of an example of generating a lead wiring pattern of a general wiring net.

A wiring path 502 indicated by a dotted line in FIG. 5 is an example of a wiring pattern that connects the upper and lower electronic components of the figure generated by applying the conventional technology by a shortest path. If it is generated first, a part 501 of the wiring path of the general wiring net from the component pin shown in the center of the drawing will be closed. For this reason, when generating the wiring pattern of the general wiring, which is the post-processing, the wiring pattern is short-circuited as shown by the mark x in the figure, and thus the wiring pattern of the general wiring cannot be generated. The part becomes unwired.

According to the embodiment of the present invention, even in such a case, the wiring path 501 of the portion indicated by the solid line of the general wiring net is used.
Can be generated in advance as a drawing wiring pattern, and the wiring pattern 502, which has been an obstacle to the general wiring path in the related art, can be generated by changing to a different wiring pattern path 503. . As a result, it is possible to secure the wiring route of the general wiring net and prevent the occurrence of unwired wiring.

Next, generation of a wiring pattern using wiring route change in consideration of the priority order in the processing of step 6 described with reference to FIG. 1 will be described with reference to FIG.

In the above-described method for generating a lead-out wiring pattern reservation, when a general wiring is previously generated as a lead-out wiring pattern, a lead-out wiring pattern shown as 601 in FIG. 6 may be generated. The wiring route 602 for which the shortest wiring is designated as shown by the middle X mark
There is an example in which the wiring is blocked and unwired.

In order to prevent such non-wiring, the wiring pattern generating method according to the embodiment of the present invention changes the wiring route in consideration of the priority order of the wiring patterns. That is, as shown in FIG. 2, the priority order of the wiring patterns is registered in the delay constraint value order net sort data 209, and in the embodiment of the present invention, the wiring order having the higher priority order is used by using this priority order. The general wiring 601 that draws out from the wiring connection point of the component pin with the lower priority order, which is an obstacle to the pattern 602, can be changed to the drawing wiring path 603.

According to an embodiment of the present invention,
It is possible to strictly adhere to the delay constraint value of the shortest wiring and prevent the occurrence of non-wiring.

[0037]

As described above, according to the present invention, it is possible to generate a wiring pattern without causing a delay defect and reducing unwiring.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a wiring pattern generation method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a wiring design system using a wiring pattern generation method according to an embodiment of the present invention.

FIG. 3 is a diagram showing a mathematical expression for calculating a detour ratio.

FIG. 4 is a diagram illustrating an example of a lead-out wiring of a net having wiring restrictions.

FIG. 5 is a diagram illustrating an example of a lead-out wiring of a general wiring net.

FIG. 6 is a diagram illustrating a change of a route of a lead wiring in consideration of a priority order;

[Explanation of symbols]

201 Design Information File 202 Wiring Constraint Information File 203 Computer 204 Detour Ratio Calculation System 206 Detour Ratio Order Net Sorting System 208 Delay Constraint Order Net Sorting System 210 Wiring Generation System from Component Pin Connection Point 211 Wiring Pattern Input File 212 Wiring Design List after completion of the process 401 Shortest wiring 402 Detour length designation wiring 501 General wiring net lead-out wiring 502 Obstacle wiring 503 Route changing wiring of faulty wiring 601 General wiring net lead-out wiring 602 Shortest wiring 603 General wiring net This is the route change wiring.

Claims (3)

[Claims] 1. A net name on a printed wiring board, design information defining a wiring connection point of a component pin of the net, and wiring constraint information defining a net name and a delay constraint of the net. A wiring pattern generation method for generating a wiring pattern on a printed wiring board based on the minimum length of a wiring connection starting point and an ending point of a component pin obtained from the design information; The maximum delay and the minimum delay are calculated from the delay constraint value converted to the wiring length.
A method of generating a wiring pattern, comprising calculating a detour ratio for all nets, rearranging nets in ascending order of the detour ratio, and using this order as a wiring order to generate a lead wiring pattern from a wiring connection point of a component pin. 2. The net according to claim 1, wherein, in the rearrangement of nets based on the detour ratio, when there are nets having the same detour ratio, these nets are rearranged in order from a net having a smaller delay constraint value. Wiring pattern generation method. 3. When a certain wiring pattern from a wiring connection point of a component pin generated according to the wiring order becomes an obstacle in generating another wiring pattern, the wiring path of the certain wiring pattern is determined. 3. The wiring pattern generation method according to claim 1, wherein the extraction wiring pattern is generated while performing the change.