JPH11330459A - Mos-type transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS-type transistor that can be manufactured readily, is capable of improving the breakdown voltage characteristic, and at the same time increasing the current drive force, and its manufacturing method. SOLUTION: A gate electrode 8 is selectively formed on a first gate insulation film 5, that is formed on the surface of a semiconductor substrate 1 and a second gate insulation film 2 that is thinner than the first gate insulation film 5. The gate electrode 8 is subjected to pattern formation so that the end part of the drain side of the gate electrode 8 is located on the thicker first gate insulation film 5. Then an N-type impurity ion-implanted to the surface of the P-type semiconductor substrate 1. For forming a low-concentration N-type source region 14 and a low-concentration N-type drain region 15, ion implantation conditions are selected so as to penetrate the first gate insulation film 5. However, for forming a high-concentration N-type source region 6 and a high-concentration N-type drain region 7, ion implantation conditions are selected so that is prevented from penetrating the first gate insulation film 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor capable of improving both breakdown voltage and current drivability and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 8 is a sectional view showing a conventional high voltage MOS transistor. FIG. 8 shows the LOD (LOCO
3 shows an N-channel MOS transistor of an S Offset Drain type.

As shown in FIG. 8, an element isolation oxide film 25 is formed on the surface of a P-type semiconductor substrate 21 to define an element region. Element isolation oxide film 2
5, an electric field relaxation region 31 is formed so as to contact element isolation oxide film 25. A high-concentration source region 26 is formed at a position separated from the element isolation oxide film 25 on a surface of one element region partitioned by the element isolation oxide film 25, and a surface of the other element region is A high concentration drain region 27 is formed at a position in contact with the element isolation oxide film 25 and the electric field relaxation region 31. Further, gate insulating films 22 are formed on the surfaces of both element regions.

Further, a gate electrode 28 is formed in a region from the gate insulating film 22 on the high concentration source region 26 to the element isolation oxide film 25. Gate electrode 2
8. On the element isolation oxide film 25 and the gate insulating film 22,
An interlayer insulating film 23 is formed. The gate insulating film 22 and the interlayer insulating film 23 have openings 23 above the high concentration source region 26 and the high concentration drain region 27, respectively.
a and 23b are provided. Furthermore, contact electrodes 29 and 30 burying these openings 23a and 23b are formed. That is, the contact electrode 29 is electrically connected to the high-concentration source region 26, and the contact electrode 30 is electrically connected to the high-concentration drain region 27.

In the N-channel MOS transistor thus configured, the electric field relaxation region 31 achieves a channel stop effect and improves withstand voltage.

Further, a MOS transistor capable of further improving the breakdown voltage and the channel stop performance has been proposed (Japanese Patent Application Laid-Open No. 6-120497). In this MOS transistor, a first electric field relaxation region is formed on a drain region side below an element isolation region, and a second electric field relaxation region is formed on a gate electrode side. Is lower than that of the first electric field relaxation region.

[0007]

However, in the N-channel MOS transistor shown in FIG. 8, when the concentration of the electric field relaxation region 31 is increased, the following problems occur. That is, when the thickness of the gate insulating film 22 is small in a region where the electric field relaxation region 31 and the gate electrode 28 are aligned via the gate insulating film 22, an electric field-induced junction occurs in this region and Will decrease. On the other hand, when the thickness of the gate insulating film 22 is increased, the withstand voltage is improved, but the driving capability of the MOS transistor is reduced.

When the concentration of the electric field relaxation region 31 is low,
The thickness of the gate insulating film 22 can be reduced without lowering the withstand voltage, but in this case, the parasitic resistance of the electric field relaxation region 31 increases, so that the current driving force cannot be increased.

In the MOS transistor proposed in Japanese Patent Application Laid-Open No. Hei 6-120497, the manufacturing method is complicated, and the current driving force cannot be increased.

As described above, conventionally, generally,
MOS that satisfies both the high withstand voltage required for high withstand voltage MOS transistors and the excellent current drive capability
Type transistors cannot be easily obtained.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above-mentioned problems. The present invention provides a MOS transistor which can be easily manufactured, can improve withstand voltage, and can increase current driving force. It is an object of the present invention to provide a manufacturing method thereof.

[0012]

A MOS transistor according to the present invention comprises a semiconductor substrate of a first conductivity type, a source region and a drain region of a second conductivity type selectively formed on the surface of the semiconductor substrate. A second conductive type low-concentration drain region formed at a position near the source region in contact with the drain region and having a lower impurity concentration than the drain region; and between the source region and the low-concentration drain region. A first gate insulating film selectively formed on the channel region and the low-concentration drain region; and a first gate insulating film formed on the semiconductor substrate in contact with the first gate insulating film. A second gate insulating film having a thickness smaller than that of the first gate insulating film; and a gate electrode formed on the first and second gate insulating films. An end on the source region side is located on the first gate insulating film, and an end on the source region side of the low-concentration drain region is located below the first gate insulating film. And

It is preferable that the low concentration drain region is formed around the drain region.

In a method of manufacturing a MOS transistor according to the present invention, a step of selectively forming a first gate insulating film on a surface of a semiconductor substrate of a first conductivity type; Forming a second gate insulating film with a thickness smaller than that of the first gate electrode on the semiconductor substrate; and forming an end on the first insulating film on the first and second gate insulating films. Selectively forming a gate electrode so as to be located; ion-implanting a second conductivity type impurity into the surface of the semiconductor substrate to form a source region on the surface of the semiconductor substrate;
Forming a drain region and a low-concentration drain region having a lower impurity concentration than the drain region at a position near the source region in contact with the drain region; and forming the source region and the drain region. Selecting an implantation energy condition that does not penetrate the first insulating film; and forming the low-concentration drain region includes selecting an implantation energy condition that penetrates the first insulating film using the gate electrode as a mask. Features.

In the present invention, there is no region where the gate electrode and the low-concentration drain region or the drain region are aligned via the second gate insulating film having a smaller thickness than the first gate insulating film. It is possible to prevent a decrease in withstand voltage due to the electric field induced junction. Therefore, in the low-concentration drain region or the region where the drain region and the gate electrode do not match, the thickness of the second gate insulating film below the gate electrode can be further reduced, so that the current driving force is improved. Can be done. Further, in a region where the gate electrode and the low-concentration drain region or the drain region match, the first gate insulating film interposed between the two forms a
High breakdown voltage can be secured.

Further, in the present invention, when the low-concentration drain region is formed around the drain region, the electric field on the drain region side of the channel region can be reduced, and the vertical direction of the drain region (of the substrate) can be reduced. In the thickness direction), the effect of relaxing the electric field can be obtained.

Further, in the method of the present invention, at the time of ion implantation for forming the low-concentration drain region, the implantation energy is selected so as to penetrate the first gate insulating film using the gate electrode as a mask, and the source region and the drain region are formed. During the ion implantation for forming the gate electrode, the implantation energy is selected so as not to penetrate the first gate insulating film, and the low-concentration drain region, the source region, and the drain region are formed in a self-aligned manner. Therefore, it is not necessary to use a special mask, and it is possible to easily manufacture a MOS transistor having the above-described structure having excellent withstand voltage and improved current driving force.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an MO according to an embodiment of the present invention will be described.
The S-type transistor will be specifically described with reference to the accompanying drawings. FIG. 1 shows an MO according to a first embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating an S-type transistor. As shown in FIG. 1, on a surface of a P-type semiconductor substrate 1, a first gate insulating film 5 is selectively formed with a thickness of, for example, 100 to 400 nm, and in other regions, the first gate insulating film 5 is formed. Is formed, a second gate insulating film 2 having a smaller thickness, for example, a thickness of 10 to 30 nm is formed.

The P-type semiconductor substrate 1 in one of the two regions on both sides of the first gate insulating film 5
A low-concentration N-type source region 14 having an impurity concentration of, for example, 1 × 10 ¹⁸ cm ⁻³ is formed on the surface of the low-concentration N-type source region 14. A high-concentration N-type source region 6 of × 10 ²⁰ cm ⁻³ is formed. P-type semiconductor substrate 1 in the other region
A low concentration N-type drain region (low concentration drain region) 15 having an impurity concentration of, for example, 1 × 10 ¹⁸ cm ⁻³ and extending to below the first gate insulating film 5 is formed on the surface of the zero. On the surface of the low-concentration N-type drain region 15, a high-concentration N-type drain region 7 having an impurity concentration of, for example, 1 × 10 ²⁰ cm ⁻³ and in contact with the first gate insulating film 5 is formed.

Further, a gate electrode 8 is pattern-formed in a region from the second gate insulating film 2 on the high-concentration N-type source region 6 to the first gate insulating film 5. Gate electrode 8, first gate insulating film 5, and second gate insulating film 2
An interlayer insulating film 3 is formed thereon. Openings are formed in the second gate insulating film 2 and the interlayer insulating film 3 above the high-concentration N-type source region 6 and the high-concentration N-type drain region 7, respectively. 3a and 3b are provided. Furthermore, contact electrodes 9 and 10 for burying these openings 3a and 3b are formed. That is, the contact electrode 9 is electrically connected to the high-concentration N-type source region 6, and the contact electrode 10 is electrically connected to the high-concentration N-type drain region 7.

Although the low-concentration N-type source region 14 and the high-concentration N-type source region 6 are formed in the present embodiment, the formation of the low-concentration N-type source region 14 is omitted in the present invention. it can.

Hereinafter, the MOS according to the first embodiment of the present invention will be described.
The method for manufacturing the type transistor will be specifically described. 2 to 5 are sectional views showing a method of manufacturing a MOS transistor according to the first embodiment of the present invention in the order of steps.
As shown in FIG. 2, the first gate insulating film 5 is selectively formed on the surface of the P-type semiconductor substrate 1. First gate insulating film 5
Is the same as the conventional selective oxidation method (LOCOS method).
A film such as a nitride film, which is hardly permeable to oxygen, is pattern-formed in all regions except a region where the gate insulating film 5 is to be formed, and is formed by thermally oxidizing the surface of the P-type semiconductor substrate 1. At this time, the film thickness of the first gate insulating film 5 is smaller than that of a normal element isolation film.
To 400 nm. Next, a screen insulating film 4 having a function as a screen film at the time of ion implantation is formed on the surface of the P-type semiconductor substrate 1 by a thermal oxidation method or a chemical vapor deposition method so as to be thinner than the first gate insulating film 5. It is formed with a thickness.

Next, as shown in FIG. 3, boron is ion-implanted into the surface of the P-type semiconductor substrate 1 in order to adjust the threshold voltage of the transistor. At this time, it is preferable to adjust the ion implantation conditions so that the conditions penetrate the screen insulating film 4 and do not penetrate the first gate insulating film 5. The reason will be described below. In the MOS transistor according to the present embodiment, as shown in FIG.
MOS having S structure and second gate insulating film 2 having a small thickness
Structure is formed. When the impurity concentration in the channel region is uniform, M
The OS structure is more effective than the MOS that sandwiches the thin second gate insulating film 2.
The inversion voltage is higher than the structure.

However, if the implantation energy of boron is adjusted to a condition of penetrating only the screen insulating film 4, the first
Since the boron concentration in the semiconductor substrate below the gate insulating film 5 can be maintained at a low concentration, an increase in the inversion voltage can be suppressed, and as a result, the current driving force can be improved. Further, the low-concentration N-type drain region 1
If the impurity concentration in the P-type semiconductor substrate in the channel region adjacent to 5 can be maintained at a low concentration, the electric field can be reduced while maintaining an appropriate threshold voltage, so that the withstand voltage can be improved. Can be done.

Thereafter, as shown in FIG. 4, after the screen insulating film 4 is removed, a film thinner than the first gate insulating film 5 is formed on the surface of the P-type semiconductor substrate 1 by a thermal oxidation method or a chemical vapor deposition method. The second gate insulating film 2 is formed with a thickness. Note that the screen insulating film 4 may be used as it is as the second gate insulating film. After that, a gate electrode 8 is selectively formed on the first gate insulating film 5 and the second gate insulating film 2. At this time, the gate electrode 8 is patterned so that the end on the drain side of the gate electrode 8 is located on the thick first gate insulating film 5.

Thereafter, N-type impurities such as phosphorus, arsenic, and antimony are ion-implanted into the surface of the P-type semiconductor substrate 1 and thermally diffused, thereby forming a low-concentration N-type source region 14 and a low-concentration N-type. The drain region 15 is formed. Low-concentration N-type source region 14 and low-concentration N-type drain region 1
When forming 5, it is preferable to use phosphorus from the viewpoint of mass and diffusion coefficient in consideration of the effect of electric field relaxation. The conditions for ion implantation of the N-type impurity need to be selected so as to penetrate the thick first gate insulating film 5. For example, when using phosphorus as an N-type impurity,
If the film thickness of the first gate insulating film 5 is 100 nm, it is desirable that the implantation energy of phosphorus be 100 keV or more.

Thereafter, N-type impurities such as arsenic are ion-implanted into the surface of the semiconductor substrate 1 under ion-implanting conditions such that the first gate insulating film 5 does not penetrate the thick first gate insulating film 5.
On the surface of the low-concentration N-type source region 14 and the low-concentration N-type drain region 15 below the second gate insulating film 2, a high-concentration N-type source region 6 and a high-concentration N-type drain region 7 are formed, respectively. The arsenic implantation energy in this case is
For example, 50 to 110 keV.

Thereafter, as shown in FIG. 5, an interlayer insulating film 3 is formed on the entire surface, and a high concentration N-type source region 6 and a high concentration N
Contact holes 3 a and 3 b are selectively provided in the second gate insulating film 2 and the interlayer insulating film 3 in a region matched with the mold drain region 7. Then, contact hole 3a
And 3b are buried with a conductive film to form a source electrode 9 electrically connected to the high-concentration N-type source region 6 and a drain electrode electrically connected to the high-concentration N-type drain region 7. Form 10. However, the process of forming the interlayer insulating film 3, the source electrode 9, and the drain electrode 10 is the same as the process of manufacturing a normal LSI. Thus, the MOS transistor according to the present embodiment is formed.

In this embodiment, since there is no region where the gate electrode 8 and the drain region are aligned with each other via the thin second gate insulating film 2, a reduction in withstand voltage due to electric field induced junction is prevented. can do. Therefore, in a region where the low-concentration N-type drain region 15 and the gate electrode 8 do not match, the thickness of the second gate insulating film 2 below the gate electrode 8 can be further reduced, so that the current driving Strength can be improved. Further, in a region where the gate electrode 8 and the low-concentration N-type drain region 15 are aligned, the thickness of the gate insulating film interposed therebetween can be increased, so that a high breakdown voltage can be ensured. .
Further, in the present embodiment, the drain region of the MOS transistor has a structure in which the low-concentration N-type drain region 15 is formed around the high-concentration N-type drain region 7, so that the channel region of the transistor is formed. The electric field on the drain side can be reduced, and the effect of reducing the electric field in the vertical direction of the drain region (the thickness direction of the substrate) can be obtained.

Further, in the method of the present embodiment, the low-concentration N-type source region 14 and the low-concentration N-type drain region 15
At the time of ion implantation at the time of forming, the implantation energy is adjusted so as to penetrate the first gate insulating film 5, and at the time of ion implantation at the time of forming the high concentration N-type source region 6 and the high concentration N-type drain region 7, The injection energy is adjusted so as not to penetrate the first gate insulating film 5, and the source regions 6, 14 and the drain regions 7, 15 are formed in a self-aligned manner using the gate electrode 8 and the first gate insulating film 5 as a mask. Therefore, it is not necessary to use a special mask, and it is possible to easily manufacture a MOS transistor having excellent withstand voltage and improved current driving force.

In the present invention, the position of the end of the high-concentration N-type drain region 7 on the channel region side and the channel region are adjusted by adjusting the position of the end of the first insulating film 5 on the side opposite to the channel region. The distance between can be adjusted. As the distance between the end of the high-concentration N-type drain region 7 and the channel is increased, the breakdown voltage of the transistor can be increased.
, The current driving force decreases. On the other hand, as the distance between the end of the high-concentration N-type drain region 7 and the channel is reduced, the current driving force can be increased, but the withstand voltage of the transistor decreases. Therefore, depending on the purpose of use of the transistor, the high concentration N
The distance between the end of the mold drain region 7 and the channel may be adjusted.

In the present invention, the order of forming the low-concentration N-type source region 14 and the low-concentration N-type drain region 15 and the high-concentration N-type source region 6 and the high-concentration N-type drain region 7 are as follows. There is no particular limitation. Further, in the present invention, a sidewall insulating film or the like of the gate electrode 8 may be formed. In this case, after forming the sidewall insulating film of the gate electrode 8, the low-concentration N-type source region 14, the low-concentration N-type drain region 15, and the high-concentration N-type source region 6 are formed.
And / or the high-concentration N-type drain region 7 can be formed.

FIG. 6 shows a MOS according to a second embodiment of the present invention.
It is sectional drawing which shows a type transistor. However, the second embodiment shown in FIG. 6 is different from the first embodiment only in the shape of the first gate insulating film and the method of forming the same. Objects are given the same reference numerals, and detailed descriptions thereof are omitted.

As shown in FIG. 6, in the second embodiment, a first gate insulating film 5a is formed on the surface of a P-type semiconductor substrate 1 so as to have a rectangular cross section. The second gate insulating film 2 has a smaller thickness than the first gate insulating film 5a and has a thickness smaller than that of the first gate insulating film 5a, as in the first embodiment.
Is formed on the surface.

Hereinafter, a method for manufacturing a MOS transistor according to the second embodiment will be described. 7A and 7B are cross-sectional views illustrating a method of manufacturing a MOS transistor according to a second embodiment of the present invention in the order of steps. However,
In the second embodiment, the steps after the step of forming the first gate insulating film 5a and the second gate insulating film 2 are the same as those of the first embodiment. Only the step of forming the first gate insulating film 5a and the second gate insulating film 2 is shown.

First, as shown in FIG. 7A, an insulating film 16 having a thickness of, for example, about 100 to 400 nm is formed on the entire surface of the P-type semiconductor substrate 1. Next, the insulating film 16 is patterned or removed by lithography or etching to form a first gate insulating film 5a at a predetermined position on the P-type semiconductor substrate 1. In the case where the insulating film 16 is removed by etching, a dry etching method or a wet etching method can be used.

Next, as shown in FIG. 7B, a screen insulating film 4 having a function as a screen film at the time of ion implantation is formed with a smaller thickness than the first gate insulating film 5a. Thereafter, similarly to the first embodiment, the low-concentration N-type source region 14, the low-concentration N-type drain region 15, the high-concentration N-type source region 6, and the high-concentration N-type drain region 7 are formed, and the interlayer insulation is formed. The film 3 and the source electrode 9 and the drain electrode 10 are formed. Thus, the MOS transistor according to the second embodiment is formed.

Also in the second embodiment, since the MOS transistor has the same structure as that of the first embodiment,
The same effect as in the first embodiment can be obtained.

In the first and second embodiments described above, an N-channel MOS transistor has been described. However, the present invention is not limited to an N-channel MOS transistor. In the first and second embodiments,
By inverting the conductivity type, the present invention provides a P-channel M
The present invention can be applied to an OS-type transistor. In this case, the same effects as those of the first and second embodiments can be obtained. When a P-channel MOS transistor is formed, phosphorus, arsenic, antimony, or the like can be used as an N-type impurity, and boron can be used as a P-type impurity.

[0040]

As described in detail above, according to the present invention,
Since the end on the drain electrode side of the gate electrode is located on the first gate insulating film and the end on the source region side of the low-concentration drain region is located below the first gate insulating film, It is possible to prevent a decrease in withstand voltage due to the electric field induced junction, and to improve the current driving force. Further, according to the method of the present invention, a low concentration drain region,
At the time of ion implantation for forming the source region and the drain region, these are formed in a self-aligned manner by selecting an implantation energy, so that it is not necessary to use a special mask, and it has excellent withstand voltage and current. It is possible to easily manufacture a MOS transistor having the above-described structure with improved driving force.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a MOS transistor according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a step subsequent to FIG. 2;

FIG. 4 is a sectional view showing a step subsequent to FIG. 3;

FIG. 5 is a sectional view showing a step subsequent to that of FIG. 4;

FIG. 6 is a sectional view showing a MOS transistor according to a second embodiment of the present invention.

FIGS. 7A and 7B are cross-sectional views illustrating a method of manufacturing a MOS transistor according to a second embodiment of the present invention in the order of steps.

FIG. 8 is a sectional view showing a conventional high breakdown voltage MOS transistor.

[Explanation of symbols]

 1, 21; semiconductor substrate 2, 5, 5a, 22; gate insulating film 3, 23; interlayer insulating film 4, screen insulating film 6, high-concentration N-type source region 7, high-concentration N-type drain region 8, 28; Electrode 9; source electrode 10; drain electrode 14; low-concentration N-type source region 15; low-concentration N-type drain region 16; insulating film 25; isolation oxide film 26; high-concentration source region 27; Contact electrode 31; electric field relaxation region

Claims (3)

[Claims] A first conductive type semiconductor substrate; a second conductive type source region and a drain region selectively formed on a surface of the semiconductor substrate; A low-concentration drain region of a second conductivity type formed at a position and having a lower impurity concentration than the drain region; a channel region formed between the source region and the low-concentration drain region; A first gate insulating film selectively formed on the concentration drain region; and a first gate insulating film formed on the semiconductor substrate in contact with the first gate insulating film and having a smaller thickness than the first gate insulating film. A second gate insulating film; and a gate electrode formed on the first and second gate insulating films. An end of the gate electrode on the drain region side is located on the first gate insulating film. A MOS transistor, wherein an end of the low-concentration drain region on the source region side is located below the first gate insulating film. 2. The semiconductor device according to claim 1, wherein the low-concentration drain region is formed around the drain region.
2. The MOS transistor according to 1. 3. A step of selectively forming a first gate insulating film on a surface of a semiconductor substrate of a first conductivity type; and a step of contacting the first gate insulating film with the first gate electrode on the semiconductor substrate. Forming a second gate insulating film having a very small thickness, and selectively forming a gate electrode on the first and second gate insulating films so that an end is located on the first insulating film. And ion-implanting a second conductivity type impurity into the surface of the semiconductor substrate to form a source region, a drain region, and the drain at a position near the source region in contact with the drain region on the surface of the semiconductor substrate. Forming a low-concentration drain region having a lower impurity concentration than the region, wherein the step of forming the source region and the drain region selects an implantation energy condition that does not penetrate the first insulating film; The method of manufacturing a MOS transistor, wherein the step of forming the low-concentration drain region selects an implantation energy condition penetrating the first insulating film using the gate electrode as a mask.