JPH11330076A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To anodic oxidation in a wiring, without forming a voltage supply wiring for anode oxidization. SOLUTION: Second wiring layers 103 formed of aluminum are separated at every wiring and are formed. They are electrically shorted by a conductive film 101 formed of tantalum nitride. The anode of the second wiring layer 103 are oxidized by applying voltage to the first conductive film 101, and anode oxide films (alumina films) 105 of the wiring layers 103 are formed on the surface. Anode oxides 104 are etched with the anode oxides 105 as masks, and first wiring layers 106 are formed. Then, wirings 101, in which the wiring layers 103 and 106 are stacked, are completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] The present invention relates to an aluminum material
Gate type transistors with wiring formed by
And a method for manufacturing the same. The present invention
Semiconductor devices are thin film transistors and MOS transistors
Not only elements such as
Display or image having a semiconductor circuit composed of
It also includes electronic devices such as disensors. [0002] 2. Description of the Related Art In recent years, semiconductor devices formed on an insulating substrate have been developed.
Thin film transistor (hereinafter abbreviated as TFT)
Active consisting of pixel matrix circuit and drive circuit
Matrix liquid crystal displays are receiving attention. liquid
Crystal display is a projector of about 0.5 to 2 inches
Or a notepad about 10 to 20 inches
For small and medium-sized display data.
It is used as a display. In recent years, there has been a demand for a large area liquid crystal display.
However, when the area is increased, the pixel
The area of the trics circuit also increases, and the matrix
The source wiring and gate wiring arranged in a matrix
Therefore, the wiring resistance increases. Demand for further miniaturization
In order to increase the wiring resistance,
It becomes apparent. In liquid crystal displays, source wiring and
A TFT is connected to the gate wiring for each pixel,
As the number of pixels increases, an increase in parasitic capacitance also poses a problem. Change
Gate signal delays become apparent as panel sizes increase
Will come. In order to solve this problem, a gate wiring and
Use aluminum-based material with low specific resistance
Have been. Gate made of aluminum-based material
By forming wiring and gate electrodes, gate delay time can be reduced.
It can be lowered and can operate at high speed. [0005] Conventionally, thin film transistors have been offset.
Structure or LDD (Light doped drain) structure
Attempts to reduce the off-current
I have. In Japanese Patent No. 2759415, the present applicant
Discloses a technique for obtaining a thin film transistor having an LDD structure.
I have. In the above-mentioned patent publication, the gate electrode material
Anodizing the gate electrode using luminium
To form an LDD structure in a semiconductor layer in a self-aligned manner.
The law is described. This method will be described with reference to FIG.
I do. On a glass substrate 10, a silicon oxide film or the like
The ground film 11 is formed. The polycrystalline silicon
An active layer 13 made of a silicon film is formed, and on the active layer 13
The gate insulating film 14 is formed. Next, the aluminum film
Formed and patterned using photoresist mask 16
Thus, a gate electrode 15 made of aluminum is formed.
(FIG. 22A) When the gate electrode 15 is used as an anode,
Anodize the pattern with porous aluminum
A na film 17 is formed. In this state, the mask 16
As a result, the surface of the gate electrode 15 is blocked,
The alumina film 17 is formed only on the side surface of the pole 15. (Figure
22 (B)) After removing the photoresist mask 16,
The gate electrode 19 is again anodized to form a non-porous alumina film.
18 are formed. (FIG. 22 (C)) Next, using the alumina films 17 and 18 as a mask,
Then, the gate insulating film 14 'is patterned. (FIG. 22
(D)) Then, the porous alumina film 17 was removed.
Later, by plasma doping method, n-type or p-type conductivity type
Is doped into the active layer 13. Do
Ping is carried out twice. The first time is a gate insulating film
14 'at low acceleration so that it functions as a mask.
Dose is increased. In the second time, the gate insulating film 14 'is not
The acceleration is set to be high so that the pure object passes. On the other hand, dose
Reduce the volume. As a result, the active layer 13 has a channel
Formation region 20, source region 21, drain region 22, low
Concentration impurity regions 23 and 24 are formed in a self-aligned manner.
The low concentration impurity region 24 on the side of the drain region 22
Area. However, in order to perform anodizing treatment,
Is the voltage supply line for anodic oxidation.
All wires must be connected. For example, the above patent publication
Technology applied to active matrix LCD panels
In such cases, an active matrix circuit or driver circuit
The gate electrode and wiring of the thin film transistor that constitutes
Must be connected to supply line. Board to connect
The voltage supply wiring is formed on the substrate. So extra
Space is required. Each gate electrode and wiring is connected by a voltage supply line.
The structure is short-circuited. After anodizing
Etches the voltage supply lines and any unnecessary connections to these supply lines.
And remove each gate wiring and electrode electrically.
To separate. Therefore, the etching process margin
With that in mind, the circuit layout must be designed. Fabrication of transistor using anodic oxidation
To form a voltage supply line,
Requires a high margin, which leads to higher circuit integration and board area.
This is an obstacle to miniaturization. In addition, aluminum wiring
Aluminum wiring is formed on TFT using aluminum material
Process temperature is 300-450 ° C after
Also, a malfunction of the TFT was confirmed. The key to this malfunction
There are various possible causes. In particular, top-gate TFTs
Many of the malfunctions are caused by hillocks and wires generated at the gate electrode.
Protrusions such as scars penetrate the gate insulating film and pass through the channel
Aluminum atoms reach gate formation area or gate insulation
And the gate electrode generated by diffusion into the film
This is due to a short circuit between the channels. [0014] As described above, the wiring
In terms of resistance, using aluminum material for wiring
Although it is desired, the use of aluminum material causes various problems.
Will occur. First, using anodizing technology
Self-aligned thin film transistor with LDD structure
Can be manufactured. However, the anodizing electrode
High integration of circuit because it is necessary to form pressure supply wiring
And the reduction of the substrate area are hindered. Also, diffusion of aluminum atoms and hillocks
Causes a short circuit between the gate wiring and the channel.
As a result, a malfunction of the TFT has occurred. The present invention has solved the above problems at once.
The present invention relates to a semiconductor device having a new wiring structure.
You. In the present invention, the voltage supply wiring for anodic oxidation is not formed.
A technology for anodizing the wiring is provided. [0017] SUMMARY OF THE INVENTION To solve the above-mentioned problems.
In order to achieve this, the semiconductor device of the present invention has a first conductive film.
A second wiring layer made of a second conductive film is stacked on the first wiring layer.
A semiconductor device provided with wiring having a stacked structure.
The wiring is formed by oxidizing the first wiring layer.
Oxidizing the first oxide film and the second wiring layer
And the second oxide film formed,
The lower part of the wiring layer is in contact with only the first wiring layer,
Of the first wiring layer and the first
It is characterized by being in contact with the oxide film. According to the present invention, the wiring has a multilayer structure,
The material forming the second wiring layer is expanded by the first wiring layer.
It is to prevent scattering. Further, the present invention provides
Without forming the voltage supply wiring for extreme oxidation, the first and second
The object is to anodize the wiring layer. That is, the first wiring layer
The first conductive film to be formed is used as a wiring for anodic oxidation.
Therefore, it is possible to anodize the second wiring layer.
Was. [Process leading to the present invention] Hereinafter, FIGS.
The process leading to the present invention will be described with reference to FIG. The present invention
Use the tantalum film as an electrode and
Multiple aluminum patterns patterned
It was confirmed whether or not could be anodized. Figure 19 shows the experimental procedure
It is sectional drawing of the aluminum pattern of every. FIG.
FIG. 20 is a partially enlarged view of the sectional structure of FIG. 19. FIG. 21 shows FIG.
5 is an SEM photograph of the cross-sectional structure of the SEM. << Experimental Procedure >> 1737 manufactured by Cornings Incorporated
Sputtering method on glass substrate (5 inch square) 40
A tantalum (Ta) film 41 having a thickness of 20 nm and a thickness of 400
An aluminum (Al) film 42 having a thickness of nm was laminated. And
Connect the probe of the anodic oxidation device to the aluminum film 42
To anodize the surface of the aluminum film
An anodic oxide film 49 was formed. Also
Rear anodic oxide film (hereinafter referred to as barrier AO film)
Alumina. (FIG. 19A) Anodizing conditions are as follows: 3% tartaric acid is added to the electrolytic solution.
Using an ethylene glycol solution containing
° C, ultimate voltage 10V, voltage application time 15 minutes, supply current 1
The substrate was 0 mA / 1 substrate. This anodic oxidation step
This is for improving the adhesion of the metal 50. This anodizer
In the process, the barrier AO film 49 is formed on the surface of the Al film 42.
For this reason, the mask anodic oxidation step will be referred to as Japanese Patent Application Laid-Open No. Sho. Next, a resist mask 50 is formed.
The O. film 49 and the Al film are etched to form a gate made of an Al film.
Wiring pattern 43 (hereinafter, referred to as gate Al43).
) Were formed. Note that the gate Al43 is provided for each wiring.
In FIG. 19, the gate Al43 is 2
Only one is shown. The etchant of the barrier AO film 49 is phosphorus
Acid: nitric acid: acetic acid: water = 85: 5: 5: 5
550 g of chromic acid solution per 10 liters of
(300 grams of chromic acid, 250 grams of water)
Acid was used. Here, this etchant is mixed with chrome
It is called acid. The etchant of the Al film 42
85: 5: 5: 5 ratio by volume of acid, acetic acid, nitric acid and water
(Hereinafter referred to as aluminum mixed acid)
Is used. (FIG. 19B) Next, with the resist mask 50 left,
A voltage is applied to the Ta film 41 in the anodic oxidation apparatus,
Oxidation was performed. The conditions are 3% oxalic acid aqueous solution in the electrolytic solution.
, The applied voltage 8V, the voltage application time 40 minutes, the supply current
20 mA / substrate was used. Conventional anodic oxidation methods
Under extreme oxidation conditions, the side surface of the aluminum pattern 43 is usually
Porous anodic oxide (porous AO) film 44
Is done. Therefore, this anodic oxidation process is called side anodic oxidation.
It is called a process. (FIG. 19C) Next, after removing the resist mask 50,
A voltage is again applied to the Ta film 41 in the anodizing apparatus,
Anodization was performed. The condition is 3% for electrolyte solution
Electrolytic solution using ethylene glycol solution containing tartaric acid
Liquid temperature 10 ° C, ultimate voltage 80V, voltage application time 30 minutes,
The supply current was 30 mA / substrate. In the conventional method, this
Under extreme oxidation conditions, tartaric acid penetrates the porous AO membrane 44.
As a result, the surface of the gate Al 43 is anodized to form a barrier type.
An anodic oxide (barrier A.O.) film 46 is formed. this child
Therefore, this anodizing step is called a barrier anodizing step.
I will. The barrier AO film 46 is made of nonporous alumina.
You. (FIG. 19D) Next, the wet with the above-mentioned aluminum mixed acid
The porous AO film 44 was removed by etching.
(FIG. 19E) << Experimental Results and Discussion >> The Ta film 41 is made of anodic acid.
To check if it functions as voltage supply wiring for
The sheet resistance of the Ta film 41 was measured for each process. Also,
After each step of FIGS. 19C to 19D, a cross section is obtained by SEM.
The structure was observed. FIG. 21 shows the SEM photograph. Also
FIG. 20 schematically shows the SEM observation photograph of FIG.
1 (A) to (C) correspond to FIGS. 20 (A) to (C).
20 and 21, the same names and the same as those in FIG.
One reference numeral corresponds to the component in FIG. The sheet resistance of the Ta film 41 is in the initial state (mass resistance).
Before anodic oxidation) was 100.1 Ω / □ cm. Side yang
After the end of the extreme oxidation process, it is 205.1 Ω /
After the oxidation process, the sheet resistance should be within the measurement range of the measuring device.
That's all. The maximum measurable value of the device is 5000 kΩ / □
cm, the sheet resistance after the barrier anodizing step is
It can be considered that it is at least 5000 kΩ / □ cm or more. After the end of the side anodic oxidation step, the glass substrate 4
When observing 0 with the naked eye, the transparency of the Ta film 41
It was more than the state. From this and the sheet resistance,
It is assumed that the Ta film 41 was slightly oxidized by oxalic acid.
Measured. From the SEM photograph of FIG.
Since there is almost no change in thickness, the Ta film 41
It can be seen that it has not been oxidized. Further, the Ta film 41
By applying a voltage to the
Anodize Al43 to form porous A.O.
It can also be seen that a lumina) film is formed. Similarly, after the barrier anodic oxidation step is completed,
When the substrate 40 is observed with the naked eye, the exposed Ta
The film 41 was almost transparent. This is a mask anodic acid
Tartaric acid used in the oxidation process also anodizes tantalum
The Ta film 41 in this portion is anodized and
Taloxide film (hereinafter referred to as TaOx film) 45
It is presumed that it has been metamorphosed. According to the SEM observation photograph of FIG.
The Ta film 41 is formed below and outside the porous A.O. film 44.
Is about three times as thick as
Shows that the Ta film 41 is anodized and transformed into a TaOx film 45.
You can see that it is. From this, the sheet resistance value is not
It can be understood that it always grows. For simplicity,
19, the thicknesses of the Ta film 41 and the TaOx film 45 are the same.
The same. However, tantalum oxide is insulated
Since the TaOx film 45 functions as a wiring,
Although it is a problem, it is monitored in the barrier anodic oxidation process
Since no large fluctuation was found in the current value, the Ta film 41
Is converted to the TaOx film 45,
It is considered that pressure has been applied. This is TaOx film 4
5 has a very high sheet resistance but is stoichiometric
Less oxygen content than Ta2 O5 (tantalum pentoxide)
Therefore, it is presumed that it shows some conductivity (semi-insulating).
Measured. The deviation from the stoichiometric ratio is due to the TaOx film 4
Due to the fact that 5 was formed by anodic oxidation
Seems to be. Therefore, a barrier anodic oxidation step is performed to
A barrier AO film 46 is formed to cover the gate Al 43.
The cross-sectional structure was confirmed by SEM to determine whether or not it was possible. (Figure 2
0 (C), see FIG. 21 (C)) The etching process shown in FIG.
Although acid was used, aluminum mixed acid was porous alumina (porous
AO film 44) and aluminum are both etched.
On the other hand, non-porous alumina (barrier A.O.
Not touched. Therefore, in the barrier anodic oxidation process,
If the A.O. film 46 is not sufficiently formed, the gate Al
43 will also be removed. In the SEM observation photograph shown in FIG.
Gate Al43 remains even after etching with aluminum mixed acid
It is confirmed that it exists. Therefore, mask anodizing
The barrier AO film 46 that can withstand aluminum mixed acid is formed
Can be concluded. Under the conditions of this experimental result, barrier A.
The thickness of the O. film 46 is about 100 nm. Also, in this process
Indicates that the barrier AO films 46 and 49 are almost integrated.
ing. According to the above experiment, the entire surface of the glass substrate 40 was
Is selectively formed on the upper portion by the Ta film 41 formed on the substrate.
With the formed gate Al43 short-circuited, Ta
By applying a voltage to the film 141, the gate Al4
3 was found to be anodizable. In particular, use tartaric acid
Using Ta film 41 for voltage supply wiring for anodic oxidation
Also, the gate Al43 formed on the upper part is anodized.
I knew it would work. Also, compare the photographs of FIGS. 21 (B) and 21 (C).
As a result, the A.O. films 44 and 46
In the region and the region without these A.O. films 44 and 46, Ta
It can be seen that the thickness distribution of the Ox film 45 is different. In the barrier anodic oxidation step, the Ta film 41
The exposed part is anodized because tartaric acid touches directly.
It is. Since the porous AO film 44 is porous, tartaric acid
Penetrate. Therefore, even under the porous AO film 44, the Ta film 4
The anodic oxidation of 1 progresses, and at the same time, the side surface of the porous AO film 44
As a result, the anodic oxidation of the gate Al43 also proceeds. However, the difference in the anodic oxidation rate due to tartaric acid
As a result, as shown in FIG.
The interface with the O. film 46 is between the Ta film 41 and the TaOx film 45.
On the side. Therefore, the lower portion of the barrier AO film 46 is a Ta film.
41 and the TaOx film 45, and the gate Al4
The lower part of 3 is in contact only with the Ta film 41. The TaOx film 45 and the barrier AO film 46 are the same.
Since the TaOx film 45 and the burr are formed in the anodic oxidation process,
A The interface with the A.O. film 46 and its vicinity are made of an alloy of Ta and Al.
It is considered to be an oxide of TaOx film 4
5 is formed so as to push up the barrier AO film 46.
Therefore, the adhesion to the barrier AO film 46 is excellent. Also, Bali
A interface end between the A.O. film 46 and the Ta film 41 is a TaOx film 45.
It is in a state of being closed. Gate Al43
The effect of preventing Al diffusion is very high. The thickness of the TaOx film 45 is as follows.
The lower part of the A.O. film 46 shown by the region 61 faces the Ta film 41.
The thickness t1 is gradually reduced. From area 61 to A.
O. Although the film thickness gradually increases toward the outside of the film 46,
In the lower part of the glass A.O.
Is maximized. Then, from the portion 62 to the outside,
Gradually become thinner, and the film thickness t3 in the region 63 becomes almost uniform.
Will be fixed. The barrier AO film 46 of the TaOx film 45
The portion extending from the side to the outside has the porous A.O.
Was formed by anodic oxidation
You. Therefore, the surface layer of the TaOx film 145 in this portion is
Reacts with the glass A.O. film 44 to oxidize the alloy of Ta and Al.
It is considered to be a compound. The thickness of the TaOx film 45 will be summarized.
And below the barrier AO film 46 and below the porous AO film 44
Have different film thickness values. Ta is formed below the barrier AO film 46.
The thickness gradually increases outward from the interface with the film 41.
It's getting worse. In addition, the maximum is below the porous A.O.
A portion 61 having a film thickness t2 and a region 63 having a constant film thickness t3
Exists. A.O. films 44 and 46 are formed on the
There is no region only in the region 63 having a constant film thickness t3.
When Ta is oxidized, its thickness becomes about 2 to 4 times.
Therefore, the thicknesses t2 and t3 are two to four times the thickness of the Ta film 41. The configuration of the present invention can be obtained from the above experimental results.
It is based on the knowledge obtained. The present invention provides a method for forming a first conductive film
Forming a second wiring layer electrically separated for each wiring
Then, the plurality of second wiring layers are formed by the first conductive film.
A voltage is applied to the first conductive film in a state where
Thus, the second wiring layer is anodized. In the above structure, the upper second wiring layer is
Mainly used as a path for electric charge, the film thickness is 200 to 50
It is about 0 nm. A conductive film forming the second wiring layer;
Is aluminum or a material containing aluminum as the main component.
It is preferable to form the wiring, so that the resistance of the wiring can be reduced. Further, a valve metal is used as the first conductive film.
Can be Valve metal is produced as an anode
Barrier-type anodic oxide film allows cathode current to flow
Refers to metals that do not conduct current, ie, exhibit valve action.
(Electrochemical Handbook, 4th edition; edited by The Electrochemical Society, p370, Maru
Zen, 1985). A valve metal film which is
High melting point materials include tantalum (Ta), niobium (Nb),
Hafnium (Hf), zirconium (Zr), titanium
(Ti), chromium (Cr) and the like. Also the first
Alloys containing these valve metal elements as conductive films,
For example, using molybdenum tantalum (MoTa)
it can. Particularly, tantalum contains aluminum as a main component.
Anodic oxidation with the same electrolytic solution as the thin film
It is suitable for the present invention. Also, molybdenum tantalum
Containing tantalum alloys such as metal (MoTa) and nitrogen
Tantalum nitride tantalum (Ta_yN (y> 1))
It is also possible to use. In addition, these conductive materials
A material with a higher melting point than Luminium
A blocking action for preventing diffusion of elements is exerted. It is preferable that the thickness of the first conductive film is smaller.
Blocks the diffusion of the constituent atoms of the second wiring layer
It is necessary to have a film thickness for functioning as a rolling layer. First
The thickness of the conductive film is 1 nm or more, preferably 5 nm or more.
You. The upper limit of the thickness of the first conductive film is as follows.
It is considered to be 50 nm, preferably about 30 nm. This is the first
The oxide is formed by oxidizing the first conductive film, and has a thickness of
It is about 2 to 4 times that of the first conductive film. Therefore, the first guide
Sloops for forming an electro-deposited film and etching the first oxide
Considering the cost, the upper limit of the first conductive film is 50 nm,
Preferably, it is 30 nm. Note that aluminum is used for the second conductive film.
A tantalum film is used as a first conductive film therebelow.
When using a tantalum film, the thickness of the tantalum film is reduced to 20 nm and 50 nm.
If the wiring is heat-treated at 550 ° C
It was confirmed that aluminum had not diffused into the lower layer of the film.
ing. As described above, the thickness of the first conductive film is 1 to 50 nm.
(Preferably 5 to 30 nm, more preferably 5 to 20 nm
 It is considered preferable to select from the range of (1). [0052] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
An embodiment will be described. [Embodiment 1] FIG. 1 shows a wiring of this embodiment.
It is sectional drawing which shows the manufacturing process of. On the surface of insulator 100
Next, a first conductive film 101 made of a valve metal is formed.
Next, in contact with the first conductive film 101, aluminum is
A second conductive film 102 which is a main component is formed. (Figure 1
(A)) As the insulator 100, a glass substrate or quartz
Insulating substrates such as substrates, oxidation formed on these substrates
Underlayer such as silicon film, or gate insulation of semiconductor device
And a film and an interlayer insulating film. Also, the second conductive film
As 102, not only pure aluminum but also Si, S
c or the like with several weight% added, or
Luminium alloy may be used. Next, the second conductive film 102 is patterned.
To select the second wiring layer 103 on the first conductive film 101
It is formed. The second wiring layer 103 includes a plurality of wirings (in FIG.
Only two are shown) and all the second
The wiring layer 103 is electrically shielded by the first conductive film 101.
Have been shot. (FIG. 1 (B)) Next, Ethylene glyco containing 3% tartaric acid
Applying a voltage to the first conductive film 101 in a cooling solution
Thereby anodizing the second wiring layer 103,
On the surface, the anodic oxide film of the wiring layer 103 (barrier type alumina)
(Film) 105 is formed. Tartrate with tartaric acid like tantalum film
When the first conductive film 101 is formed of a material that is extremely oxidized
The exposed portion of the conductive film 101 is an anodic oxide 1
Transformed to 04. The anodic oxide film 104 is larger than the conductive film.
Although it is thicker, it is illustrated with the same film thickness for simplicity.
(Fig. 1 (C)) Next, using the anodic oxide film 105 as a mask,
Etching the anodic oxide 104 to form a first wiring layer
106 is formed, and the wiring 110 is completed. (Figure 1
(D)) Note that the first wiring layer 106 is anodized.
Of the first conductive film 101 remaining without being removed.
First, in the anodic oxidation step of FIG.
Can be regarded as being defined. As shown in FIG. 21, the second conductive film 10
No. 2 had a higher anodic oxidation rate than the first conductive film 101.
The interface between the second wiring layer 103 and the anodic oxide film 105
From the interface between the first wiring layer 106 and the anodic oxide 104
Is also inside. Therefore, the lower part of the anodic oxide 103 is the first
In contact with both the wiring layer 106 and the anodic oxide 104,
The lower part of the second wiring layer should be in contact only with the first wiring layer
Becomes In addition, the thickness of the oxide 104 gradually increases outward.
It is thicker. In the present embodiment, the first conductive film
Since the entire wiring layer 102 was short-circuited, it was used for anodic oxidation.
No voltage supply line is required. Therefore, after the anodizing step,
The second wiring layer 103 is separated from the voltage supply line by etching.
A step of dividing the wire for each wiring is not required. Therefore, wiring
As shown in FIG. 2C, the side surface of the end 111 of
Since the anodic oxide films 105 and 104 exist in the
The heat resistance of 110 is not impaired. The end indicated by 111
Other than the above, the side surface of the wiring 110 is the same as the end portion 111
It is. On the other hand, as shown in FIG.
Aluminum coated with lumina (anodic oxide) layer 55
Wiring 50 must be connected to voltage supply wiring 51 for anodic oxidation.
It is necessary. Therefore, after the anodizing step, the wiring 50 is
It was necessary to cut off from 51. Side structure of the divided part 53
The structure is such that the aluminum layer 54 is exposed as shown in FIG.
Is done. In this regard, the present invention is distinguished from the conventional anodizing process.
it can. When the aluminum layer 54 is exposed,
The heat resistance of the wire 50 will be reduced. [Embodiment 2] FIG. 3 shows a wiring according to the present embodiment.
It is sectional drawing which shows the manufacturing process of. In the present embodiment, the first
So that the oxide of the metal extends outside the side surface of the second oxide
On the insulating film divided into islands for each wiring
It is formed. Other configurations are the same as in the first embodiment.
You. First, on a glass substrate 140, silicon oxide or
An insulating film 148 such as silicon nitride is formed. On insulating film 148
Next, a Ta film 141 is formed as a first conductive film. next,
A second conductive film is formed on and in contact with the first conductive film 141.
A film 142 is formed. Ethylene grease containing 3% tartaric acid
A voltage is applied to the first conductive film 141 in the coal solution.
Anodic oxidation of the Al film 142,
A barrier type anodic oxide (barrier A.O.) film 149 is formed.
You. (FIG. 3 (A)) The anode conditions are as follows.
Electrolyte solution using ethylene glycol solution containing tartaric acid
Temperature 30 ° C, ultimate voltage 10V, voltage application time 15 minutes,
The supply current was 10 mA / substrate. This anodization process is
This is for improving the adhesion of the strike mask 150. Next, a resist mask 150 is formed,
The A.O. film 149 and the Al film 142 are etched and
And a plurality of second wiring layers 143 made of an Al film separated into
Formed. In FIG. 3, only two wiring layers 143 are shown.
did. (FIG. 3 (B)) Next, leave the resist mask 150
A voltage is applied to the Ta film 141 in the anodizing apparatus.
Then, anodization was performed. The conditions are as follows:
Acid aqueous solution, ultimate voltage 8V, voltage application time 40 minutes, power supply
The current was 20 mA / 1 substrate. In the conventional anodic oxidation method,
Under the anodic oxidation conditions, the side of the aluminum pattern 43 is usually
A porous anodic oxide (porous AO) film 144 on the surface
Is formed. (FIG. 3 (C)) Next, the resist mask 150 was removed.
Thereafter, a voltage is applied to the Ta film 141 again in the anodizing apparatus.
Anodic oxidation was performed. Porous AO membrane 144 tartar
Acid penetrates and the surface of the second wiring layer 143 is anodized.
Thus, the barrier type anodic oxide (barrier A.O.) film 146 is formed.
The Ta film 141 is also selectively anodized,
A tantalum oxide (TaOx) film 145 is formed.
You. The barrier A.O. is non-porous alumina, and the barrier A.O.
The membranes 149 and 146 are integrated. It is also anodized
The remaining Ta film 141 serves as the first wiring layer 147
Define. (FIG. 3 (D)) Next, the AO films 144 and 146 are used as masks.
Etching to form an insulating film 148 and a TaOx film 145.
Was self-aligned and patterned into islands. Finally, Po
The lath AO film 144 is removed by etching to complete the wiring
I do. Therefore, the wiring was separated into islands for each wiring.
It is formed on the insulating film 148. (FIG. 3 (E)) FIG. 4 is a sectional view of the wiring of this embodiment.
3 and 4 indicate the same components. In addition,
For simplicity, FIG. 3 shows a Ta film 141 and a TaOx film 145.
Were the same thickness. In this embodiment, the TaOx film 145 is
A) The A.O. film 146 extends outside the side surface. Figure 21
As described above, also in the present embodiment, the TaOx film 14 is used.
5 is the lower part of the barrier AO film 146 and the outer part thereof.
Have different film thickness values. Below the barrier A.O.
Film thickness t from the interface with the first wiring layer 146 to the outside.
11 grows gradually. The TaOx film 145 is a barrier AO film 1
Since 46 is formed in the same anodic oxidation step, the TaOx film is formed.
The interface between the barrier 145 and the barrier AO film 146 and its vicinity is Ta.
It is considered to be an oxide of an Al alloy,
The Ox film 45 is formed so as to push up the barrier AO film 146.
The interface end between the barrier AO film 46 and the Ta film 41 is made of Ta.
It is in a state of being closed by the Ox film 45, and the barrier A.
O. When the film is pressed against the Ta film 141
Conceivable. Therefore, Al expands from second wiring layer 143.
Very effective in preventing scattering. The barrier AO film 146 and the second wiring layer
Interface between the first wiring layer 146 and the TaOx film 145.
By being inside the interface, aluminum from the wiring
High diffusion prevention effect. This means that the barrier AO film 14
The interface between the first wiring layer 146 and the second wiring layer
Outside the interface of the aOx film 145 or when they match
Assuming that In this case, the second wiring
Below the layer, the first wiring layer 146 and the TaOx film 145
Fear that aluminum will diffuse from the interface
It is. In the structure of this embodiment, the second wiring layer 14
3 is in contact with only the first wiring layer.
The effect of preventing diffusion of nitrogen increases. Further, the barrier AO film 146 extends from the side to the outside.
The extended portion exists below the porous AO membrane 144.
Area. As described with reference to FIGS.
The Ox film 145 is the largest film under the porous AO film 44.
A portion 61 having a thickness t2, and a constant outside the portion 161.
There is a region 63 having a thickness t3. Therefore, this embodiment
In the wiring of FIG. 1, the TaOx film 145 is also a barrier AO film.
In the part extending from the side to the outside, the maximum film thickness t12 is taken
A portion 162 and a constant thickness t13 outside the portion 162
Region 163 exists. When Ta is oxidized,
Since the film thickness is about 2 to 4 times, the film thicknesses t12 and t13 are
2 to 4 times the thickness of the Ta film 141 (the first wiring layer 146).
You. The TaOx film 145 barrier AO film 14
The portion extending outward from the six sides is the porous AO membrane 144.
Was formed by anodizing in the presence of
is there. Therefore, the surface layer of the TaOx film 145 in this portion is
Reacts with the porous AO film 144 to form an alloy of Ta and Al.
It is considered to be an oxidized compound. The porous AO film 144 is etched.
By using as a mask, the TaOx film 145 and the insulating film
Since 148 is patterned in a self-aligning manner, TaO
The side surface of the x film 145 substantially coincides with the side surface of the insulating film 148,
Be coplanar. Also in this embodiment, after the anodic oxidation step,
Since there is no need to divide the wiring, the wiring layers 143 and s14
6 is not exposed, so the heat resistance of the wiring
No damage. [0078] EXAMPLE Hereinafter, the present invention will be described with reference to FIGS.
Examples will be described in detail. [Embodiment 1] In this embodiment, the present invention is applied to a TFT.
This is an example applied to. FIG. 5 is used for an embodiment of the present invention.
Will be described. 5 to 14 are schematic top views of the TFT.
Show. In FIG. 5, reference numeral 201 denotes an active layer of a TFT;
Reference numerals 202 and 203 denote an active layer 201 and a source electrode or a drain.
Contact with source electrode (source / drain contact
) And 204 are gate wirings. Note that the gate wiring 2
The portion of the electrode 04 overlapping with the active layer 201 is particularly called a gate electrode.
I will do it. Reference numeral 205 denotes the gate wiring 204.
Contact part with outgoing wiring (not shown) (gate contour
Part). FIG. 6 is a sectional view taken along the line AA ′ of FIG.
(A) shows. In FIG. 6A, reference numeral 206 denotes an insulating surface
207 is an insulating substrate made of silicon oxide.
Film, and a tantalum layer (T
a layer) 208 and an aluminum layer as a second wiring layer
(Al layer) Gate wiring 204 having a laminated structure with 209
Is provided. Further, the TFT portion shown in FIG. 5 is cut by BB '.
FIG. 6 (B) shows a cross-sectional view taken along the line. In addition, FIG.
2 shows a partially enlarged view of a region C. In FIG. 6, 2
Reference numerals 14 and 215 denote a source wiring made of a conductive film and a source wiring, respectively.
The lead wiring 2 shown in FIG. 6A is a rain wiring.
13 and the same material. The tantalum layer 208 is an aluminum layer 209
Is passed through the gate insulating film 207 to form the active layer 201.
As a blocking layer to prevent outflow (diffusion)
Also works. Such diffusion of aluminum can be achieved by heat treatment or static
The heat generated by electricity causes the aluminum alloy to become fluid
It may be caused by having
By providing a valve metal film under the aluminum film,
It is possible to prevent such diffusion. Referring to FIGS. 8 and 9, the TFT of this embodiment is
The manufacturing process will be described. First, the substrate 20 having an insulating surface
As 0, a glass substrate provided with an insulating film on the surface is prepared.
In addition, a silicon substrate with a thermal oxide film, a quartz substrate,
Using a ceramic substrate with a silicon film
Can be. Next, on the substrate 200, each TFT is activated.
An island-shaped semiconductor layer to be the layer 201 is formed. In FIG.
Only one active layer 201 is shown. The active layer 201 is
It is covered with an insulating film 207 made of copper. (FIG. 8A) In this embodiment, Japanese Patent Application Laid-Open No. Hei 7-130652
Active in polysilicon film formed by the described technology
A layer 201 is formed. In addition, a method of forming a polysilicon film
Means any known method such as a method using laser annealing.
Steps can be used. Also, Six Ge1-x (0 <
Even if a silicon germanium film represented by X <1) is used
good. Next, tantalum having a thickness of 20 nm is formed on the substrate 200.
Film (Ta film) 231 and 2 wt% scandium of 40 nm thickness
And an aluminum film (Al film) 232 containing
The film was formed by lamination in a putter device. And the Al film
232 is brought into contact with the probe P of the anodic oxidation device,
A thin barrier type alumina film (not shown) is formed on the surface of the Al film 232.
Was formed. This anodic oxidation step is performed in the resist mask 2
This is for improving the adhesiveness of the 33. Conditions are electrolytic solution
Ethylene glycol solution containing 3% tartaric acid in electrolytic solution
Solution, electrolyte temperature 30 ° C, ultimate voltage 10V, voltage
The application time was 15 minutes, and the supply current was 10 mA / 1 substrate. Soshi
Then, a resist mask 233 is formed. (FIG. 8 (B)) FIG. 14 is a schematic diagram of an anodizing apparatus.
The anodizing device was equipped with a power supply 251 and an electrolytic solution 253.
And a cathode (platinum) 254 and a positive electrode
The substrate 200 serving as a pole is connected to the power supply 251. Base
Both the plate 200 and the cathode 254 are immersed in the electrolytic solution 253.
On the substrate 200, the probe P of the device contacts the Al film 232
Is done. An alumina film (not shown) was etched with chromium mixed acid.
And then etch the aluminum film with aluminum mixed acid
To form an aluminum layer (Al layer) as a second wiring layer
209 was formed. The Al layer 209 is
It constitutes the upper layer. Note that in FIG.
Side Al layer 209 and right side Al layer 209 are separated from each other.
Although they are listed, they are actually integrated as shown in FIG.
You. The Al layer 209 on the left side toward the end is finally the active layer 2
01 and functions as a gate electrode of the TFT. Ma
The Al layer 209 on the right side is connected to an external terminal later.
It becomes a contact part for performing. FIG. 10 shows a cross section of the TFT in the state of FIG. 8C.
Figures and a plan view are shown. FIG. 10A is a plan view. FIG.
0 (B) is a TFT chip cut along XX 'in FIG. 10 (A).
It is sectional drawing of a channel length direction. FIG. 10 (C) is FIG.
FIG. 5A is a cross-sectional view taken along the YY ′ plane of FIG.
It corresponds to the cross-sectional view of the TFT in the width direction. FIG. 10 (A)
Is a plan view taken along the line YY 'in FIG.
You. Note that the planar shape of the Al layer 209 is actually
The shape is similar to the gate wiring 204, but simplified to a rectangular shape.
It has become. 10 and 11, the Al layer 209 is
And so on. Next, with the resist mask 233 left,
In the anodizing apparatus, the probe P is connected to the tantalum film 2
Anodizing was carried out by contacting with No. 31. Conditions are electrolytic solution
Using 3% oxalic acid aqueous solution (temperature 10 ° C)
Voltage 8V, voltage application time 40 minutes, supply current 20mA / 1 board
And Under these anodizing conditions, the side surface of the Al layer 209
The porous anodic oxide film 234 (hereinafter, porous A.O.
A film 234 is formed. A.O. membrane 234 is porous
It is an alumina film. (Fig. 8 (D)) After the resist mask 233 is removed,
In the anodic oxidation apparatus shown in FIG.
A pressure was applied and anodic oxidation was performed. The conditions are as follows:
Ethylene glycol solution containing 3% tartaric acid in dissolving solution
Used, electrolytic solution temperature 10 ° C, ultimate voltage 80V, voltage applied
The time was 30 minutes, and the supply current was 30 mA / 1 substrate. Tartaric acid penetrates the porous AO membrane 234.
As a result, the surface of the Al layer 209 is anodized to form a barrier type anode.
An extreme oxide film (referred to as a barrier AO film) 211 is formed.
You. The barrier AO film 211 is a non-porous alumina film. Ma
In the Ta film 231, the exposed portion and
The portion where the porous AO film 234 exists is also anodized.
Tantalum oxide film (hereinafter referred to as TaOx film)
Transformed into 210. Remaining tantalum layer (Ta layer) 2
08 is defined as the first wiring layer. In addition, TaOx film
210 is thicker than the Ta film 231,
Therefore, the same thickness is shown in FIG. (FIG. 8 (E)) FIG. 11 shows a cross section of the TFT in the state of FIG.
Figures and a plan view are shown. FIG. 11B is a cross-sectional view of FIG.
FIG. 3 is a cross-sectional view in the channel length direction of the TFT, which is cut at X ′.
FIG. 11C is a cross-sectional view taken along the YY ′ plane of FIG.
FIG. 3 is a plan view corresponding to a cross-sectional view of the TFT in a channel width direction.
You. FIG. 11A is a plan view taken along the line YY ′ of FIG.
FIG. As shown in FIG. 11, barrier A.
Porous A.O. membrane 234 projecting from the side of O. membrane 211
The thickness tp of the barrier A.O. film 211 and the thickness tb of the barrier A.O.
All around 209 are uniform. Using the A.O. films 211 and 234 as masks,
The aOx film 210 and the insulating film 207 are etched. Edge
Ching is performed by dry etching using CHF3 gas.
Do. (FIG. 8 (F)) By aluminum mixed acid. Porous AO membrane 23
4 is removed by etching. By this process,
The gate wiring in which the Ta layer 208 and the Al layer 209 are stacked is 2
04 is completed. (FIG. 9A) The entire side surface of the gate wiring 204 is Ta
Structure covered with Ox film 210 and barrier AO film 209
Has become. The TaOx film 210 is on the barrier AO film 209 side.
It extends outside the plane. FIG. 12 shows a cross section of the TFT in the state of FIG.
Figures and a plan view are shown. FIG. 12A is a plan view. FIG.
2B is a TFT chip cut along the line XX ′ in FIG.
It is sectional drawing of a channel length direction. FIG. 12C shows FIG.
FIG. 5A is a cross-sectional view taken along the YY ′ plane of FIG.
It corresponds to the cross-sectional view of the TFT in the width direction. FIG. 12 (A)
Is a plan view taken along the line YY 'in FIG.
You. As shown in FIG. 12, from the side of the barrier AO film 211
The length of the extending TaOx film 210 corresponds to the thickness tp.
Then, it becomes uniform all around the Al layer 209. Further, as described above, the TaOx film 210
Referring to FIG. 7, the film thickness is at least the active layer 201 or
Is a region 261 on the island-shaped gate insulating film.
Below the O. film 236, its thickness t2
1 becomes thinner. The AO film 2 of the TaOx film 210
11 extends to the lower part of the porous A.O.
Area that existed in Therefore, on the outside of the A.O.
Is that the TaOx film thickness gradually increases toward the outside,
The film thickness t22 becomes maximum at the portion indicated by 62. Further part
From 262 to the outside, the film thickness gradually decreases,
At 263, the film thickness t23 becomes substantially constant. In this embodiment, the Ta layer 208 and the TaO
The interface between the x film 210 and the Al layer 208 and the barrier AO film 2
By being outside the interface of No. 11, as described above,
The effect of preventing Al from diffusing from the Al layer 208 is
Very high. The TaOx film 210 is a barrier AO film 2
Since 11 is formed in the same anodic oxidation step, the TaOx film
210 is formed so as to push up the barrier AO film 211.
ing. Therefore, the barrier AO film 211 and the Al layer 208
Of the interface is closed by the TaOx film 210.
Press the barrier AO film 211 against the Al layer 209.
It is considered that it is in a state where it can be run. Therefore, the Al layer
The effect of preventing Al from diffusing from 209 is very high. Next, impurity ions for imparting one conductivity are
It is added to the active layer 201. Fabricate N-channel TFT
To do this, add phosphorus or arsenic to make a P-channel TFT.
For the production, boron or gallium is added. These impure
Ion implantation can be performed by ion implantation,
Zuma doping or laser doping
Means may be used. In addition, a CMOS circuit
If necessary, use a resist mask to implant impurity ions.
I just need to split it. This step is performed by dividing the acceleration voltage into two parts.
The first time, the acceleration voltage was set as high as about 80 keV,
For the first time, the acceleration voltage is set as low as about 30 keV. This
As a result, the first time, the TaOx film 308 and the insulating film 20 are formed.
7, impurity ions are also added below TaOx for the second time.
The film 210 and the insulating film 207 serve as a mask, and
No impurity ions are added. By such an impurity ion adding step,
TFT channel formation region, source region 222, drain
Region 223, low concentration impurity region (LDD region) 22
4, 225 are formed in a self-aligned manner. Region 221 is not
The region where no pure substance was added,
An area and an offset area are formed. Note that each impurity region
The concentration of impurity ions added to the region is set appropriately by the practitioner
Just do it. (FIG. 7, FIG. 9 (B)) Referring to FIG. 7, in active layer 201,
The drain region 223 (source region 222) is
07 and the TaOx film 210 do not exist.
It is formed. The low concentration impurity region 225 (224)
O. Outside the film 211, the insulating film 207 and TaOx
A film 210 is formed in the region above it. Cha
The tunnel formation region 221 has a barrier AO.
It is formed in the existing area. In the channel formation region 221, the gate
Effective channel where electric field is applied directly by electrodes
The formation region is a region 221a where the Ta layer 208 exists.
You. A.O. film 211 and Ta via gate insulating film 207
The region 221b where the Ox film 210 exists is from the gate electrode.
The applied electric field is small. Therefore, the length of the region 221b
If it is large, it will effectively function as an offset area,
The qualitative channel formation region is only the region 221a. The length of the region 221b is determined by the TaOx film 210.
The length corresponding to the length of the barrier A.O.
Therefore, the length is controlled by the anodic oxidation shown in FIG.
Determined by the process. That is, the thickness of the barrier A.O.
It is determined. However, if the length of the region 221b is small,
The impurity also wraps around the region 221b and becomes a low concentration impurity.
Will work. About 200 nm barrier AO film
If it is more than m, it functions as a mask for doping
Therefore, it is necessary to make the region 221b function as an offset region.
Can be. The area 221b is an offset area.
In the case of functioning, reduction of the on-current becomes a problem.
Therefore, the driving voltage of the gate electrode is about 10 to 50 V T
In the FT, the area 221b is used as an offset area,
A priority may be given to reducing the off-current value. On the other hand, drive
In the case of a low voltage of about 1.5 to 5 V, the length of the region b
Function as low concentration impurity region (LDD)
It is preferable to give priority to raising the on-current value. Incidentally, the low concentration impurity region (LDD region) 2
24 and 225 pass through the insulating film 207 and the TaOx film 210.
The TaOx film is formed by adding impurities
If 210 is too thick, it will decrease throughput.
U. Further, low concentration impurity regions (LDD regions) 224, 2
25 to obtain a desired resistance value.
In some cases, it cannot be done. The insulating film 207 has a thickness of about 50 to 100 nm.
Therefore, the maximum thickness of the TaOx film 210 is 100 nm.
You. When oxidized, the Ta film 231 becomes about 2 to 4 times thicker.
Therefore, the initial thickness of the Ta film 231 is set to 50 nm or less.
Preferably. After the step of adding impurity ions is completed,
Furnace annealing, lamp annealing, laser annealing
Or a heat treatment using them in combination to add impurities
Activate the ions. The side surface of the alumina film 211
Tantalum oxide 210 film projecting from
When the metal layer remains, the low-concentration impurity regions 224, 2
The voltage is applied to the gate wiring 25 by the gate wiring.
This is inconvenient. Therefore, after the addition step, 400
Tantalum remaining after thermal oxidation at a temperature of ~ 600 ° C
The layer may be oxidized. Next, an interlayer insulating film 2 made of a silicon oxide film
12 is formed to a thickness of 1 μm. Next, the interlayer insulating film 2
12 is patterned to form a contact hole.
The formation of these contact holes 236 to 238 is as follows.
And do it. First, LAL500 manufactured by Hashimoto Kasei Co., Ltd.
The interlayer insulating film 212 is etched using an etchant called
Switch. LAL500 is compatible with ammonium fluoride
Several percent in buffered hydrofluoric acid mixed with hydrofluoric acid and water
This is an etchant to which a surfactant is added. Of course, others
Buffered hydrofluoric acid may be used. The buffered hydrofluoric acid used here was oxidized silicon oxide.
Recon film can be etched at relatively high speed
preferable. Since the interlayer insulating film 212 is as thick as 1 μm, it is etched.
The higher the rate, the higher the throughput. Thus, the interlayer insulating film 212 is etched.
At the time, the source region 222 and the drain
The region 223 is exposed and the contact holes 236 and 23 are exposed.
7 is completed. Barrier AO film 2 at the gate contact
11 is exposed. Next, ammonium fluoride and fluoride
A thin mixture of 2: 3: 150 (vol.%) Of hydrogen acid and water
Proceed with etching using a buffered hydrofluoric acid
You. In this buffered hydrofluoric acid, a silicon film,
That is, the source region 222 and the drain region 223 are almost
Not touched. However, the burr of the gate contact
A. The A.O. film 211 is etched and the underlying Al layer 20 is etched.
9 is also etched. Finally, up to the Ta layer 208
Etching stops when the etching reaches,
A tact hole 238 is formed. (FIG. 9 (C)) When the state shown in FIG. 9E is obtained,
A source wiring 214 and a drain wiring 215 made of a conductive film are formed.
Formed and electrically connected to the gate wiring 204 using the same material.
The extraction wiring 213 to be formed is formed. (FIG. 9 (D)) In this embodiment, the source wiring 214 and the drain
Conductive film forming the connection wiring 215 and the extraction wiring 213
Is composed of titanium / aluminum alloy / titanium
Use layered wiring. In this way, high reactivity
Wiring with low resistance while protecting aluminum film with titanium
Can be realized. Of course, it can be applied to this embodiment.
The conductive film is not limited to this. In the structure of this embodiment, the contact hole 2
38 is formed by using the Ta layer 208 as an etching stopper.
Function, so process controllability and margin
It is greatly improved. That is, the over edge which has conventionally been a problem
Contact failure such as ching can be prevented. Ma
Also, an etcher that is difficult to handle industrially like chromium mixed acid
Buffered footprint that does not require
It is economical because acid can be used. FIG. 13 shows the active layer 201 of FIG.
Figure cut in channel width direction (direction orthogonal to channel length)
Corresponding to FIG. 13 shows a cut of the gate contact portion.
Surface parts are also shown at the same time. Conventionally, in a multilayer wiring, an interlayer insulating film 21
On the two surfaces, there is a step reflecting the lower structure. Wiring 2
13 is formed in such a stepped portion,
There has been a problem of disconnection of wiring at a step portion. Especially
Due to steps between the gate wiring and the gate insulating film
Is occurring. In this embodiment, the gate insulating film 207
Since the TaOx film 210 is formed around the surface,
Height difference between gate wiring 204 and gate insulating film 207 is reduced
In particular, steps due to gate wiring and gate insulating film
At 240, the wiring 213 is less likely to break. [Embodiment 2] In the embodiment 1, FIG.
As shown, when forming the contact hole 238,
Metal layer (Ta layer) 208 as an etching stopper
In this example, the etching strike was used.
Tantalum nitride layer (hereinafter referred to as Ta)_yNotation as N layer
The following is an example of using the following. In this specification, T
a_yN means tantalum containing nitrogen.
The composition is Ta_yN (y> 1). The Ta layer of Example 1 was formed as shown in FIG.
In addition to the function as a
As shown in (D), between the gate wiring and the extraction wiring
It also has a function of preventing occurrence of contact failure. It
Is Ta, which is a part of the extraction wiring 213 and the gate wiring.
Good ohmic contact with layer 208
is there. By the way, this Ta layer is_yWhen the N layer is used,
Good ohmic contact
You. [0126] Ta_yN layer has better ohmic contact
The reason I can get is Ta_yN layer has contact if y> 1
It has enough resistance to take, and further compared to Ta layer
And Ta_ySince the N layer is not easily oxidized naturally, the contact
When forming a hole,_yNatural oxide film on the surface of N layer
It is considered that it is not formed. Also, Ta_yN-layer is better ohmic
The reason for contact is Ta_yN is lower resistance and cheaper than Ta
It is also considered that a stable crystal structure can be obtained. Ta result
The crystal structure is low resistance and stable cubic (α-Ta) and high
Two kinds of tetragonal (β-Ta), which is metastable and metastable, are known.
You. Generally, at room temperature, if the film thickness is 1 μm or less, β-Ta
Grows preferentially, and low-resistance and stable α-Ta does not grow.
No. Various studies have been conducted to grow α-Ta
One of them is to add nitrogen when forming a Ta film.
is there. Ta obtained in this way_yN is cubic and stable
Therefore, it is known that the similarity of crystal structure with α-Ta is high.
ing. The manufacturing process of the TFT of this embodiment is described in FIG.
In (B), the Ta film 231 is made of Ta._yN film
Except for this, the manufacturing steps are the same as those of the first embodiment shown in FIGS.
You. Hereinafter, Ta_yAn example of N film formation conditions is shown below.
The invention is not limited to these film forming conditions. Ta_y
The N film is formed using Ta as a target and a back pressure of 4.0 × 1.
0^-FourPa, sputtering pressure 4.0 × 10^-1Pa, sputtering power
Flow 4A, pre-sputtering time 5 minutes, argon gas flow 5
0 sccm and a nitrogen gas flow rate of 2 sccm.
Ta with a thickness of nm_yAn N film was formed. The same components as in this embodiment
200 nm thick Ta obtained under film conditions_yThe resistivity of the N film is 3
0 to 50 μΩcm and the sheet resistance calculated from the resistivity.
The resistance value was 15 to 25 Ω / □ at 20 nm. This
The value of the resistivity is determined by changing the flow rate of nitrogen gas.
It can be controlled by the
Good. Also, Ta_yThe thickness of the N film is 1 to 50 nm (preferably
Is in the range of 5 to 30 nm, more preferably 5 to 20 nm)
It is preferable to select from
is not. Also, Ta_yN oxide film is Ta oxide
Since it is formed in the same process as the film in the same manner,
The TFT has the same characteristics as the Ta oxide film of Example 1.
Ta_yIt has an N oxide film. Therefore, Ta_yN film
Is used, the same as when the Ta film of Example 1 is used,
For example, the effect of preventing Al from diffusing is very high,
A TFT that does not require a voltage supply line for extreme oxidation can be obtained.
You. The semiconductor device of this embodiment will be described with reference to FIG.
I will tell. However, this embodiment is not limited to FIG.
Absent. The semiconductor device according to the present embodiment has a structure as shown in FIG.
And Ta_yThe product of stacking the Al layer 209 on the N layer 208
A semiconductor device provided with a wiring having a layer structure,
The wiring is the Ta_yFormed in contact with the side surface of the N layer 208
Said Ta_yN oxide film 210 and the Al layer 209
Oxide film 211 of the Al layer formed in contact with the side surface of
And the following. In this embodiment, the Ta_ySide of N layer
Means Ta in the region 261_yN layer 208 and Ta_yN
Interface with the oxide film 210 of the Al layer
The plane means the Al layer 209 in the region 261 and the oxidation of Al.
The boundary surface with the object film 210. Further, the semiconductor device of this embodiment is shown in FIG.
Ta_yAn Al layer 209 is laminated on the N layer 208
A semiconductor device provided with wiring having a laminated structure.
And the wiring is Ta_yTa formed by oxidizing the N layer
_yFormed by oxidizing an N oxide film 210 and an Al layer
An Al oxide film 211, and the Al layer 209.
Below the Ta_yIn contact with only the N layer 208, the Al
The lower portion of the oxide film 211 is made of Ta._yN layer 208 and Ta
_yAnd is in contact with the oxide film 210 of N.
You. In this embodiment, the lower portion of the Al oxide film is
Means that the Al oxide film 211 in the region 261 is Ta
_yN layer 208 and Ta_yIn contact with the N oxide film 210
Part. Further, the semiconductor device of this embodiment is shown in FIG.
Ta_yAn Al layer 209 is laminated on the N layer 208
A semiconductor device provided with wiring having a laminated structure.
And the wiring is Ta_yTa formed by oxidizing the N layer
_yFormed by oxidizing an N oxide film 210 and an Al layer
An Al oxide film 211, an Al layer 209 and an Al
Interface with the oxide film 211 of Ta_yN layer 208 and Ta
_yThat it is inside the interface with the N oxide film 210
Features. In this embodiment, the Al layer and the oxide of Al
The interface with the film means that the Al layer 209 and the A
1 is a boundary surface with the oxide film 210,_yN
Layer and Ta_yThe interface with the N oxide film is in a region 261.
Ta_yN layer 208 and Ta_yN oxide film 210
It is a boundary surface. Further, the semiconductor device of this embodiment is shown in FIG.
Ta_yIn the oxide film 210 of N,
The portion existing under the oxide film 211 has a thickness that is outward.
Is gradually increasing. In this embodiment, the outside means Ta._yN layer
From 208, Ta_yThe direction toward the N oxide film 210
The standard. Further, the semiconductor device of this embodiment is shown in FIG.
Ta_yThe oxide film 210 of N is an oxide of Al
It is characterized by extending outside the side surface of the film 211.
You. Further, the semiconductor device of this embodiment is shown in FIG.
Ta_yThe oxide film 210 of N is an oxide of Al
The film 211 extends outside the side surface, and_yOxidation of N
The thickness of the object film 210 is lower than that of the Al oxide film 211 (eg,
For example, t21) and the outer side of the side surface of the Al oxide film 211.
(For example, t22). The semiconductor device of this embodiment is shown in FIG.
Ta_yThe oxide film 210 of N is an oxide of Al
The film 211 extends outside the side surface, and_yOxidation of N
The object film 210 is located outside the side surface of the Al oxide film 211.
And has a portion 262 where the film thickness is maximum.
I do. The semiconductor device of this embodiment is shown in FIG.
Ta_yThe oxide film 210 of N has the minimum thickness.
Outside the larger portion 262, the film thickness becomes substantially uniform.
263. Further, the semiconductor device of this embodiment is shown in FIG.
Ta_yThe oxide film 210 of N is an oxide of Al
The film 211 extends outside the side surface, and_yN layer 20
8 has a laminated structure in which an Al layer 209 is laminated on
Is the activation of at least one insulated gate transistor
Layers, and on one active layer, Ta_yN
Oxide film 210 is higher than the side surface of Al oxide film 211.
It has a portion 262 where the film thickness is maximum on the outside
And Further, the semiconductor device of this embodiment is shown in FIG.
Ta_yN oxide film is on the side of Al oxide film
More outward than Ta_yOn the N layer 208, Al
A wiring having a stacked structure in which the layers 209 are stacked is at least
Also overlaps the active layer of one insulated gate transistor
And on one active layer, Ta_yN oxide film 2
10 has a film thickness outside the side surface of the Al oxide film 211.
A portion having a maximum portion 262, wherein the film thickness is maximum;
There is a region 263 where the film thickness becomes almost uniform outside the minute.
It is characterized by that. The semiconductor device of this embodiment is shown in FIG.
Ta_yPart where the thickness of the N oxide film becomes maximum
The thickness of 262 is 2 to 4 times the thickness of Al layer 208.
It is characterized by the following. Further, the semiconductor device of this embodiment is shown in FIG.
Ta_yThe thickness of the N oxide film becomes almost uniform
The thickness of the region 263 is 2 to 4 times the thickness of the Al layer 208.
There is a feature. The semiconductor device of this embodiment is shown in FIG.
Ta_yAn Al layer 209 is laminated on the N layer 208
The wiring having the laminated structure is formed on the island-shaped insulating film 207.
And Ta_yThe side surface of the N oxide film 210 is the island-shaped insulation.
It is characterized by being substantially coincident with the side surface of the film 207. Further, the semiconductor device of this embodiment is shown in FIG.
Ta_yAn Al layer 209 is laminated on the N layer 208
Insulated gate type having a gate wiring having a laminated structure
A semiconductor device having a plurality of transistors, wherein
Port wiring is Ta_yTa formed by oxidizing the N layer_yN
Oxide film 210 and Al formed by oxidizing the Al layer
And an oxide film 211 of Ta._yN oxide film 21
0 extends outside the side surface of the Al oxide film 211.
The interface between the Al layer 209 and the Al oxide film 211 is
Ta_yN layer 209 and Ta_yInterface with N oxide film 210
It is characterized by being on the inside. The semiconductor device of this embodiment is shown in FIG.
As shown in FIG.
Ta on the active layer via the gate insulating film 207._yOxidation of N
In the region where only the material film 210 exists, the low-concentration impurity region 2
25 is formed. The semiconductor device of this embodiment is similar to that of FIG.
As shown in (C), at least the gate wiring
Overlaps with one of the active layers of the transistor,
Ta in the channel width direction_yThe oxide film 210 of N is made of Al
Extending outside the oxide film 211 of
I do. The semiconductor device of this embodiment is similar to that of FIG.
As shown in (A), Ta_yAl layer 2 on N layer 209
Wiring having a layered structure in which the layers 10 are laminated, and an insulating film
Extraction wiring formed above the gate wiring
The line 213, the gate wiring and the extraction wiring 213 are electrically connected.
And a contact hole for
A semiconductor device having a tact structure in its configuration, wherein
The line is Ta_yTa formed by oxidizing the N layer_yOxidation of N
Of the object film 210 and Al formed by oxidizing the Al layer
The contact hole is an Al layer.
209, and the lead-out wiring 213 is
Ta at the contact hall_yIn contact with N layer 208
It is characterized by the following. Further, the semiconductor device of this embodiment has a Ta_yN
Oxide film is Ta_yFormed by anodizing the N layer
The Al oxide film is formed by anodizing the Al layer.
Formed. Further, the semiconductor device of this embodiment has a Ta_yN
The layer and the Al layer are characterized by different anodic oxidation rates.
You. The semiconductor device according to the present embodiment has a Ta_yN
Oxide film 210 and Al oxide film 211 have the same anode
It is characterized by being formed in an oxidation step. Further, the semiconductor device of this embodiment has a Ta_yN
The thickness of the layer is 1 to 50 nm. Further, the semiconductor device of this embodiment is the same as that of the above-described Al device.
The layer is aluminum or aluminum-based
It is characterized by being made of a material. Further, the semiconductor device of this embodiment is characterized in that
The tantalum layer is a tantalum layer containing nitrogen.
Features. Further, the semiconductor device of this embodiment is characterized in that
The composition of the tantalum layer is Ta_yN (y> 1)
Features. Further, the semiconductor device of this embodiment has a display device.
Devices, image sensors, arithmetic integrated circuits, high-frequency modules
Or any one of the following. Further, the semiconductor device of this embodiment has the display
Video camera, still camera, project
Projector, projection TV, head mount disc
Play, car navigation, personal computer
Data or portable information terminal equipment.
You. In this embodiment, an etching stopper is used.
Ta_yAlthough a single N layer was used,_yN layer and Ta layer
The same effect can be obtained by layering. That is, Ta_yN /
Ta layer, Ta layer / Ta_yN layer or Ta layer / Ta_y
It is also possible to adopt a laminated structure of N layer / Ta layer. With the structure of this embodiment, the gate
Prevents the materials that make up the electrodes and gate wiring from diffusing
can do. Also, the voltage supply wiring for anodic oxidation
It is possible to anodize wiring without forming
Space for forming voltage supply wiring, voltage supply wiring
Without considering the etching margin for dividing
Circuit design becomes possible. Therefore, high integration and basic
Reduction of the board area is promoted. Also, a good connection between the gate wiring and the take-out wiring
Good ohmic contact can be made. Also, over
ー Prevents contact failure such as etching
You. In addition, it is difficult to handle industrially like chromium mixed acid.
A buffer that can be easily managed without the need for a buffer
It is economical because you can use dofluoric acid. [Embodiment 3] The structure of the present invention is applied to a TFT.
MOSFET formed using silicon substrate without limitation
It is also possible to apply to. The present invention uses MOS
FIG. 15 shows an example in which the present invention is applied to an FET. In FIG. 15, reference numeral 301 denotes a silicon substrate;
302 is a field oxide film, 303 is a source region, 30
4 is a drain region, and 305 is a pair of LDD regions.
The other structure is described in the first embodiment.
Since the structure is almost the same, the description is omitted. Also, MO
As a structure to make SFET inside the well structure
Is also good. As described above, the present invention can be applied to the TFT for the MO.
It can also be applied to SFETs. Also, TF
Not only semiconductor devices such as T and MOSFET, but also anodic acid
Formed on a layer different from the aluminum wiring protected by the passivation film.
When a structure that electrically connects the conductive film is required
It is effective to apply the present invention. [Embodiment 4] In Embodiment 1, an NTFT is manufactured.
Although the case of manufacturing was explained as an example, the present invention
Needless to say, it can be applied to T. Note that
Substantially P-channel TFT (PTFT) fabrication steps and conditions
One example is shown below. First, a source and a source into which phosphorus ions have been implanted.
Impurity ion (bore) for imparting P-type conductivity to the rain region
Ron). 5% with hydrogen as doping gas
Use diborane diluted in water. Acceleration voltage is 60 to 90
kV, dose amount is 1.times.10@13 to 8.times.10@15 atoms / c.
m3. Note that the source and drain regions are implanted.
From the maximum value of boron concentration to the maximum value of phosphorus ion concentration
3 × 10 19 to 3 × 10 21 atoms / cm 3
It is important to adjust the dose so that This
As a result, the conductivity types of the source and drain regions are inverted and P
A type impurity region is formed. The conductivity of the LDD region
The mold may be reversed. When a known CMOS technology is used, N
Complementary combination of channel type TFT and P channel type TFT
It is also easy to form a combined CMOS circuit. In this embodiment, a CMOS circuit is formed on the same substrate.
Composed of a driving circuit and an N-channel TFT
Active matrix with pixel matrix circuit
FIG. 16 shows an example of manufacturing a substrate. In FIG.
Here, an N-channel TFT 601 and a P-channel TF
T602 forms a CMOS circuit 603. The aforementioned
The same as the first embodiment by using the well-known CMOS technology.
The process can be easily realized. The pixels constituting the pixel matrix circuit
The TFT (NTFT in this embodiment) 604 is the same as in the first embodiment or
Can be realized by adding some steps to the manufacturing steps described in Embodiment 4.
Can appear. First, according to the steps of Example 1 or Example 4,
Thus, an N-channel TFT 601 and a P-channel TFT
602, the pixel TFT 604 is completed. Next, FIG.
As shown, a first planarization film 610 is formed. In this embodiment
Is silicon nitride (50 nm) / silicon oxide (25 nm) / acrylic (1
μm) is used as the first planarization film 610.
You. In addition, organic materials such as acrylic and polyimide
Resin film is a solution-coated insulating film formed by spin coating
Therefore, a thick film can be easily formed and a very flat surface
It is possible to get. Therefore, a film thickness of about 1 μm
It is possible to form with high throughput
A flat surface is obtained. Next, a light-shielding conductive film is formed on the first planarizing film 610.
A black mask 611 made of an electric film is formed. Also,
Prior to formation of the rack mask 611, a first planarizing film
610 is etched to leave only the lowermost silicon nitride film.
The formed concave portion is formed in advance. By doing so, a concave portion was formed.
In the part, the drain electrode and the black mask are silicon nitride films
, And forms the storage capacitor 612 there.
You. Since silicon nitride has a high relative dielectric constant and a small film thickness,
Easy to secure large capacity. When the black mask 611 is formed,
After forming the auxiliary capacitance 612, the second planarization film 613 is formed.
 It is formed of 1.5 μm thick acrylic. Shape auxiliary capacity 612
The formed part has a large step, but such a step is not enough.
It can be flattened in minutes. Finally, the first planarizing film 610 and the second
A contact hole is formed in the planarizing film 613, and a transparent conductive film is formed.
Form pixel electrode 614 made of film (typically ITO)
I do. Thus, the active matrix substrate shown in FIG.
Is completed The pixel electrode 614 has high reflectivity.
Conductive film, typically aluminum or aluminum
If the material used as the main component is used, the reflective AMLCD
An active matrix substrate can also be manufactured. In FIG. 16, the gate of the pixel TFT 604 is shown.
The gate electrode has a double gate structure, but a single gate
Multi-gate structure such as triple gate structure
The structure may be as follows. The active matrix substrate shown in FIG.
Is not limited to the structure of this embodiment. Book
The feature of the invention resides in the configuration of the gate wiring.
The configuration may be appropriately determined by the practitioner. For example,
TFTs 601, 603 and 604 are bottom gate type
It is easy for those skilled in the art. Example 5 In this example, the TF of the present invention was used.
An example in which an AMLCD is configured using T will be described.
FIG. 17 shows the appearance of the AMLCD of this embodiment. In FIG. 17A, reference numeral 701 denotes an active
A pixel matrix circuit 702,
The source side drive circuit 703 and the gate side drive circuit 704 are shaped.
Has been established. The drive circuit consists of an N-type TFT and a P-type TFT
It is preferable to compose complementary CMOS circuits.
Good. 705 is a counter substrate. The AMLCD shown in FIG.
The matrix substrate 701 and the counter substrate 705 have the same end face.
And are stuck together. However, only certain parts are opposed
After removing the substrate 705, the exposed active matrix
FPC (Flexible Print Circuit)
) 706 are connected. By this FPC706,
To transmit an external signal to the inside of the circuit. Also, use the surface on which the FPC 706 is mounted.
Then, IC chips 707 and 708 are attached.
These IC chips are video signal processing circuits,
Pulse generation circuit, gamma correction circuit, memory circuit, arithmetic circuit
And various circuits are formed on a silicon substrate.
You. In FIG. 17A, two are attached, but one is attached.
However, there may be more than one. Also, a configuration as shown in FIG.
You. In FIG. 17B, the same portions as in FIG.
The same reference numerals are given. Here, the IC chip shown in FIG.
The signal processing that has been done by
The example performed by the logic circuit 709 formed by
doing. In this case, the logic circuit 709 is also connected to the drive circuit 7.
03 and 704, the CMOS circuit is basically used.
It is. Further, the AMLCD of this embodiment is a black mask.
Configuration in which a disk is provided on an active matrix substrate (BM o
n TFT), but in addition, a black
A mask may be provided. [0187] Further, a color table is displayed using a color filter.
Or ECB (Electric Field Controlled Birefringence) mode
Drive the liquid crystal in the GH (guest host) mode,
It is good also as composition not using a color filter. Further, Japanese Patent Application Laid-Open No. 8-15686 discloses
Using a microlens array as in technology
Is also good. [Embodiment 6] The structure of the present invention is similar to that of AMLC.
Applicable to various other electro-optical devices and semiconductor circuits other than D
can do. As an electro-optical device other than the AMLCD, E
L (electroluminescence) display device and image sensor
And the like. Further, as a semiconductor circuit, an IC chip is used.
Arithmetic processing circuits such as microprocessors
High-frequency module (MMIC) that handles input / output signals of
Etc.). As described above, the present invention comprises an insulating gate type TFT.
For all semiconductor devices that function with the circuit
It is possible to apply. [Embodiment 7] As shown in Embodiments 5 and 6,
AMLCD is used as a display for various electronic devices.
Used. Note that the electronic devices described in this embodiment are
Defined as a product equipped with an active matrix liquid crystal display
I do. As such an electronic device, a video camera
LA, still camera, projector, projection
TV, head mounted display, car navigation
Computers, personal computers (including notebooks), mobile phones
Information terminals (mobile computers, mobile phones, etc.)
No. One example of them is shown in FIG. FIG. 18A shows a mobile phone, and the main body 20 is provided.
01, audio output unit 2002, audio input unit 2003, display
Device 2004, operation switch 2005, antenna 200
6. The present invention employs an audio output unit 2002 and an audio input unit.
It can be applied to the power unit 2003, the display device 2004, etc.
Wear. FIG. 18B shows a video camera,
2101, a display device 2102, a voice input unit 2103, an operation
Operation switch 2104, battery 2105, image receiving unit 21
06. The present invention relates to a display device 2102, an audio input device.
Can be applied to the power unit 2103 and the image receiving unit 2106.
You. FIG. 18C shows a mobile computer (mode).
-Building computer), main body 2201, camera unit
2202, image receiving unit 2203, operation switch 2204, table
It comprises a display device 2205. The present invention relates to an image receiving unit 220.
3. Applicable to the display device 2205 and the like. FIG. 18D shows a head mount display.
A main body 2301, display device 2302, band unit
2303. The present invention is suitable for the display device 2302.
Can be used. FIG. 18E shows a rear projector.
Main body 2401, light source 2402, display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. Departure
The light can be applied to the display device 2403. FIG. 18F shows a front type projector.
And the main body 2501, the light source 2502, the display device 250
3, composed of an optical system 2504 and a screen 2505
You. The present invention can be applied to the display device 2503.
You. As described above, the applicable range of the present invention is extremely wide.
It can be applied to electronic devices in all fields.
You. In addition, there are other electronic signboards and displays for advertising
It can also be used for such purposes. [0202] According to the present invention, a voltage supply for anodic oxidation is also provided.
Anodic oxidation of wiring without forming wiring
Space for forming the voltage supply wiring and the voltage supply
Consider the etching margin for dividing the supply wiring
Circuit design becomes possible without care. Therefore, high integration of the circuit
And reduction of the substrate area is promoted. [0203]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating a step of manufacturing a wiring. FIG. 2 is a top view and a side view of a wiring. FIG. 3 is a cross-sectional view illustrating a step of manufacturing a wiring. (Embodiment 2) FIG. 4 is an enlarged sectional view of a wiring. (Embodiment 2) FIG. 5 is a top view of a TFT. (Example 1) FIG. 6 is a sectional view of a gate contact portion and a TFT. (Example 1) FIG. 7 is a partially enlarged view of FIG. 6 (B). (Example 1) FIG. 8 is a cross-sectional view illustrating a manufacturing process of a TFT. (Example 1) FIG. 9 is a cross-sectional view illustrating a manufacturing process of a TFT. (Example 1) FIGS. 10A and 10B are a plan view and a cross-sectional view of a TFT during a manufacturing process (Example 1). FIGS. 11A and 11B are a plan view and a cross-sectional view of a TFT during a manufacturing process (Example 1). FIG. 13 is a plan view and a cross-sectional view of a TFT during a manufacturing step (Example 1). FIG. 13 is a schematic view of a TFT during a manufacturing step and a cross-sectional view (Example 1). FIG. 15 is a cross-sectional view of a MOS transistor. (Example 3) FIG. 16 is a sectional view of an active matrix substrate. (Example 4) FIG. 17 is a perspective view of an AMLCD substrate. FIG. 18 is a structural view of an electronic device using a semiconductor device (Example 5). (Example 7) FIG. 19 is a sectional view of an aluminum pattern showing an experimental procedure of an anodizing step. FIG. 20 is a partially enlarged view of the sectional structure of FIG. 19; FIG. 21 is an SEM photograph showing the cross-sectional structure of FIG. FIG. 22 is a cross-sectional view showing a manufacturing process of a TFT using a conventional anodic oxidation process. (Conventional example) [Description of code] 200 Substrate 201 Active layer 204 Gate wiring 208 Tantalum film (Ta film) 209 Aluminum film (Al film) 210 Tantalum oxide film (TaOx film) 211 Barrier type anodic oxide film (Barrier AO film) )

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Setsuo Nakajima             398 Hase, Atsugi City, Kanagawa Prefecture             Conductor Energy Laboratory

Claims (1)

Claims: 1. A semiconductor comprising a wiring having a laminated structure in which a second wiring layer made of a second conductive film is stacked on a first wiring layer made of a first conductive film. The device, wherein the first conductive film includes at least a tantalum nitride layer, the wiring is an oxide film of the first conductive film formed in contact with a side surface of the first wiring layer, An oxide film of the second conductive film formed in contact with a side surface of the second wiring layer. 2. A semiconductor device comprising a wiring having a stacked structure in which a second wiring layer made of a second conductive film is stacked on a first wiring layer made of a first conductive film, The first conductive film includes at least a tantalum nitride layer, and the wiring is formed by oxidizing the first wiring layer and oxidizing the second wiring layer. And a second oxide film, wherein the second wiring layer is in contact with only the first wiring layer, and a lower portion of the second oxide film has the first wiring layer and A semiconductor device which is in contact with the first oxide film. 3. A semiconductor device comprising a wiring having a stacked structure in which a second wiring layer made of a second conductive film is stacked on a first wiring layer made of a first conductive film, The first conductive film includes at least a tantalum nitride layer, and the wiring is formed by oxidizing the first wiring layer and oxidizing the second wiring layer. An interface between the second wiring layer and the second oxide film, wherein an interface between the second wiring layer and the second oxide film is higher than an interface between the first wiring layer and the first oxide film. Wherein the semiconductor device is also inside. 4. The method according to claim 2, wherein in the first oxide film, a portion existing below the second oxide film gradually increases in thickness toward the outside. Characteristic semiconductor device. 5. The semiconductor device according to claim 2, wherein the first oxide film extends outside a side surface of the second oxide film. 6. The first oxide film according to claim 2, wherein the first oxide film extends outside a side surface of the second oxide film. A thickness of the semiconductor device is different between a lower portion of the second oxide film and an outer side of a side surface of the second oxide film. 7. The first oxide film according to claim 2, wherein the first oxide film extends outside a side surface of the second oxide film. A semiconductor device having a portion having a maximum thickness outside a side surface of the second oxide film. 8. The semiconductor device according to claim 7, wherein the first oxide film has a region where the film thickness is substantially uniform outside a portion where the film thickness is maximum. 9. The semiconductor device according to claim 2, wherein the first oxide film extends outside a side surface of the second oxide film, and the wiring is formed of at least one insulated gate transistor. The first oxide film overlaps with an active layer, and has a portion on one active layer where the thickness is maximum outside a side surface of the second oxide film. Semiconductor device. 10. The semiconductor device according to claim 2, wherein the first oxide film extends outside a side surface of the second oxide film, and the wiring includes at least one wiring. The first oxide film overlaps with the active layer of the insulated gate transistor, and has a portion on one active layer where the thickness is maximum outside the side surface of the second oxide film. A semiconductor device having a region where the film thickness is substantially uniform outside a portion where the film thickness is maximum. 11. The semiconductor device according to claim 6, wherein the thickness of the portion having the maximum thickness is two to four times the thickness of the first wiring layer. Semiconductor device. 12. The device according to claim 7, wherein the thickness of the region where the thickness is substantially uniform is 2 to 4 times the thickness of the first wiring layer. Semiconductor device. 13. The island according to claim 2, wherein the wiring is formed on an island-shaped insulating film, and a side surface of the first oxide film substantially coincides with a side surface of the island-shaped insulating film. A semiconductor device, comprising: 14. A semiconductor device comprising: a first wiring layer formed of a first conductive film;
A semiconductor device including a plurality of insulated gate transistors each having a gate wiring having a stacked structure in which a second wiring layer formed of a second conductive film is stacked, wherein the first conductive film includes at least a tantalum nitride layer, The gate wiring includes: the first oxide film formed by oxidizing a first wiring layer; and the second oxide film formed by oxidizing a second wiring layer. The first oxide film extends outside the side surface of the second oxide film, and the interface between the second wiring layer and the second oxide film is formed by the first wiring A semiconductor device located inside an interface between the layer and the second oxide film. 15. The low-concentration impurity region according to claim 14, wherein in one active layer of the transistor, a region where only the first oxide film exists above the active layer via a gate insulating film has a low concentration impurity region. A semiconductor device characterized by being formed. 16. The transistor according to claim 14, wherein the gate wiring overlaps at least one of the active layers of the transistor, and the first oxide film is formed on the active layer in a channel width direction. A semiconductor device extending outside the oxide film. 17. A semiconductor device comprising: a first wiring layer formed of a first conductive film;
A first wiring having a stacked structure in which a second wiring layer made of a second conductive film is stacked; a second wiring formed in a layer above the first wiring with an insulating film interposed; A semiconductor device including a contact structure including a first wiring and a contact hole for electrically connecting the second wiring, wherein the first conductive film includes at least a tantalum nitride layer; The first wiring includes: a first oxide film formed by oxidizing a first wiring layer; and a second oxide film formed by oxidizing a second wiring layer. Wherein the contact hole is formed to penetrate the second wiring layer, and the second wiring is in contact with the first conductive film in the contact hole. 18. The semiconductor device according to claim 2, wherein the first oxide film is formed by anodizing the first conductive film, and the second oxide film is formed by the second oxide film. 2. A semiconductor device formed by anodizing the conductive film of No. 2. 19. The semiconductor device according to claim 2, wherein the first conductive film and the second conductive film have different anodic oxidation rates. 20. The semiconductor device according to claim 19, wherein the first oxide film and the second oxide film are formed in the same anodic oxidation step. 21. The semiconductor device according to claim 2, wherein the first conductive film has a thickness of 1 to 50 nm. 22. The semiconductor device according to claim 2, wherein the second conductive film is made of aluminum or a material containing aluminum as a main component. 23. The semiconductor device according to claim 2, wherein the tantalum nitride layer is a tantalum layer containing nitrogen. 24. The semiconductor device according to claim 2, wherein a composition of the tantalum nitride layer is Ta _y N (y> 1). 25. A semiconductor device according to claim 2, wherein the semiconductor device is one of a display device, an image sensor, an arithmetic integrated circuit, and a high-frequency module. 26. The semiconductor device according to claim 25, wherein the semiconductor device is any one of a video camera, a still camera, a projector, a projection TV, a head mounted display, a car navigation, a personal computer, and a portable information terminal equipped with the display device. A semiconductor device, characterized in that: