JPH1131819A - Electrostatic breakdown protective transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-performance electrostatic breakdown protective transistor without the increase in the number of processes, while the rise in manufacturing cost is suppressed. SOLUTION: On a gate electrode 8, a plurality of comb-like gate electrode extension parts 8b, extending from a gate electrode main body part 8b to a source region 6 side and a drain region 5 side, are provided, a gate sidewall insulating film 10 is formed so as to fill the gaps among the teeth the comb of the gate electrode extension part 8b, and a silicide layer 9 is formed on the gate electrode 8 is a source region 6 and a drain region 5 except for the region where the gate sidewall insulating film 10 is formed. Such a drain regions 5 and a source region 6 below the gate sidewall insulating film 10 among the teeth of the comb of the gate electrode extension part 8b are of high resistance, and this high resistance is connected in series to the resistance of an interface between the silicide layer 9 and a source/drain diffused layer. Consequently concentration of electric field at this interface and resulting heat-accumulation are suppressed, improving the breakdown resistance. The silicide layer 9 is formed self-alignedly with the gate sidewall insulating film 10 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge protection transistor for protecting an internal circuit.

[0002]

2. Description of the Related Art In a MOS device, miniaturization causes an increase in parasitic resistance due to thinning of a diffusion layer, and therefore, a silicide structure for reducing the diffusion resistance is often used. However, in the silicide structure, a high-resistance layer is formed at the interface between the silicide layer and the diffusion layer, and when used in an electrostatic discharge protection transistor, the resistance of the diffusion layer is reduced. And the heat generated at this interface is intense. Thus, for example, US Pat. No. 5,021,853 (1)
According to 991.6.4), when selectively etching in the vertical direction for forming a gate sidewall insulating film, the protection transistor portion is masked and a non-salicide region is selectively formed. .

Hereinafter, a conventional electrostatic discharge protection transistor will be described with reference to the drawings. FIG. 5 is a circuit diagram of a conventional electrostatic discharge protection circuit. Reference numeral 1 denotes a pad for connection to an external circuit, 3 denotes a protection resistor, 4 denotes an internal circuit, and 11 denotes an electrostatic discharge protection transistor. FIG. 6 shows the electrostatic discharge protection transistor 11 of FIG.
1 ”), 5 is a drain region, 6 is a source region, 8 is a gate electrode, 9 is a silicide layer, 13
Denotes a semiconductor substrate, 14 denotes an isolation insulating film, and 16 denotes a gate oxide film.

In FIG. 5, an electrostatic charge applied to the pad 1 from the outside is caused to flow to the substrate by the bipolar operation after the protection transistor 11 exhibits the snapback characteristic, and the internal circuit is protected by the protection resistor 3. 4 does not flow, and the internal circuit 4 is protected. The protection transistor 11 is normally off and does not operate, and does not affect the circuit operation. This protection transistor 11 has the cross-sectional structure of FIG. 6, and allows the static charge applied to the drain region 5 side to flow to the source region 6 side by a parasitic bipolar operation.

In the protection transistor 11, a silicide layer 9 is formed on a drain region 5 and a source region 6 which are not covered with an insulating film 12 selectively formed by a mask, and a diffusion layer of the drain region 5 and the source region 6 is formed. The interface between the metal and the silicide layer 9 has a high resistance. On the other hand, the silicide layer 9 is not formed in the drain region 5 and the source region 6 in the portion covered with the insulating film 12, and the region is a high resistance region. Therefore, the high resistance of the drain region 5 and the source region 6 immediately below the insulating film 12 and the interface resistance between the diffusion layer and the silicide layer 9 are connected in series.
Due to the high-resistance drain region 5 and source region 6 immediately below the insulating film 12, an electric field is not concentrated on the interface resistance between the diffusion layer and the silicide layer 9, and the breakdown voltage of the protection circuit is improved.

FIG. 7 is a sectional view showing a manufacturing process of the protection transistor 11. This protection transistor 11 is configured as shown in FIG.
As shown in FIG. 7A, after an isolation insulating film 14, a gate oxide film 16, a gate electrode 8, a drain region 5 and a source region 6 are formed on a semiconductor substrate 13, as shown in FIG. Then, an insulating film 12 is formed on the entire surface. Next, as shown in FIG. 7C, a mask 15 made of a resist or the like is formed on the insulating film 12, and a predetermined region of the insulating film 12 is etched using the mask 15. Thereafter, as shown in FIG. 7D, a silicide layer 9 is formed in a region where the insulating film 12 is opened in a self-aligned manner.

[0007]

In order to manufacture the protection transistor 11 as described above, a mask 15 is required in order to selectively leave the insulating film 12 which defines the non-salicided region where the silicide layer 9 is not formed. Met. This results in an increase in the number of steps and an increase in manufacturing cost.

An object of the present invention is to provide a high-performance electrostatic discharge protection transistor which does not increase the number of steps and suppresses an increase in manufacturing cost in view of the above problems.

[0009]

According to a first aspect of the present invention, there is provided an electrostatic discharge protection transistor, comprising: a source region and a drain region which are arranged opposite to a surface of a semiconductor substrate of a first conductivity type and formed of a diffusion layer of a second conductivity type; A gate electrode main body provided between the source region and the drain region with a gate insulating film interposed therebetween, and a comb-like shape from the gate electrode main body to at least the drain region side of the source region side and the drain region side. A gate electrode comprising a plurality of gate electrode extensions formed by extension; a gate sidewall insulating film formed on the semiconductor substrate and on sidewalls of the gate electrode, filling a comb-shaped portion of the gate electrode extension; and a source region. And a silicide layer formed on the drain region except for the region where the gate sidewall insulating film is formed.

According to this structure, since the silicide layer is formed on the source region and the drain region excluding the region where the gate sidewall insulating film is formed, the source is self-aligned using the gate electrode and the gate sidewall insulating film as a mask. A silicide layer can be formed on the region and the drain region, and the gate sidewall insulating film can be patterned by strong anisotropic etching in the vertical direction without requiring a masking step. No masking step or the like is required, and the manufacturing cost can be reduced without increasing the number of steps.

A plurality of gate electrode extending portions are formed on the gate electrode so as to extend from the gate electrode body to the drain region side, and a gate sidewall insulating film is formed between the comb tooth portions of the gate electrode extending portion. And the silicide layer is formed on the source region and the drain region excluding the region where the gate sidewall insulating film is formed. Therefore, the gate sidewall insulating film between the comb teeth of the gate electrode extension is formed. The lower drain region becomes a high resistance region without a silicide layer, and this high resistance is connected in series with the resistance at the interface between the silicide layer and the source region and the drain region (hereinafter referred to as “silicide / diffusion layer interface”). Electric field concentration at the silicide / diffusion layer interface and heat generation due to the electric field concentration can be suppressed, and the breakdown voltage can be improved. In particular, since destruction occurs on the drain side to which an electrostatic charge is applied, by providing a gate electrode extension only on the drain region side, it is possible to improve electrostatic breakdown withstand voltage and to reduce the source region. The size of the transistor can be reduced.

According to a second aspect of the present invention, there is provided the electrostatic breakdown protection transistor according to the first aspect, wherein a plurality of gate electrode extensions are provided also on the source region side. In this manner, by providing a plurality of gate electrode extensions on the source region side, the source region under the gate sidewall insulating film between the comb teeth of the gate electrode extension on the source region side also has no silicide layer. It becomes a high resistance region, and the breakdown voltage can be further improved.

According to a third aspect of the present invention, in the electrostatic discharge protection transistor of the first or second aspect, the width of each gate electrode extension is set to be equal to or larger than the minimum design rule width of the gate electrode. Thereby, it is possible to easily form a stable shape of the extended portion of the gate electrode, which is easy to manage in size and conforms to the design rule.

According to a fourth aspect of the present invention, there is provided the electrostatic breakdown protection transistor according to the first or second aspect, wherein the interval between the extended portions of the gate electrode is 0.3 μm, which is twice the width of the gate side wall insulating film. It is below the added value. As a result, the breakdown voltage can be reliably improved.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention. Reference numeral 1 denotes a pad for connecting to an external circuit, and reference numeral 2 denotes an embodiment in which the internal circuit 4 is protected from external electrostatic noise. The form of the electrostatic breakdown protection transistor 3 is a protection resistor for protecting the internal circuit 4 from external electrostatic noise.

FIG. 2A is a plan view of the electrostatic discharge protection transistor 2 of FIG. 1 (hereinafter referred to as “protection transistor 2”), FIG. 2B is a sectional view taken along the line AA, and 5 is FIG. A drain region connected to the pad 1 through a contact 7a, a source region 6 grounded through a contact 7b, a gate electrode 8 composed of a gate electrode body 8a and a plurality of gate electrode extensions 8b, and a ground electrode 9. A silicide layer formed on the gate electrode 8 and on the drain region 5 and the source region 6; a gate insulating film 10 formed on the side wall of the gate electrode 8; a semiconductor substrate 13; Is a gate oxide film.

The protection transistor 2 has a drain region 5 and a source region 6 formed of, for example, an n-type diffusion layer on the surface of a p-type semiconductor substrate 13, and a gate oxide film 16 on the semiconductor substrate 13 via a gate oxide film 16. An electrode 8 is provided. The gate electrode 8 is provided with a plurality of gate electrode extensions 8b extending in a comb-like shape from the gate electrode body 8a toward the source region 6 and the drain region 5, and the gate sidewall insulating film 10 is formed as a gate electrode extension. 8b is formed so as to fill the space between the teeth of the comb. Then, the silicide layer 9 is
It is formed on the gate electrode 8 and on the source region 6 and the drain region 5 excluding the region where the gate sidewall insulating film 10 is formed. Note that the diffusion layers of the source region 6 and the drain region 5 are formed using the gate electrode 8 having the gate electrode body 8a and the gate electrode extension 8b as a mask, and the diffusion layer goes under the gate electrode 8. However, other than that, the source region 6 and the drain region 5 are not formed under the gate electrode 8.

In FIG. 1, an electrostatic charge applied to the pad 1 from the outside is caused to flow to the substrate by the bipolar operation after the protection transistor 2 exhibits the snap-back characteristic, while the internal resistance is changed by the protection resistor 3. 4 does not flow, and the internal circuit 4 is protected. The protection transistor 2 is normally off and does not operate, and does not affect the circuit operation. The protection transistor 2 causes the static charge applied to the drain side to flow to the source side by a parasitic bipolar operation.

In FIG. 2, inside the protection transistor 2, an electrostatic charge externally applied to the pad 1 of FIG. 1 flows to the drain region 5 through the contact 7a. The electrostatic charge is transferred from the silicide layer 9 to the interface between the silicide layer 9 and the drain region 5 as a diffusion layer (hereinafter referred to as “silicide / drain diffusion layer interface”), the drain region 5 below the gate sidewall insulating film 10, and the parasitic bipolar. It flows under the operating gate electrode 8 and flows from the source region 6 to the interface between the silicide layer 9 and the source region 6 which is a diffusion layer (hereinafter referred to as “silicide layer 9”).
Source diffusion layer interface), and flows to the grounded semiconductor substrate 13 through the contact 7b.

The interface between the silicide / drain diffusion layer and the interface between the silicide / source diffusion layer is extremely thin, and generates heat when a high potential is applied in a short time such as a surge, and the heat does not diffuse, possibly leading to melting. It causes junction breakdown of the transistor. Therefore, in this embodiment, the gate electrode 8 is provided with a plurality of gate electrode extension portions 8b extending from the gate electrode main body portion 8a in a comb-teeth shape, and the gate side wall insulating film 10 is formed by the comb of the gate electrode extension portion 8b. Since the silicide layer 9 is formed on the source region 6 and the drain region 5 excluding the region where the gate sidewall insulating film 10 is formed, the comb of the gate electrode extension 8b is formed. The drain region 5 and the source region 6 under the gate sidewall insulating film 10 between the teeth have a high resistance.
The resistance at the silicide / drain diffusion layer interface and the resistance at the silicide / source diffusion layer interface are connected in series to suppress electric field concentration and heat generation at the silicide / drain diffusion layer interface and the silicide / source diffusion layer interface.
The breakdown voltage can be improved.

The method of manufacturing the protection transistor 2 is as follows.
As shown in the process sectional view of FIG. 3, an isolation insulating film 14, a gate oxide film 16, a gate electrode 8, a drain region 5 and a source region 6 are formed on a semiconductor substrate 13 (FIG. 3).
After (a)), an insulating film 10a is formed on the entire surface (FIG. 3).
(B)). By performing dry etching with strong anisotropy in the vertical direction on the insulating film 10a, the gate sidewall insulating film 10 can be formed without a masking process.
(C)). Next, a silicide layer 9 is formed in a self-aligned manner in a region not covered with the insulating films (10, 14) (FIG. 3D). As a result, the silicide layer 9 is formed on the gate electrode 8 and on the source region 6 and the drain region 5 excluding the region where the gate sidewall insulating film 10 is formed.

As described above, the silicide layer 9 can be formed in a self-aligned manner using the gate side wall insulating film 10 as a mask, and the mask step is required for forming the gate side wall insulating film 10 as described above. 7, a step of forming a mask 15 for forming a pattern of the insulating film 12 serving as a mask for forming the silicide layer 9 and the like are unnecessary, and the gate electrode can be formed without increasing the number of steps. Since this can be realized by changing only the forming mask, the manufacturing cost can be reduced.

In FIG. 2, the gate electrode extension 8b is formed to extend from the gate electrode body 8a to both sides of the source region 6 and the drain region 5; Therefore, as shown in FIG. 4, by extending the gate electrode extension 8b only from the gate electrode body 8a to the drain region 5 side, the electrostatic breakdown voltage can be improved and the gate electrode 8 and The distance from the source-side contact 7b can be reduced, and the source region 6 can be reduced, so that the size of the transistor can be reduced. FIG. 4A is a plan view of a protection transistor in which a gate electrode extension 8b is provided only on the drain region 5 side, and FIG. 4B is a BB cross-sectional view thereof. However, the structure of FIG. 2 has a greater effect of improving the breakdown voltage than the structure of FIG.

The width W of each gate electrode extension 8b
_By setting the width _8b to be equal to or larger than the minimum design rule width of the gate electrode, it is possible to easily form a stable shape of the gate electrode extension 8b which is easy to manage in size and conforms to the design rule. It is known that the sheet resistance of the silicide layer 9 increases when the thin line width becomes 0.3 μm or less. In this case, the silicide layer 9 does not function as a low-resistance layer. the, if the following values plus 0.3μm to 2 times the width W ₁₀ of the gate sidewall insulating film 10, it is possible to improve the electrostatic breakdown voltage. Here, the width W ₁₀ of the gate side wall insulating film 10 refers to the gate electrode 8.
Of the gate sidewall insulating film 10 measured from the peripheral edge of the gate sidewall insulating film 10.

[0025] The distance L _R from the gate electrode main body portion 8a to the silicide layer 9, in the length of the extending direction of the gate electrode extending portions 8b, the width W ₁₀ of the gate sidewall insulating film 10 may be defined Therefore, it can be easily changed depending on the device.

[0026]

As described above, according to the present invention, since the silicide layer is formed on the source region and the drain region excluding the region where the gate sidewall insulating film is formed, the gate electrode and the gate sidewall insulating film are masked. As a result, a silicide layer can be formed on the source region and the drain region in a self-aligned manner, and a mask step or the like for forming the silicide layer is unnecessary, and the manufacturing cost can be suppressed without increasing the number of steps. . Further, a plurality of gate electrode extension portions extending in a comb-like shape from the gate electrode main body portion to the drain region side are provided on the gate electrode, and the gate sidewall insulating film is filled between the comb-like portions of the gate electrode extension portion. Formed into
Since the silicide layer is formed on the source region and the drain region excluding the region where the gate sidewall insulating film is formed, the drain region below the gate sidewall insulating film between the comb teeth of the gate electrode extension portion is formed of the silicide layer. The high resistance and the resistance at the interface between the silicide layer and the source / drain regions (silicide / diffusion layer interface) are connected in series, and the electric field concentration at the silicide / diffusion layer interface and the , Heat generation due to heat generation can be suppressed, and the breakdown voltage can be improved.

Also, by providing a plurality of gate electrode extensions on the source region side, the source region below the gate sidewall insulating film between the comb teeth of the gate electrode extension on the source region side also has a silicide layer. Thus, a high resistance region can be obtained, and the breakdown voltage can be further improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention.

FIGS. 2A and 2B are a plan view and a cross-sectional view illustrating a configuration of an electrostatic discharge protection transistor according to an embodiment of the present invention.

FIG. 3 is a process sectional view illustrating the method for manufacturing the electrostatic discharge protection transistor according to the embodiment of the present invention.

FIG. 4 is a plan view and a cross-sectional view illustrating a configuration of an electrostatic discharge protection transistor according to an embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional electrostatic discharge protection circuit.

FIG. 6 is a sectional view showing a configuration of a conventional electrostatic discharge protection transistor.

FIG. 7 is a process sectional view showing a method for manufacturing a conventional electrostatic discharge protection transistor.

[Explanation of symbols]

 Reference Signs List 1 pad 2 electrostatic breakdown protection transistor 3 protection resistor 4 internal circuit 5 drain region 6 source region 7a, 7b contact 8 gate electrode 8a gate electrode main body portion 8b gate electrode extension portion 9 silicide layer 10 gate side wall insulating film 13 semiconductor substrate

Claims (4)

[Claims] A gate insulating film disposed on a surface of a semiconductor substrate of a first conductivity type, the source region and the drain region being made of a diffusion layer of a second conductivity type, and between the source region and the drain region; A gate electrode body comprising a plurality of gate electrode extension portions formed in a comb-tooth shape from the gate electrode body portion to the drain region side; and A gate sidewall insulating film formed on a side wall of the gate electrode and filling in a comb-like shape of the gate electrode extending portion; and a region formed on the source region and the drain region except for a region where the gate sidewall insulating film is formed. ESD protection transistor having a silicide layer formed thereon. 2. The electrostatic discharge protection transistor according to claim 1, wherein a plurality of gate electrode extensions are provided also on the source region side. 3. The electrostatic discharge protection transistor according to claim 1, wherein the width of each gate electrode extension is equal to or larger than the minimum design rule width of the gate electrode. 4. The electrostatic discharge protection transistor according to claim 1, wherein the interval between the gate electrode extending portions is set to be equal to or less than a value obtained by adding 0.3 μm to twice the width of the gate side wall insulating film.