JP2007059565A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having an improved breakdown voltage characteristic, and a manufacturing method thereof. <P>SOLUTION: This semiconductor device 1 comprises a semiconductor substrate 11, a pair of low concentration diffusion regions 17s and 17d formed in the surface of the semiconductor substrate 11, a gate insulating film 13 formed on the surface of the semiconductor substrate 11, and a gate electrode 15 formed on the surface of the semiconductor substrate 11 via the gate insulating film 13. The side face on the drain (17d) side of the gate electrode 15 has interdigital electrodes 15a including a first side face parallel to the gate widthwise direction, a second side face projecting in the gate lengthwise direction from the first side face, and third side faces connecting the first side face and the second side face at both ends of the second side face. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device suitable for application to an output transistor that requires a relatively high breakdown voltage characteristic and a manufacturing method thereof.

  Conventionally, an electronic device or the like is provided with an output circuit for driving a potential of an output line. In general, this output circuit includes a transistor provided in an output stage. Hereinafter, a transistor provided in the output stage is referred to as an output transistor.

  Usually, a structure having a high withstand voltage characteristic is applied to the output transistor as compared with, for example, a normal transistor incorporated in an internal circuit or the like. Such a transistor is hereinafter referred to as a high voltage transistor. The structure of a high voltage transistor according to the prior art is disclosed in, for example, Patent Document 1 shown below.

  Here, the configuration of the high voltage transistor 900 will be described with reference to FIGS. FIG. 1 is a top view showing the configuration of the high voltage transistor 900. FIG. 2 is a diagram showing the structure of the i-i ′ cross section in FIG. 1.

  As shown in FIGS. 1 and 2, the high voltage transistor 900 according to the prior art has an active region (also referred to as an element formation region) AR and a field region (also referred to as an element isolation region) FR defined by an element isolation insulating film 912. The semiconductor substrate 911 is provided. A pair of source region 917 s and drain region 917 d are formed in the active region AR in the semiconductor substrate 911 by diffusing predetermined impurities. A gate insulating film 913 is formed over a region sandwiched between the source region 917 s and the drain region 917 d, and a gate electrode 915 is formed over the gate insulating film 913. A region sandwiched between the source region 917 s and the drain region 917 d functions as a region where a channel is formed (hereinafter referred to as a channel formation region 916).

  The source region 917 s and the drain region 917 d each have a region overlapping with the gate electrode 915. In this description, this overlapping region is referred to as an overlap region. By having such an overlap region, the output transistor 900 can be reliably turned on or off during driving.

Further, an interlayer insulating film 921 is formed on the semiconductor substrate 911 in which the above-described configuration is formed. The interlayer insulating film 921 has contact holes that expose portions of the upper surfaces of the source region 917s and the drain region 917d. On the interlayer insulating film 921, a source electrode 923s and a drain electrode 923d, which are wiring layers that form electrical connections with other elements, are formed. The source electrode 923s and the drain electrode 923d are electrically connected to the source region 917s and the drain region 917d through contact wirings 922s and 922d filled in the contact holes, respectively.
JP-A-9-260504

  However, in the configuration as described above, as shown in FIG. 3, the impurity doped in the source region 917s and the drain region 917d diffuses, and the impurity at the boundary portion with the non-diffusion region is shown as an arrow in FIG. It will flow out in the direction. For this reason, as shown in FIGS. 4A and 4B, the impurity concentration at the boundary portion decreases as it goes toward the channel formation region 916 side in the semiconductor substrate 911. When the impurity concentration is thus reduced, when a voltage is applied, as shown in FIGS. 5A and 5B, the energy level Ec at the lower end of the conduction band and the energy level Ev at the upper end of the valence band in the vicinity of the surface of the semiconductor substrate 911. In this case, the depletion layer easily extends in the substrate thickness direction.

  3 is an enlarged view of the region o1 in FIG. 1, and the broken lines L1, L2, and L3 in FIG. 3 are lines that connect the same density (this is referred to as an equal density line). 4A is a graph showing the impurity concentration along the line ii-ii ′ in FIG. 3, and FIG. 4B is a graph showing the impurity concentration along the line iii-iii ′ in FIG. is there. 5A is an energy band diagram at a position P1 (corresponding to a corner a described later) on the line ii-iii ′ in FIG. 3, and FIG. 5B is on the line iii-iii ′ in FIG. It is an energy band figure in position P2 (corresponding to the middle part b in the later description). In FIGS. 5A and 5B, Ef represents the Fermi level. The position P1 is a region where the end of the source region 971s or the drain region 917d and the end of the gate electrode 915 overlap, and the position P2 is the source region 971s or the drain region 917d and the gate electrode 915 are the source region 917s or the drain region. This is an overlapping area other than the end of 917d.

  In the above, particularly in a region where the end of the source region 917 s or the drain region 917 d and the end of the gate electrode 915 intersect (this is referred to as a corner portion a, see FIGS. 1 to 3), there are many portions adjacent to the non-diffusion region. Therefore, for example, as compared with a region where the source region 917s or drain region 917d and the gate electrode 915 overlap except at the end of the source region 917s or drain region 917d (this is referred to as a middle portion b), it diffuses from the periphery and enters. There are few impurities coming. For this reason, as is clear when FIG. 4 (a) is compared with FIG. 4 (b), the impurity concentration at the corner a (see FIG. 4 (a)) is the impurity concentration at the middle part b (FIG. 4 (b)). Compared with reference) Therefore, as is clear when FIG. 5A is compared with FIG. 5B, the depletion layer becomes easier to extend in the substrate thickness direction at the corner portion a than at the middle portion b.

For example, at the position P1 (corresponding to the corner part a) and the position P2 (corresponding to the middle part b) shown in FIGS. 4A and 4B, the impurity concentration at the position P1 is about ½ of the impurity concentration at the position P2. It has become. Here, the impurity concentration at position P1 is 0.5 × 10 ¹⁵ / cm ³ , the impurity concentration at position P2 is 1.0 × 10 ¹⁵ / cm ^3, and a silicon substrate is used as the semiconductor substrate 911. When the impurity concentration of the p-type well region at 911 is 1 × 10 ¹⁴ / cm ³ , the voltage applied to the gate is 20 V (volts), and the temperature is room temperature (300 K), the width of the depletion layer at position P2 is 12 Whereas the width of the depletion layer at the position P1 is about 13.0 μm. In this case, the diffusion potential is about 0.66V.

  The end portion of the gate electrode 915 is a portion where electric lines of force are concentrated due to a current input from the drain region 917d side, for example. For this reason, an electric field stronger than that in the middle part b is generated, and the equipotential surface of the semiconductor substrate 911 under this is dense. In particular, since a strong electric field is generated in the corner portion of the gate electrode 915 as compared with the other end portions, an equipotential surface in an emergency is very dense below this.

  As described above, at the corners a of the source region 917s and the drain region 917d, the impurity concentration is reduced and a strong electric field is generated. For this reason, the deep depletion layer D will be formed in a wide range compared with the middle part b. That is, as shown in FIGS. 6A and 6B, the depletion layer D at the corner a (see a in FIG. 6A) is depleted at the middle part b (see b in FIG. 6B). Compared to the reference), it tends to extend in the horizontal direction toward the inside of the source region 917s or the drain region 917d. 6A shows the configuration of the depletion layer D in the section along the line ii-ii ′ in FIG. 3, and FIG. 6B shows the depletion layer in the section along the line iii-iii ′ in FIG. The structure of D is shown.

Thus, at the corner portion a where the depletion layer D extends, the capacity per unit area of the depletion layer (referred to as depletion layer capacity or barrier capacity) tends to be small. For this reason, the high breakdown voltage transistor 900 is easily broken down. As shown in FIG. 7, when the surge current is input, the current flows in the corner portion a that is easily broken down. Therefore, the current I _a flowing through the corner a is exceeds the easily broken current I _1, a result, the corner portion a is disrupted by such heat generated by this current, the high voltage transistor 900 is damaged The problem to say occurs. Note that the breakdown current I ₁ indicates a current when the transistor is broken. In addition, the voltage at this time that the breakdown voltage V _1.

  Further, in Patent Document 1 described above, the gate length at the end of the transistor is configured to be longer than the gate length at the middle of the transistor, thereby preventing surge current from concentrating on the end of the transistor. is doing. However, even in such a configuration, a path through which a large current flows in the middle part of the transistor compared to the current flowing between the drain and the source is formed in the corner part (end part of the transistor), so that the withstand voltage characteristic is sufficient. It was difficult to improve.

  Accordingly, the present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device having improved withstand voltage characteristics and a method for manufacturing the same.

  In order to achieve such an object, a semiconductor device according to the present invention includes a semiconductor substrate, a pair of diffusion regions formed on the surface of the semiconductor substrate, a gate insulating film formed on the surface of the semiconductor substrate, and gate insulation on the surface of the semiconductor substrate. A first side surface formed through a film, at least one side surface being parallel to the gate width direction, a second side surface projecting in the gate length direction from the first side surface, and the first side surface at both ends of the second side surface A third side surface connecting the second side surface and a gate electrode connected to the signal line.

  As described above, the present invention includes a pair of first diffusion regions (for example, a low concentration diffusion region) and a second diffusion region (for example, a high concentration diffusion region) having a higher impurity diffusion concentration than that of the first diffusion region. In a semiconductor device having a withstand voltage characteristic with respect to voltage, at least one side surface of the gate electrode has a first side surface parallel to the gate width direction, a second side surface protruding in the gate length direction from the first side surface, and a first side surface And a third side surface connecting the second side surface. That is, the side surface of the gate electrode has an uneven shape. As a result, for example, when a relatively large current such as a surge current is input from the first diffusion region on the side surface having the concavo-convex shape, the location where the electric field is concentrated can be dispersed in the corners of the concavo-convex shape. Therefore, the strength of the electric field generated at one corner can be reduced, and the current flowing in the depletion layer formed under each corner can be reduced. In addition, by increasing the number of corners of the gate electrode in this way, it is possible to increase the number of paths through which current concentrates, so that the amount of current passing through one path can be reduced. . From these, according to the present invention, it is possible to reduce the amount of current that flows in a concentrated manner when a relatively large current such as a surge current is input, so that the breakdown voltage characteristics of the semiconductor device can be improved. Achieved.

  According to the present invention, it is possible to realize a semiconductor device with improved breakdown voltage characteristics and a method for manufacturing the same.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  First, Embodiment 1 according to the present invention will be described in detail with reference to the drawings. In the following description, a semiconductor device 1 suitable for use as an output transistor that requires a relatively high breakdown voltage is taken as an example.

〔Constitution〕
FIG. 8 is a top view showing the configuration of the semiconductor device 1 according to this embodiment. FIG. 9 is a diagram showing the structure of the II ′ section in FIG. 8, and FIG. 10 is the diagram showing the structure of the II-II ′ section in FIG. 8.

  As shown in FIGS. 8 to 10, the semiconductor device 1 includes a semiconductor substrate 11, an element isolation insulating film 12 formed on the semiconductor substrate 11, a gate insulating film 13 formed on the semiconductor substrate 11, and gate insulation. A gate electrode 15 formed on the film 13, a pair of low concentration diffusion regions (first diffusion regions) 17s and 17d sandwiching a region under the gate electrode 15 in the semiconductor substrate 11, and the surfaces of the low concentration diffusion regions 17s and 17d And high concentration diffusion regions (second diffusion regions) 18s and 18d formed respectively. A region sandwiched between the low concentration diffusion regions 17s and 17d, that is, a region under the gate electrode 15 in the semiconductor substrate 11 functions as a region where a channel is formed (channel formation region 16).

  Further, on the semiconductor substrate 11 in which the above-described configuration is formed, an interlayer insulating film 21 having a contact hole exposing the surfaces of the high concentration diffusion regions 18s and 18d, and a contact filled inside the contact hole, respectively. Wirings 22 s and 22 d, and source electrode 23 s and drain electrode 23 d formed on interlayer insulating film 21 are included. However, in FIG. 8, in order to clarify the configuration of the semiconductor device 1, the configurations of the interlayer insulating film 21, the contact wirings 22s and 22d, the source electrode 23s, and the drain electrode 23d are omitted.

  In the above configuration, for example, a silicon substrate doped with n-type impurities (hereinafter referred to as an n-type silicon substrate) is used as the semiconductor substrate 11. However, the present invention is not limited to this, and various modifications can be made as necessary, such as a silicon substrate doped with p-type impurities (p-type silicon substrate).

The element isolation insulating film 12 is a film (LOCOS film) formed by, for example, a LOCOS (Local Oxidation of Silicon) method. This can be, for example, a silicon oxide film (SiO ₂ ). However, the present invention is not limited to this, and an insulating film formed by another method such as an STI (Shallow Trench Isolation) method may be used. The element isolation insulating film 12 defines an active region AR and a field region FR in the semiconductor substrate 11.

The gate insulating film 13 is formed on a region that divides the active region AR in the semiconductor substrate 11 into two, and electrically floats a gate electrode 15 described later with respect to the semiconductor substrate 11. This gate insulating film 13 is, for example, a silicon oxide film (SiO ₂ ) formed on the active region AR by thermally oxidizing the surface of the semiconductor substrate 11. The film thickness can be, for example, 100 mm (angstrom).

  The gate electrode 15 formed on the gate insulating film 13 is a polysilicon (poly-silicon) film containing a predetermined impurity, for example. The film thickness can be, for example, 5000 mm. Further, the gate electrode 15 according to the present embodiment has comb-like uneven portions (comb-like electrode portions 15a) on the side surface on the drain side. The comb-like electrode portion 15a will be described later.

The low concentration diffusion regions 17 s and 17 d are impurity diffusion regions formed in a pair of regions sandwiching a region under the gate electrode 15 in the semiconductor substrate 11. The low concentration diffusion regions 17s and 17d function as a source (17s) and a drain (17d), respectively. For example, when the semiconductor device 1 is a transistor that forms a p-type channel, the low-concentration diffusion regions 17s and 17d can be formed by implanting a p-type impurity, for example, boron (B) ions. The dose amount can be, for example, about 1 × 10 ¹² to 1 × 10 ¹⁴ / cm ² . When the semiconductor device 1 is a transistor that forms an n-type channel, the low-concentration diffusion regions 17s and 17d can be formed by implanting an n-type impurity such as phosphorus (P) ions. The dose amount can be, for example, about 1 × 10 ¹² to 1 × 10 ¹⁴ / cm ² .

  Further, the low-concentration diffusion regions 17s and 17d functioning as the source / drain regions each have a region overlapping with the gate electrode 15, that is, an overlap region, as shown in FIGS. For example, when the width of the channel formation region 16 in the gate length direction is about 1.5 μm and the width of the gate electrode 15 in the channel length direction is about 3.5 μm, the width of the overlap region in the gate length direction is about 1 μm. It becomes. By providing such an overlap region, the semiconductor device 1 is reliably turned on or off during driving.

  In the active region AR, a region sandwiched between the low concentration diffusion regions 17 s and 17 d and under the gate electrode 15 functions as a channel formation region 16. In the semiconductor substrate 11 having a well structure, this region is doped with a predetermined impurity.

The high-concentration diffusion regions 18s and 18d formed on the surfaces of the low-concentration diffusion regions 17s and 17d are conductive regions for making ohmic contact with the in-contact wirings 22s and 22d, which will be described later. For example, when the semiconductor device 1 is a transistor that forms a p-type channel, the high-concentration diffusion regions 18s and 18d can be formed by implanting p-type impurities such as boron (B) ions. The dose amount can be, for example, about 1 × 10 ¹⁵ / cm ² . When the semiconductor device 1 is a transistor that forms an n-type channel, the high-concentration diffusion regions 18s and 18d can be formed by implanting n-type impurities such as phosphorus (P) ions. The dose amount can be, for example, about 1 × 10 ¹⁵ / cm ² .

  Further, as shown in FIGS. 8 to 10 and the above description, the semiconductor device 1 according to the present embodiment has a comb-like uneven portion (comb-like shape) on the side surface of the gate electrode 15 on the drain (low concentration diffusion region 17d) side. Electrode part 15a). The comb-like electrode portion 15a is formed integrally with the gate electrode 15, and is periodically arranged on the side surface of the gate electrode 15 on the drain (17d) side along the channel width direction. The comb-like electrode portion 15a is configured to increase the number of locations where the electric field formed when current is input is concentrated. By dispersing the places where the electric field concentrates in this way, it is possible to increase the paths through which the current input from the drain (17s) side flows. Here, the relationship between the period in which the comb-like electrode portion 15a is formed and the spread of the depletion layer will be described with reference to FIG. FIG. 11 is an enlarged view of a region o2 in FIG.

  As shown in FIG. 11, each comb-like electrode portion 15a includes a first side surface S11 parallel to the gate width direction, a second side surface S12 protruding in the gate length direction from the first side surface S11, and a second side surface. It has a concavo-convex shape including a third side surface S13 connecting the first side surface S11 and the second side surface S12 at both ends of S12, and has a length d4 of the third side surface S13 and a length d3 of the second side surface S12. Is formed. Further, the interval between the comb-like electrode portions 15a adjacent in the gate width direction (the length of the first side surface S11) is set to d2. In the following description, the length in the gate length direction is referred to as length d4, the length in the gate width direction is referred to as width d3, and the interval between the comb-like electrode portions 15a along the gate width is referred to as interval d2. .

  In this configuration, for example, when a current is input from the drain (17d) side, electric lines of force are formed at the corners C1 and C2 of the comb-shaped electrode portion 15a, thereby forming other portions (for example, comb teeth). A strong electric field is formed as compared with the inner electrode portion of the electrode portion 15a. For this reason, in the region B1 or B2 (see FIG. 8) below the corner C1 or C2, a large current is channeled from the drain (17d) side as compared with the filling portion in the gate electrode 15 and the comb-like electrode portion 15a. It flows to the source (17s) through the formation region 16. In other words, a larger number of paths through which a relatively large current flows (referred to as current paths) are formed according to the number of corners C1 and C2 than in the prior art.

By increasing the current path when the surge current is input in this way, the current I _a that has been concentrated in the region a below the corners of the source region 917 s and the drain region 917 d can be converted into a comb-like electrode. Since it is possible to disperse the regions B1 and B2 below the corners C1 and C2 of the portion 15a, it is possible to reduce the currents I _A , I _B1 and I _B2 flowing through the individual regions A, B1 and B2. Become.

Here, currents I _A , I _B1, and I _B2 flowing through the individual regions A, B1, and B2 are shown in FIG. As shown in FIG. 12, by increasing the current path, current flows in a distributed manner in each current path, so that straight lines indicating the currents I _A , I _B1 and I _B2 flowing in the individual regions A, B1 and B2 are obtained. , it shifted to the right side from the straight line indicating the current I _a in the conventional. That is, the current flowing at the same voltage is I ₂ lower than I ₁ and the breakdown voltage is V ₂ or V ₃ higher than V ₁ . Note that the slopes of the straight lines indicating the currents I _A , I _B1 and I _B2 flowing through the individual regions A, B1 and B2 are the gate width, the number of convex portions of the comb-like electrode portion 15a, and the area of the overlap region. Therefore, detailed description will be omitted individually.

Thus, by increasing the current path when the surge current is input, the current flowing through each of the regions A, B1, and B2 can be reduced. As a result, the withstand voltage characteristics of the semiconductor device 1 are improved. It becomes possible to improve. In this embodiment, when the currents flowing in the regions A, B1, and B2 are equal (I _A = I _B1 = I _B2 ), the configuration is ideal. That is, it is possible to improve the breakdown voltage characteristics of the semiconductor device 1 most by distributing the current evenly in the regions A, B1 and B2. In this case, for example, assuming that the current input to the drain (17d) side is I and the number of convex portions of the comb-like electrode portion 15a is n, two regions B1 and B2 are formed for each convex portion. Therefore, the currents flowing in the individual regions A, B1, and B2 are I _A = I _B1 = I _B2 = I / (2 + 4n). This is a very small current compared to the current Ia = I / 2 flowing in the region a when the comb-like electrode portion 15a is not provided.

  In the present embodiment, as shown in FIG. 11, for example, when a current of a certain value is input, the horizontal width (hereinafter referred to as the depletion layer D formed in the region B1 or B2 below the corner C1 or C2). (Where the spread of the depletion layer D) is d1, the length d4, the width d3 and the interval d2 of the comb-shaped electrode portion 15a are set to be larger than twice the spread d1 of the depletion layer D, respectively. Is done.

  In this way, by setting the length d4, the width d3, and the interval d2 of the comb-shaped electrode portion 15a to values wider than the spread d1 of the depletion layer D formed in the region B1 or B2, respectively. It can be avoided that the depletion layer D formed in B1 / B2 and the depletion layer D formed in the adjacent region B1 / B2 are combined with each other. As a result, an expected number of current paths (an increase due to the number of corners C1 and C2) can be reliably formed, and the current flowing through one current path can be reliably reduced.

More specifically, for example, the impurity concentration of the low-concentration diffusion regions (source region and drain region) 17s and 17d is 1.0 × 10 ¹⁵ / cm ³ , a silicon substrate is used as the semiconductor substrate 11, and this semiconductor substrate 11, the impurity concentration of the n-type well region is 1 × 10 ¹⁴ / cm ³ , the potential at the corner c of the comb-like electrode portion 15 a is 20 V (volts), and the temperature is room temperature (300 K). The spread d1 in the horizontal direction of the depletion layer D formed under the part c is about 17.3 μm. In this case, the diffusion potential is about 0.66V. Therefore, the length d4, the width d3, and the interval d2 of the comb-like electrode portion 15a according to the present embodiment are set to be twice or more of about 17.3 μm, that is, about 34.6 μm or more.

  Further, as described above, the mask shape when forming the gate electrode 15 including the comb-shaped electrode portion 15a by periodically arranging the comb-shaped electrode portions 15a at predetermined intervals along the channel width direction. Can be simplified, and the number of current paths can be increased according to twice the increase in channel width. As a result, the semiconductor device 1 can have a breakdown voltage characteristic depending on the channel width. In other words, the breakdown voltage characteristic of the semiconductor device 1 can be made W-dependent. Note that W is a channel width.

  In addition, an interlayer insulating film 21 is formed on the semiconductor substrate 11 on which the above-described configuration is formed. The interlayer insulating film 21 has contact holes that expose portions of the upper surfaces of the high concentration diffusion regions 18s and 18d. On the interlayer insulating film 21, a source electrode 23s and a drain electrode 23d, which are wiring layers constituting electrical connection with other elements, are respectively formed. The source electrode 23s and the drain electrode 23d are electrically connected to the high-concentration diffusion regions 18s and 18d through contact wirings 22s and 22d filled in the contact holes, respectively.

〔Production method〕
Next, a method for manufacturing the semiconductor device 1 according to this embodiment will be described with reference to the drawings. 13 to 15 are process diagrams showing a method for manufacturing the semiconductor device 1. In the following, description will be made based on the structure corresponding to the section II-II ′ in FIG.

  In the manufacturing method of the semiconductor device 1, first, a silicon oxide film 12 a that is a buffer film is formed on the semiconductor substrate 11 by, for example, thermal oxidation, and then a silicon oxide film is formed by, for example, a CVD (Chemical Vapor Deposition) method. A silicon nitride film 12b, which is a protective film against thermal oxidation, is formed on 12a. Next, the silicon nitride film 12b is patterned using an existing photolithography method and etching method. When the silicon nitride film 12b is patterned in this way, the surface of the semiconductor substrate 11 is thermally oxidized using the patterned silicon nitride film 12b as a mask, so that an element isolation insulating film that is a LOCOS film is formed as shown in FIG. A film 12 is formed on the semiconductor substrate 11. In this case, the thermal oxidation conditions may be, for example, that the atmosphere in the oven is an oxygen / hydrogen atmosphere, the heating temperature is 1000 ° C., and the heating time is 100 minutes. Thereby, for example, the element isolation insulating film 12 having a film thickness of 5000 mm can be formed. Further, after forming the element isolation insulating film 12, the silicon nitride film 12b is removed under predetermined etching conditions.

Next, by using an existing photolithography method, a resist R1 is formed on a region where the gate electrode 15 is formed in a later step. Subsequently, predetermined impurities are implanted into the active region AR in the semiconductor substrate 11 using the resist R1 and the element isolation insulating film 12 as a mask. Thereafter, the implanted predetermined impurities are thermally diffused to form the low concentration diffusion regions 17s and 17d as shown in FIG. 13B. As a condition at this time, for example, when the semiconductor device 1 manufactures a semiconductor device 1 in which a p-type channel is formed, for example, boron (B) ions are used as a predetermined impurity, and the acceleration is, for example, 500 keV (kiloelectron volts). ), The dose amount may be, for example, about 1 × 10 ¹² to 1 × 10 ¹⁴ / cm ^2, and the heating temperature during thermal diffusion may be 1000 ° C. For example, when manufacturing the semiconductor device 1 in which an n-type channel is formed, for example, phosphorus (P) ions are used as the predetermined impurity, the acceleration is set to, for example, about 500 keV (kiloelectron volts), and the dose amount is set to, for example, It can be set to about 1 × 10 ¹² to 1 × 10 ¹⁴ / cm ² . The resist R1 is removed after the low concentration diffusion regions 17s and 17d are formed.

  Next, for example, by thermal oxidation, a silicon oxide film 13A having a thickness of, for example, 100 mm is formed on the surface of the semiconductor substrate 11 on which the low concentration diffusion regions 17s and 17d are formed as shown in FIG. . The thermal oxidation conditions at this time may be, for example, that the atmosphere in the oven is an oxygen / hydrogen atmosphere, the heating temperature is 850 ° C., and the heating time is 20 minutes.

  Next, a polysilicon film 15A containing a predetermined impurity and having a thickness of 5000 mm is formed on the silicon oxide film 13A by, eg, CVD or sputtering. Thereby, a cross-sectional structure as shown in FIG.

  Next, by using an existing photolithography method, as shown in FIG. 14B, a resist R2 having a pattern of the gate electrode 15 including the shape of the comb-like electrode portion 15a is formed on the polysilicon film 15A. Form. The pattern of the gate electrode 15 including the comb-like electrode portion 15a is as shown in FIG.

Subsequently, by etching the polysilicon film 15A and the silicon oxide film 13A using the resist R2 as a mask by an existing etching method, the gate electrode 15 and the semiconductor substrate 11 are formed on the semiconductor substrate 11 as shown in FIG. The gate insulating film 13 is sequentially formed, and the surfaces of the low concentration diffusion regions (source region and drain region) 17s and 17d in the active region AR (excluding the overlap region) are exposed. The etching at this time may be dry etching or wet etching. For example, when dry etching is used for etching the polysilicon film 15A, the condition is that a mixed gas having a mixing ratio of Cl ₂ : HBr ₃ : O ₂ = 100: 100: 2 to 4 is used as an etching gas. be able to. For example, when dry etching is used for etching the silicon oxide film 13A, the condition can be, for example, a mixed gas having a mixing ratio of CF ₄ / CHF ₃ = 1: 10.

Next, by using an existing photolithography method, a resist R3 having an opening exposing a part of the surface of the low concentration diffusion regions 17s and 17d is formed, and a predetermined impurity is implanted by using the resist R3 as a mask. As shown in FIG. 15B, the high concentration diffusion regions 18s and 18d are formed on at least a part of the surface of the low concentration diffusion regions 17s and 17d. As a condition at this time, for example, when the semiconductor device 1 manufactures the semiconductor device 1 in which a p-type channel is formed, for example, boron (B) ions are used as a predetermined impurity, and the acceleration is set to, for example, 50 keV (kiloelectron volts). ) And the dose can be set to about 1 × 10 ¹⁵ / cm ^2, for example. For example, when manufacturing the semiconductor device 1 in which an n-type channel is formed, for example, phosphorus (P) ions are used as the predetermined impurities, the acceleration is set to, for example, about 50 keV (kiloelectron volts), and the dose amount is set to, for example, It can be about 1 × 10 ¹⁵ / cm ² . The resist R3 is removed after the high concentration diffusion regions 18s and 18d are formed.

  Thereafter, an interlayer insulating film 21 is formed by depositing silicon oxide on the semiconductor substrate 11 in which the above-described configuration is formed, to such an extent that it is buried. Next, an opening that exposes the upper surfaces of the high-concentration diffusion regions 18s and 18d is formed in the interlayer insulating film 21 using an existing photolithography method and etching method, and this is filled with a conductor such as tungsten (W). Thus, the in-contact wirings 22s and 22d are formed. Next, a conductor is deposited on the interlayer insulating film 21 and patterned to form the source electrode 23s and the drain electrode 23d. Thereby, the semiconductor device 1 having a cross-sectional structure as shown in FIGS. 8 to 10 is manufactured.

[Function and effect]
As described above, the semiconductor device 1 according to this embodiment includes the semiconductor substrate 11, the pair of low concentration diffusion regions 17s and 17d formed on the surface of the semiconductor substrate 11, and at least the surfaces of the pair of low concentration diffusion regions 17s and 17d. High-concentration diffusion regions 18s and 18d that are partially formed and have a higher impurity concentration than the pair of low-concentration diffusion regions 17s and 17d, and regions sandwiched between the pair of low-concentration diffusion regions 17s and 17d on the surface of the semiconductor substrate 11 The gate insulating film 13 formed thereon, the first side surface S11 formed on the gate insulating film 13, the side surface on the drain (17d) side being parallel to the gate width direction, and the gate length direction more than the first side surface S11 And a third side surface S13 connecting the first side surface S11 and the second side surface S12 at both ends of the second side surface S12. Constructed and a over gate electrode 15.

  As described above, this embodiment includes a pair of low-concentration diffusion regions 17s and 17d and high-concentration diffusion regions 18s and 18d having a higher impurity diffusion concentration, thereby providing a semiconductor having a breakdown voltage characteristic with respect to a relatively high voltage. In the device 1, the side surface on the drain (17d) side of the gate electrode 15 has a first side surface S11 parallel to the gate width direction, a second side surface S12 projecting in the gate length direction from the first side surface S11, and a first side surface. It includes a third side surface S13 connecting S11 and the second side surface S12. That is, the side surface of the gate electrode 15 has a comb-like electrode portion 15a having an uneven shape. Thereby, for example, when a relatively large current such as a surge current is input from the low concentration diffusion region 17d on the drain (17d) side having the comb-like electrode portion 15a, the portion where the electric field is concentrated is formed in an uneven shape. Therefore, it is possible to reduce the intensity of the electric field generated at one corner and reduce the current flowing through the depletion layer formed below each corner. In addition, by increasing the number of corners of the gate electrode in this way, it is possible to increase the number of paths through which current concentrates, so that the amount of current passing through one path can be reduced. . From these, according to the present embodiment, it is possible to reduce the amount of current that flows in a concentrated manner when a relatively large current such as a surge current is input, so that the breakdown voltage characteristics of the semiconductor device 1 are improved. Is achieved.

[Application form]
FIG. 16 shows the configuration of an electronic circuit 100 configured using the semiconductor device 1 according to this embodiment. As shown in FIG. 16, the electronic circuit 100 includes an output circuit 101 and an internal circuit 102. The output circuit 101 includes a p-type output transistor P1 connected between a terminal to which an output power supply voltage is applied (output VDD) and the output terminal, and a terminal grounded to the output terminal (output GND). And an n-type output transistor N1 provided therebetween. The output transistors P1 and N1 are each formed on a predetermined semiconductor substrate using the structure of the semiconductor device 1 according to the present embodiment.

  With the above configuration, an output circuit with improved resistance to ESD and the like and an electronic device having the output circuit can be realized.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as that of the first embodiment.
〔Constitution〕
FIG. 17 is a top view showing the configuration of the semiconductor device 2 according to this embodiment. 18 is a diagram showing the structure of the III-III ′ section in FIG. 17, and FIG. 19 is the diagram showing the structure of the IV-IV ′ section in FIG.

  As shown in FIGS. 17 to 19, in the semiconductor device 2, the gate electrode 15 and the gate insulating film 13 are replaced with the gate electrode 25 and the gate insulating film 23, respectively, in the same configuration as that of the semiconductor device 1 according to the first embodiment. It has the structure which was made.

  Similarly to the gate electrode 15, the gate electrode 25 has a comb-like electrode portion 15a formed along the side surface on the drain (17d) side and a comb-like electrode portion along the side surface on the source (17s) side. 25b is formed.

  The length, width and interval of the comb-shaped electrode portion 25b are the same as the length d4, width d3 and interval d2 of the comb-shaped electrode portion 15a, respectively. However, it is preferable that the convex portion in the comb-shaped electrode portion 15a and the convex portion in the comb-shaped electrode portion 25b are configured not to overlap in the gate length direction. Thereby, it is possible to prevent the gate length from being locally increased to such an extent that the characteristics of the transistor are deteriorated, and it is possible to prevent the operation characteristics and the breakdown voltage characteristics from being significantly changed. In this case, the interval d2 is set equal to or larger than the width d3.

Thus, by providing the comb-like electrode portion 25b not only on the drain (17d) side but also on the source (17s) side, the current flowing to the source (17s) side can be supplied not only to the corner portion A but also to the source ( The currents I _B3 and I _B4 can also be dispersed in the regions B3 and B4 below the corners of the comb-like electrode portion 25b on the 17s) side. As a result, it is possible to prevent current from concentrating on the corner A on the source (17 s) side, and to further improve the breakdown voltage characteristics of the semiconductor device 2.

  Further, with this configuration, for example, even when a surge current is input from the source (17s) side, the concentration points of the electric field can be dispersed as in the case where the surge current is input from the drain (17d) side. Become. As a result, it is possible to improve the breakdown voltage characteristics when a surge current is input from the source (17s) side.

  Such a gate electrode 25 can be formed of the same material and film thickness as the gate electrode 15 according to the first embodiment. The gate insulating film 23 has an upper surface having the same shape as the gate electrode 25. The gate insulating film 23 can be made of the same material and film thickness as the gate insulating film 13 according to the first embodiment.

  Since the other configuration is the same as that of the semiconductor device 1 according to the first embodiment as described above, detailed description thereof is omitted here.

〔Production method〕
In addition, the manufacturing method of the semiconductor device 2 according to the present embodiment is the same as the manufacturing method of the semiconductor device 1 according to the first embodiment, and thus detailed description thereof is omitted here. However, in this embodiment, the resist R2 in FIG. 14B is formed in a pattern including not only the gate electrode 25 shown in FIG. 17, that is, the comb-shaped electrode portion 15a but also the comb-shaped electrode portion 25b. Therefore, the gate electrode 15 and the gate insulating film 13 are replaced with the gate electrode 25 and the gate insulating film 23, respectively, in the steps after FIG.

[Function and effect]
As described above, the semiconductor device 2 according to this embodiment includes the semiconductor substrate 11, the pair of low concentration diffusion regions 17s and 17d formed on the surface of the semiconductor substrate 11, and at least the surfaces of the pair of low concentration diffusion regions 17s and 17d. High-concentration diffusion regions 18s and 18d that are partially formed and have a higher impurity concentration than the pair of low-concentration diffusion regions 17s and 17d, and regions sandwiched between the pair of low-concentration diffusion regions 17s and 17d on the surface of the semiconductor substrate 11 A gate insulating film 23 formed on the gate insulating film 23; a first side surface S11 formed on the gate insulating film 23; both side surfaces on the drain (17d) side and the source (17s) side are parallel to the gate width direction; A second side S12 projecting in the gate length direction from the first side S11 at both ends of the two side S12, a first side S11 and a second side S12; Constructed and a gate electrode 25 comprising a third side surface S13 connecting.

  As described above, this embodiment includes a pair of low-concentration diffusion regions 17s and 17d and high-concentration diffusion regions 18s and 18d having a higher impurity diffusion concentration, thereby providing a semiconductor having a breakdown voltage characteristic with respect to a relatively high voltage. In the device 2, the side surfaces of the gate electrode 25 on the drain (17d) side and the source (17s) side are respectively the first side surface S11 parallel to the gate width direction and the second side surface protruding in the gate length direction from the first side surface S11. It includes a side surface S12 and a third side surface S13 connecting the first side surface S11 and the second side surface S12. That is, the both side surfaces of the gate electrode 25 have comb-like electrode portions 15a and 25b having an uneven shape. Thus, for example, when a relatively large current such as a surge current is input from the low concentration diffusion region 17d or 17s on the drain (17d) side or the source (17s) side, a portion where the electric field is concentrated is formed in an uneven shape. Therefore, it is possible to reduce the intensity of the electric field generated at one corner and reduce the current flowing through the depletion layer formed below each corner. In addition, by increasing the number of corners of the gate electrode in this way, it is possible to increase the number of paths through which current concentrates, so that the amount of current passing through one path can be reduced. . From these, according to the present embodiment, it is possible to reduce the amount of current that flows in a concentrated manner when a relatively large current such as a surge current is input, so that the breakdown voltage characteristics of the semiconductor device 2 are improved. Is achieved.

[Application form]
Further, the configuration of the electronic circuit configured using the semiconductor device 2 according to the present embodiment is the same as that described with reference to FIG. 16 in the first embodiment, and thus detailed description thereof is omitted here.

  In this embodiment, the convex comb-like electrode portions 15a and 25b are alternately provided on the source (17s) side and the drain (17d) side to prevent the gate length from becoming locally long. However, the present invention is not limited to this, and for example, as shown in FIG. 20, the gate electrode 25 ′ may be configured to meander in a rectangular shape. In this case, in order to meander the channel formation region 16 ′ in the gate electrode 25 ′ along the gate electrode 25 ′, the low-concentration diffusion regions 17s ′ and 17d ′ are alternately projected to the opposing regions 27s ′ and 27d ', and the distance between the low-concentration diffusion regions 17s' and 17d ', that is, the length of the channel formation region 16' is equal in any part. Thereby, as shown in FIG. 20, a channel forming region 16 'meandering along the gate electrode 25' is disposed. With such a configuration, it is possible to make the gate length uniform, and thus it is possible to prevent the operation characteristics and breakdown voltage characteristics of the transistor from changing significantly. Note that the gate insulating film under the gate electrode 25 ′ has a shape meandering in a rectangular shape, like the gate electrode 25 ′.

  Next, Example 3 of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first embodiment or the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as that of the first embodiment or the second embodiment.

〔Constitution〕
FIG. 21 is a top view showing the configuration of the semiconductor device 3 according to this embodiment. As shown in FIG. 21, the semiconductor device 3 has a configuration in which the gate electrode 25 is replaced with a gate electrode 35 in the same configuration as that of the semiconductor device 2 according to the second embodiment. Although not shown in FIG. 21, the gate insulating film 23 is also replaced with a gate insulating film having the same top surface pattern as the gate electrode 35.

  The gate electrode 35 has comb-shaped electrode portions 35a periodically arranged along the channel width direction on the side surface on the drain (17d) side. The comb-like electrode portion 35 a is formed integrally with the gate electrode 35.

  Here, an enlarged view of a region o3 in FIG. 21 is shown in FIG. As shown in FIG. 22, each comb-like electrode portion 35a includes a first side surface S31 parallel to the gate width direction, a second side surface S32 projecting in the gate length direction from the first side surface S31, and a second side surface. It has a concavo-convex shape including a third side surface S33 connecting the first side surface S31 and the second side surface S32 at both ends of S32, the length d7 of the third side surface S33, the first side surface S31 and the second side surface S32. It has a length d6. Further, the distance between the first side surfaces S31 and the second side surface S32 adjacent in the gate width direction is set to d5.

As is apparent from a comparison between FIG. 22 and FIG. 11, the corners C5 and C6 of the comb-shaped electrode portion 35a are substantially equal to the corners C1 and C2 of the comb-shaped electrode portion 15a. On the other hand, it is obtuse. Thus, by making the corners of the comb-like electrode portion 35a obtuse, the electric field generated at the corners can be adjusted to be low. Thereby, the spread of the depletion layer D formed in the regions B5 and B6 below the corners C5 and C6 of the comb-like electrode part 35a can be adjusted, and as a result, when a surge current is input It becomes possible to adjust the current flowing through the regions B5 and B6 to be smaller than that in the first embodiment. That is, as shown in the graph of FIG. 23, the straight lines indicating the currents I _B5 and I _B6 flowing through the individual regions B5 and B6 are shifted from the straight lines indicating the currents I _B1 and I _B2 in the first embodiment to the right. It becomes possible to adjust.

  Further, in this embodiment, as shown in FIG. 22, for example, when a current of a certain value is input, the width in the horizontal direction of the depletion layer D formed in the region B5 or B6 below the corner C5 or C6 (hereinafter referred to as the horizontal portion). , The spread of the depletion layer D) is d1, the convex length d7 of the comb-shaped electrode portion 35a, the width d6 of the tip and bottom of the comb-shaped electrode portion 35a, and the distance between the tips or the bottom The interval d5 is set to be wider than twice the spread d1 of the depletion layer D, as in the first embodiment.

  Thus, by setting the length d7, the width d6, and the interval d5 of the comb-like electrode portion 35a to values wider than the spread d1 of the depletion layer D formed in the region B5 or B6, a certain region It can be avoided that the depletion layer D formed in B5 / B6 and the depletion layer D formed in the adjacent regions B5 / B6 are combined and integrated. As a result, it is possible to reliably form an expected number of current paths (an increase due to the number of corners C5 and C6), and it is possible to reliably reduce the current flowing through one current path.

  Similarly, the gate electrode 35 has comb-shaped electrode portions 35b periodically arranged along the channel width direction on the side surface on the source (17s) side. The comb-like electrode portion 35b has the same configuration as the comb-like electrode portion 35a, and is formed integrally with the gate electrode 35.

In this manner, by providing the comb-like electrode portion 35b not only on the drain (17d) side but also on the source (17s) side, the current flowing to the source (17s) side can be supplied not only to the corner portion A but also to the source ( The currents I _B7 and I _B8 can also be dispersed in the regions B7 and B8 below the corners of the comb-like electrode portion 35b on the 17s) side. As a result, it is possible to prevent current from concentrating on the corner A on the source (17 s) side, and to further improve the breakdown voltage characteristics of the semiconductor device 3.

  Further, with this configuration, for example, even when a surge current is input from the source (17s) side, the concentration points of the electric field can be dispersed as in the case where the surge current is input from the drain (17d) side. Become. As a result, it is possible to improve the breakdown voltage characteristics when a surge current is input from the source (17s) side.

  However, it is preferable that the convex portion in the comb-shaped electrode portion 35a and the convex portion in the comb-shaped electrode portion 35b are configured so as not to overlap in the gate length direction as in the second embodiment. Thereby, it is possible to prevent the gate length from being locally increased to such an extent that the characteristics of the transistor are deteriorated, and it is possible to prevent the operation characteristics and the breakdown voltage characteristics from being significantly changed.

  Such a gate electrode 35 can be made of the same material and film thickness as the gate electrode 15 according to the first embodiment. The gate insulating film under the gate electrode 35 has an upper surface having the same shape as the gate electrode 35. This gate insulating film can be formed of the same material and film thickness as the gate insulating film 13 according to the first embodiment.

  Since the other configuration is the same as that of the semiconductor device 1 according to the first embodiment or the semiconductor device 2 according to the second embodiment as described above, detailed description thereof is omitted here.

〔Production method〕
In addition, the manufacturing method of the semiconductor device 3 according to the present embodiment is the same as the manufacturing method of the semiconductor device 1 according to the first embodiment, and thus detailed description thereof is omitted here. However, in this embodiment, the resist R2 in FIG. 14B is formed in a pattern including the gate electrode 35 shown in FIG. 21, that is, the comb-like electrode portions 35a and 35b. Therefore, in the steps after FIG. 15A, the gate electrode 15 and the gate insulating film under the gate electrode 35 are replaced with the gate electrode 35 and a gate insulating film having the same top surface pattern as the gate electrode 35, respectively.

[Function and effect]
As described above, the semiconductor device 3 according to this example includes the semiconductor substrate 11, the pair of low concentration diffusion regions 17s and 17d formed on the surface of the semiconductor substrate 11, and at least the surfaces of the pair of low concentration diffusion regions 17s and 17d. High-concentration diffusion regions 18s and 18d that are partially formed and have a higher impurity concentration than the pair of low-concentration diffusion regions 17s and 17d, and regions sandwiched between the pair of low-concentration diffusion regions 17s and 17d on the surface of the semiconductor substrate 11 A gate insulating film formed on the gate insulating film; a first side surface S31 formed on the gate insulating film and having both side surfaces on the drain (17d) side and the source (17s) side parallel to the gate width direction; A second side S32 protruding in the gate length direction from S31 and a first side S31 and a second side S32 are connected at both ends of the second side S32. Constructed and a gate electrode 35 comprising a side surface S33.

  As described above, this embodiment includes a pair of low-concentration diffusion regions 17s and 17d and high-concentration diffusion regions 18s and 18d having a higher impurity diffusion concentration, thereby providing a semiconductor having a breakdown voltage characteristic with respect to a relatively high voltage. In the device 3, the side surfaces of the gate electrode 35 on the drain (17d) side and the source (17s) side are respectively the first side surface S31 parallel to the gate width direction and the second side surface protruding in the gate length direction from the first side surface S31. It includes a side surface S32 and a third side surface S33 connecting the first side surface S31 and the second side surface S32. In other words, both side surfaces of the gate electrode 35 have comb-like electrode portions 35a and 35b having an uneven shape. Thus, for example, when a relatively large current such as a surge current is input from the low concentration diffusion region 17d or 17s on the drain (17d) side or the source (17s) side, a portion where the electric field is concentrated is formed in an uneven shape. Therefore, it is possible to reduce the intensity of the electric field generated at one corner and reduce the current flowing through the depletion layer formed below each corner. In addition, by increasing the number of corners of the gate electrode in this way, it is possible to increase the number of paths through which current concentrates, so that the amount of current passing through one path can be reduced. . From these, according to the present embodiment, it is possible to reduce the amount of current that flows in a concentrated manner when a relatively large current such as a surge current is input, so that the breakdown voltage characteristics of the semiconductor device 3 are improved. Is achieved.

  In this embodiment, the angle formed by the second side surface and the third side surface and / or the angle formed by the first side surface and the second side surface, that is, the corner portions of the comb-shaped electrode portions 35a and 35b are obtuse angles. is there. By making the corners obtuse in this way, it becomes possible to reduce the strength of the electric field generated at the corners, so that the amount of current flowing in the depletion layer formed below the corners can be reduced. it can. In other words, the amount of current flowing under the corner can be adjusted by adjusting the angle of the corner.

[Application form]
In addition, the configuration of the electronic circuit configured using the semiconductor device 3 according to the present embodiment is the same as that described with reference to FIG. 16 in the first embodiment, and thus detailed description thereof is omitted here.

  Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first to third embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as any one of the first to third embodiments.

〔Constitution〕
FIG. 24 is a top view showing the configuration of the semiconductor device 4 according to this embodiment. As shown in FIG. 24, the semiconductor device 4 has a configuration in which the gate electrode 25 or 35 is replaced with a gate electrode 45 in the same configuration as the semiconductor device 2 according to the second embodiment or the semiconductor device 3 according to the third embodiment. In FIG. 24, although not shown, the gate insulating film is also replaced with a gate insulating film having the same top surface pattern as the gate electrode 45.

  The gate electrode 45 has comb-like electrode portions 45a periodically arranged along the channel width direction on the side surface on the drain (17d) side. The comb-like electrode portion 45 a is formed integrally with the gate electrode 45.

  Here, an enlarged view of a region o4 in FIG. 24 is shown in FIG. As shown in FIG. 25, each comb-like electrode portion 45a includes a first side surface S41 parallel to the gate width direction, a second side surface S42 protruding in the gate length direction from the first side surface S41, and a second side surface. It has an uneven shape including a third side surface S43 connecting the first side surface S41 and the second side surface S42 at both ends of S42. The length d10 of the third side surface S43, the first side surface S41 and the second side surface S42 It has a length d9. Further, the distance between the first side surfaces S41 and the second side surfaces S42 adjacent in the gate width direction is set to d8.

As is apparent from a comparison between FIG. 25 and FIG. 11, the corners C9 and C10 of the comb-like electrode portion 45a are substantially perpendicular to the corners C1 and C2 of the comb-like electrode portion 15a. On the other hand, it has an acute angle. In this way, by setting the corners of the comb-like electrode portion 45a to an acute angle, the electric field generated at the corner of the comb-like electrode portion 45a can be adjusted to be stronger, contrary to the third embodiment. . As a result, the spread of the depletion layer D formed in the regions B9 and B10 below the corners C9 and C10 of the comb-like electrode portion 45a can be adjusted, and as a result, when a surge current is input It is possible to adjust so that the current flowing through the regions B9 and B10 is larger than that in the first embodiment. That is, as shown in the graph of FIG. 26, the straight lines indicating the currents I _B9 and I _B10 flowing in the individual regions B9 and B10 are shifted from the straight lines indicating the currents I _B1 and I _B2 in the first embodiment to the left. It becomes possible to adjust.

  That is, as apparent from referring to the semiconductor device 3 according to the third embodiment and the semiconductor device 4 according to the present embodiment, by adjusting the angle of the corners of the comb-like electrode portions formed on the side surfaces of the gate electrodes, It becomes possible to adjust the ratio of the amount of current flowing in the region below the corner to the other part, and as a result, a semiconductor device having desired operation characteristics and breakdown voltage characteristics can be realized.

  Further, in this embodiment, as shown in FIG. 25, for example, when a current of a certain value is input, the width in the horizontal direction of the depletion layer D formed in the region B9 or B10 below the corner C9 or C10 (hereinafter referred to as the horizontal portion). , The spread of the depletion layer D) is defined as d1, the convex length d10 of the comb-like electrode portion 45a, the width d9 of the tip and bottom portions of the comb-like electrode portion 45a, and between or between the tip portions The interval d8 is set to be larger than twice the spread d1 of the depletion layer D, as in the first embodiment.

  In this way, by setting the length d10, the width d9, and the interval d8 of the comb-shaped electrode portion 45a to values wider than the spread d1 of the depletion layer D formed in the region B9 or B10, a certain region It can be avoided that the depletion layer D formed in B9 / B10 and the depletion layer D formed in the adjacent region B9 / B10 are combined with each other. As a result, it is possible to reliably form an expected number of current paths (an increase due to the number of corners C9 and C10), and it is possible to reliably reduce the current flowing through one current path.

  Similarly, the gate electrode 45 includes comb-like electrode portions 45b periodically arranged along the channel width direction on the side surface on the source (17s) side. The comb-like electrode part 45b is formed integrally with the gate electrode 45 while having the same configuration as the comb-like electrode part 45a.

In this way, by providing the comb-like electrode portion 45b not only on the drain (17d) side but also on the source (17s) side, the current flowing to the source (17s) side can be supplied not only to the corner portion A but also to the source ( The currents I _B11 and I _B12 can also be dispersed in the regions B11 and B12 below the corners of the comb-like electrode portion 45b on the 17s) side. As a result, it is possible to prevent current from concentrating on the corner A on the source (17 s) side, and to further improve the breakdown voltage characteristics of the semiconductor device 4.

  Further, with this configuration, for example, even when a surge current is input from the source (17s) side, the concentration points of the electric field can be dispersed as in the case where the surge current is input from the drain (17d) side. Become. As a result, it is possible to improve the breakdown voltage characteristics when a surge current is input from the source (17s) side.

  However, it is preferable that the convex portion in the comb-shaped electrode portion 45a and the convex portion in the comb-shaped electrode portion 45b are configured so as not to overlap in the gate length direction as in the second and third embodiments. Thereby, it is possible to prevent the gate length from being locally increased to such an extent that the characteristics of the transistor are deteriorated, and it is possible to prevent the operation characteristics and the breakdown voltage characteristics from being significantly changed.

  Such a gate electrode 45 can be made of the same material and film thickness as the gate electrode 15 according to the first embodiment. The gate insulating film under the gate electrode 45 has an upper surface having the same shape as the gate electrode 45. This gate insulating film can be formed of the same material and film thickness as the gate insulating film 13 according to the first embodiment.

  Since the other configuration is the same as that of any of the semiconductor devices 1 to 3 according to the first to third embodiments as described above, detailed description thereof is omitted here.

〔Production method〕
In addition, the manufacturing method of the semiconductor device 4 according to the present embodiment is the same as the manufacturing method of the semiconductor device 1 according to the first embodiment, and thus detailed description thereof is omitted here. However, in this embodiment, the resist R2 in FIG. 14B is formed in a pattern including the gate electrode 45 shown in FIG. 24, that is, the comb-like electrode portions 45a and 45b. Therefore, in the steps after FIG. 15A, the gate electrode 15 and the gate insulating film under the gate electrode 45 are respectively replaced with the gate electrode 45 and a gate insulating film having the same upper surface pattern.

[Function and effect]
As described above, the semiconductor device 4 according to the present embodiment includes the semiconductor substrate 11, the pair of low concentration diffusion regions 17s and 17d formed on the surface of the semiconductor substrate 11, and at least the surfaces of the pair of low concentration diffusion regions 17s and 17d. High-concentration diffusion regions 18s and 18d that are partially formed and have a higher impurity concentration than the pair of low-concentration diffusion regions 17s and 17d, and regions sandwiched between the pair of low-concentration diffusion regions 17s and 17d on the surface of the semiconductor substrate 11 A gate insulating film formed thereon, a first side surface S41 formed on the gate insulating film, with both side surfaces on the drain (17d) side and the source (17s) side being parallel to the gate width direction; A second side S42 protruding in the gate length direction from S41, and a first side S41 and a second side S42 are connected at both ends of the second side S42. Constructed and a gate electrode 45 comprising a side surface S43.

  As described above, this embodiment includes a pair of low-concentration diffusion regions 17s and 17d and high-concentration diffusion regions 18s and 18d having a higher impurity diffusion concentration, thereby providing a semiconductor having a breakdown voltage characteristic with respect to a relatively high voltage. In the device 4, the side surfaces of the gate electrode 45 on the drain (17d) side and the source (17s) side are respectively the first side surface S41 parallel to the gate width direction and the second side surface protruding in the gate length direction from the first side surface S41. It includes a side surface S42, and a third side surface S43 connecting the first side surface S41 and the second side surface S42. That is, both side surfaces of the gate electrode 45 have the comb-like electrode portions 45a and 45b having an uneven shape. Thus, for example, when a relatively large current such as a surge current is input from the low concentration diffusion region 17d or 17s on the drain (17d) side or the source (17s) side, a portion where the electric field is concentrated is formed in an uneven shape. Therefore, it is possible to reduce the intensity of the electric field generated at one corner and reduce the current flowing through the depletion layer formed below each corner. In addition, by increasing the number of corners of the gate electrode in this way, it is possible to increase the number of paths through which current concentrates, so that the amount of current passing through one path can be reduced. . From these, according to the present embodiment, it is possible to reduce the amount of current that flows in a concentrated manner when a relatively large current such as a surge current is input, so that the breakdown voltage characteristics of the semiconductor device 4 are improved. Is achieved.

  In this embodiment, the angle formed by the second side surface and the third side surface and / or the angle formed by the first side surface and the second side surface, that is, the corner portions of the comb-like electrode portions 45a and 45b are acute angles. is there. By setting the corner to an acute angle in this way, it is possible to increase the strength of the electric field generated at the corner, and thus the amount of current flowing in the depletion layer formed below the corner can be increased. it can. In other words, the amount of current flowing under the corner can be adjusted by adjusting the angle of the corner.

[Application form]
Further, the configuration of the electronic circuit configured using the semiconductor device 4 according to the present embodiment is the same as that described with reference to FIG. 16 in the first embodiment, and thus detailed description thereof is omitted here.

  Next, a fifth embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first to fourth embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as that of any one of the first to fourth embodiments.

〔Constitution〕
FIG. 27 is a top view showing the configuration of the semiconductor device 5 according to this embodiment. As shown in FIG. 27, the semiconductor device 5 has a configuration in which the gate electrode 25, 35 or 45 is replaced with a gate electrode 55 in the same configuration as that of any of the semiconductor devices 2 to 4 according to the second to fourth embodiments. In FIG. 27, although not shown, the gate insulating film is also replaced with a gate insulating film having the same top surface pattern as the gate electrode 55.

  The gate electrode 55 has comb-like electrode portions 55a that are periodically arranged along the channel width direction on the side surface on the drain (17d) side. The comb-like electrode portion 55 a is formed integrally with the gate electrode 45.

  Here, an enlarged view of the region o5 in FIG. 27 is shown in FIG. As shown in FIG. 28, each comb-like electrode portion 55a includes a second side surface S52 that is parallel to the gate width direction and a third side surface S53 that connects the second side surfaces S52 in a V shape. It has a letter-shaped depression and is formed with a length d14 of the third side surface S53 and a length d13 of the second side surface S52. The interval between the second side surfaces S52 adjacent in the gate width direction is set to d12.

As is clear from comparison between FIG. 28 and FIG. 11, the corner C13 at the tip of the comb-like electrode portion 55a is substantially perpendicular to the corner C1 at the tip of the comb-like electrode 15a. Is obtuse. Thus, by making the corner of the tip of the comb-like electrode portion 55a an obtuse angle, the electric field generated at the corner of the tip of the comb-like electrode portion 55a is adjusted to be weak as in the third embodiment. be able to. As a result, the spread of the depletion layer D formed in the region B13 below the corner C13 at the tip of the comb-shaped electrode portion 55a can be adjusted, and as a result, the region B13 can be adjusted when a surge current is input. It is possible to adjust the flowing current to be smaller than that in the first embodiment. That is, as shown in the graph of FIG. 29, the straight line indicating the current I _B13 flowing through each region B13 can be adjusted to shift to the right from the straight line indicating the current I _a1 in the first embodiment.

Further, the corner C14 at the bottom of the comb-shaped electrode portion 55a forms an acute angle, whereas the corner C2 at the bottom of the comb-shaped electrode 15a forms a substantially right angle. In this way, by making the corner of the bottom of the comb-like electrode portion 55a an obtuse angle, the electric field generated at the corner of the bottom of the comb-like electrode 55b is adjusted to be strong as in the fourth embodiment. be able to. As a result, the spread of the depletion layer D formed in the region B14 below the corner portion C14 of the comb-like electrode portion 55a can be adjusted, and as a result, the current flowing through the region B14 when a surge current is input. Can be adjusted to be larger than that of the first embodiment. That is, as shown in the graph of FIG. 29, the straight line indicating the current I _B14 flowing through the individual areas B14, it becomes possible to adjust the line indicating current I _B2 in Example 1 so as to shift to the left.

  Thus, the current flowing through each of the regions B13 and B14 can be adjusted by setting the corners at the tip and bottom of the comb-shaped electrode portion 55a to an obtuse or acute angle, respectively. Note that at the bottom of the comb-shaped electrode portion 55a, one corner C14 is formed by two adjacent comb-shaped electrode portions 55a.

  In this embodiment, as shown in FIG. 28, for example, when a current of a certain value is input, the horizontal width (hereinafter referred to as the depletion layer D formed in the region B13 or B14 below the corner C13 or C14). (Where the depletion layer D spreads) is defined as d1, the convex length d13 of the comb-shaped electrode portion 55a, the width d12 of the tip portion of the comb-shaped electrode portion 55a, and the distance d11 between the tip portions In the same manner as in Example 1, each is set to be wider than twice the spread d1 of the depletion layer D.

  Thus, by setting the length d13, the width d12, and the interval d11 of the comb-shaped electrode portion 55a to values wider than the spread d1 of the depletion layer D formed in the region B13 or B14, a certain region It can be avoided that the depletion layer D formed in B13 / B14 and the depletion layer D formed in the adjacent regions B13 / B14 are combined and integrated. As a result, it is possible to reliably form an expected number of current paths (an increase due to the number of corners C13 and C14), and it is possible to reliably reduce the current flowing through one current path.

  Similarly, the gate electrode 55 has comb-like electrode portions 55b periodically disposed along the channel width direction on the side surface on the source (17s) side. The comb-like electrode portion 55b is formed integrally with the gate electrode 55 while having the same configuration as the comb-like electrode portion 55a.

In this manner, by providing the comb-like electrode portion 35b not only on the drain (17d) side but also on the source (17s) side, the current flowing to the source (17s) side can be supplied not only to the corner portion A but also to the source ( The currents I _B15 and I _B16 can also be dispersed in the regions B15 and B16 below the corners of the comb-like electrode portion 55b on the 17s) side. As a result, it is possible to prevent current from concentrating on the corner A on the source (17s) side, and to further improve the breakdown voltage characteristics of the semiconductor device 5.

  Further, with this configuration, for example, even when a surge current is input from the source (17s) side, the concentration points of the electric field can be dispersed as in the case where the surge current is input from the drain (17d) side. Become. As a result, it is possible to improve the breakdown voltage characteristics when a surge current is input from the source (17s) side.

  However, it is preferable that the convex portion in the comb-shaped electrode portion 55a and the convex portion in the comb-shaped electrode portion 55b are configured so as not to overlap in the gate length direction as in the second to fourth embodiments. Thereby, it is possible to prevent the gate length from being locally increased to such an extent that the characteristics of the transistor are deteriorated, and it is possible to prevent the operation characteristics and the breakdown voltage characteristics from being significantly changed.

  Such a gate electrode 55 can be made of the same material and film thickness as the gate electrode 15 according to the first embodiment. Further, the gate insulating film under the gate electrode 55 has an upper surface having the same shape as the gate electrode 55. This gate insulating film can be formed of the same material and film thickness as the gate insulating film 13 according to the first embodiment.

  Since the other configuration is the same as that of any one of the semiconductor devices 1 to 4 according to the first to fourth embodiments as described above, detailed description thereof is omitted here.

〔Production method〕
In addition, the manufacturing method of the semiconductor device 5 according to the present embodiment is the same as the manufacturing method of the semiconductor device 1 according to the first embodiment, and thus detailed description thereof is omitted here. However, in this embodiment, the resist R2 in FIG. 14B is formed in a pattern including the gate electrode 55 shown in FIG. 27, that is, the comb-like electrode portions 55a and 55b. Therefore, in the steps after FIG. 15A, the gate electrode 15 and the gate insulating film under the gate electrode 55 are respectively replaced with the gate electrode 55 and a gate insulating film having the same upper surface pattern.

[Function and effect]
As described above, the semiconductor device 5 according to this embodiment includes the semiconductor substrate 11, the pair of low concentration diffusion regions 17s and 17d formed on the surface of the semiconductor substrate 11, and at least the surfaces of the pair of low concentration diffusion regions 17s and 17d. High-concentration diffusion regions 18s and 18d that are partially formed and have a higher impurity concentration than the pair of low-concentration diffusion regions 17s and 17d, and regions sandwiched between the pair of low-concentration diffusion regions 17s and 17d on the surface of the semiconductor substrate 11 A gate insulating film formed on the gate insulating film; and a gate electrode 55 formed on the gate insulating film and having V-shaped depressions on both sides of the drain (17d) side and the source (17s) side. Is done.

  As described above, this embodiment includes a pair of low-concentration diffusion regions 17s and 17d and high-concentration diffusion regions 18s and 18d having a higher impurity diffusion concentration, thereby providing a semiconductor having a breakdown voltage characteristic with respect to a relatively high voltage. In the device 5, the gate electrode 55 has V-shaped depressions on both side surfaces on the drain (17d) side and the source (17s) side. That is, by forming V-shaped grooves on both side surfaces of the gate electrode 55, the comb-shaped electrode portions 55a and 55b are provided. Thereby, for example, when a relatively large current such as a surge current is input from the low concentration diffusion region 17d or 17s on the drain (17d) side or the source (17s) side, the portion where the electric field is concentrated is combed. Can be dispersed at the corners of the electrode portions 55a and 55b, so that the intensity of the electric field generated at one corner can be reduced, and the current flowing through the depletion layer formed below each corner can be reduced. . In addition, by increasing the number of corners of the gate electrode in this way, it is possible to increase the number of paths through which current concentrates, so that the amount of current passing through one path can be reduced. . From these, according to the present embodiment, it is possible to reduce the amount of current that flows in a concentrated manner when a relatively large current such as a surge current is input, thereby improving the breakdown voltage characteristics of the semiconductor device 5. Is achieved.

  In the present embodiment, the angle formed by the second side surface S52 and the third side surface S53, that is, the corners at the tips of the comb-like electrode portions 55a and 35b are obtuse angles. By making the corners obtuse in this way, it becomes possible to reduce the strength of the electric field generated at the corners, so that the amount of current flowing in the depletion layer formed below the corners can be reduced. it can. Further, the corners formed by the third side surfaces S53, that is, the corners at the bottoms of the comb-like electrode portions 55a and 55b are acute angles. By setting the corner to an acute angle in this way, it is possible to increase the strength of the electric field generated at the corner, and thus the amount of current flowing in the depletion layer formed below the corner can be increased. it can. Thus, by adjusting the angle of the corner portion, the amount of current flowing under the corner portion can be adjusted.

[Application form]
Further, the configuration of the electronic circuit configured using the semiconductor device 5 according to the present embodiment is the same as that described with reference to FIG. 16 in the first embodiment, and thus detailed description thereof is omitted here.

  In addition, the first to fifth embodiments described above are merely examples for carrying out the present invention, and the present invention is not limited to these. Various modifications of these embodiments are within the scope of the present invention. It is obvious from the above description that various other embodiments are possible within the scope of the present invention.

  Further, the semiconductor devices 1, 2, 3, 4 or 5 according to the above-described embodiments can be used as, for example, a protection element for ESD countermeasures. In this case, the semiconductor device 1, 2, 3, 4 or 5 can be provided, for example, in an input stage or an output stage of a semiconductor device including the semiconductor device. Note that examples of the semiconductor device including the semiconductor devices 1, 2, 3, 4 or 5 include an input device, an output device, and an input / output device. Regarding these configurations, since general configurations other than the configurations of the semiconductor devices 1, 2, 3, 4 or 5 illustrated in the embodiments of the present invention can be applied, detailed description will be given here. Omitted.

It is a top view which shows the structure of the high voltage transistor 900 by a prior art. It is a figure which shows the structure of the i-i 'cross section in FIG. It is an enlarged view of the area | region o1 in FIG. (A) is a graph showing the impurity concentration along the line ii-iii ′ in FIG. 3, and (b) is a graph showing the impurity concentration along the line iii-iii ′ in FIG. 3. (A) is an energy band diagram at position P1 on the ii-iii 'line in FIG. 3, and (b) is an energy band diagram at position P2 on the iii-iii' line in FIG. c (A) shows the structure of the depletion layer D in the cross section along the ii-iii 'line in FIG. 3, and (b) shows the structure of the depletion layer D in the cross section along the iii-iii' line in FIG. Is a graph showing the current I _a flowing through the corner a of the semiconductor device 900 according to the prior art. 1 is a top view showing a configuration of a semiconductor device 1 according to Embodiment 1 of the present invention. It is a figure which shows the structure of the I-I 'cross section in FIG. It is a figure which shows the structure of the II-II 'cross section in FIG. It is an enlarged view of the area | region o2 in FIG. 4 is a graph showing currents I _A , I _B1, and I _B2 flowing in regions A, B1, and B2 of the semiconductor device 1 according to Example 1 of the present invention, respectively. It is a process diagram which shows the manufacturing method of the semiconductor device 1 by Example 1 of this invention (1). It is a process diagram which shows the manufacturing method of the semiconductor device 1 by Example 1 of this invention (2). It is a process diagram which shows the manufacturing method of the semiconductor device 1 by Example 1 of this invention (3). It is a figure which shows the structure of the electronic circuit 100 comprised using the semiconductor device 1 by Example 1 of this invention. It is a top view which shows the structure of the semiconductor device 2 by Example 2 of this invention. It is a figure which shows the structure of the III-III 'cross section in FIG. It is a figure which shows the structure of the IV-IV 'cross section in FIG. It is a top view which shows the structure of semiconductor device 2 'which is a modification of the semiconductor device 2 by Example 2 of this invention. It is a top view which shows the structure of the semiconductor device 3 by Example 3 of this invention. It is an enlarged view of the area | region o3 in FIG. 7 is a graph showing currents I _A , I _B5, and I _B6 flowing in regions A, B5, and B6 of a semiconductor device 3 according to Example 3 of the present invention, respectively. It is a top view which shows the structure of the semiconductor device 4 by Example 4 of this invention. It is an enlarged view of the area | region o4 in FIG. Example 4 by the area of the semiconductor device 4 A, B11 and current flowing in each of the B12 _I A of the present _invention, is a graph showing the _{I B11} and _{I B12.} It is a top view which shows the structure of the semiconductor device 5 by Example 5 of this invention. It is an enlarged view of the area | region o5 in FIG. Current _I A flowing according to Example 4 in each of the regions A, B13 and B14 of the semiconductor device 4 of the present _invention, is a graph showing the _{I B13} and _{I B14.}

Explanation of symbols

1, 2, 3, 4, 5 Semiconductor device 11 Semiconductor substrate 12 Element isolation insulating film 12a Silicon oxide film 12b Silicon nitride film 13, 23 Gate insulating film 13A Silicon oxide film 15, 25, 25 ′, 35, 45, 55 Gate Electrode 15a, 25b, 35a, 35b, 45a, 45b, 55a, 55b Comb-like electrode portion 15A Polysilicon film 16, 16 'Channel formation region 17d, 17d', 17s, 17s' Low concentration diffusion region 18d, 18s High concentration Diffusion region 21 Interlayer insulating film 22s, 22d In-contact wiring 23s Source electrode 23d Drain electrode 27d ', 27s' region 100 Electronic circuit 101 Output circuit 102 Internal circuit B1-B16 region C1, C2, C5, C6, C9, C10, C13 , C14 Corner D Depletion layer L1-L3 Concentration line R1-R3 DOO S11, S31, S41 first aspect S12, S32, S42, S52 second side S13, S33, S43, S53 third aspect AR active region FR field region P1, N1 output transistor

Claims (25)

A semiconductor substrate;
A pair of diffusion regions formed on the surface of the semiconductor substrate;
A gate insulating film formed on the surface of the semiconductor substrate;
Formed on the surface of the semiconductor substrate via the gate insulating film, and at least one side surface is a first side surface parallel to the gate width direction, a second side surface protruding in the gate length direction from the first side surface, A semiconductor device comprising: a gate electrode connected to a signal line, and including a third side surface connecting the first side surface and the second side surface at both ends of the second side surface.   2. The semiconductor device according to claim 1, wherein both sides of the gate electrode include the first side, the second side, and the third side, respectively.   The semiconductor device according to claim 1, wherein the second side surface is periodically provided on the side surface at a predetermined interval.   4. The angle formed by the second side surface and the third side surface and / or the angle formed by the first side surface and the third side surface is 90 °. 5. A semiconductor device according to 1.   The angle formed between the second side surface and the third side surface and / or the angle formed between the first side surface and the second side surface is an acute angle or an obtuse angle, respectively. 2. A semiconductor device according to item 1.   The horizontal length of the first to third side surfaces is an angle formed by the second side surface and the third side surface when a predetermined voltage is applied to the gate electrode and / or the first side surface. 6. The method according to claim 1, wherein the depletion layer formed in the semiconductor substrate below a corner formed by the third side surface is longer than twice a horizontal spread. 7. Semiconductor device.   The second side surface forming one side surface of the gate electrode and the second side surface forming the other side surface are alternately arranged so as not to overlap in the gate length direction. Item 3. The semiconductor device according to Item 2.   The one side surface of the gate electrode is located on one diffusion region of the pair of diffusion regions, and the other side surface is located on the other diffusion region of the pair of diffusion regions. Item 8. The semiconductor device according to any one of Items 1 to 7. A semiconductor substrate;
A pair of diffusion regions formed on the surface of the semiconductor substrate;
A gate insulating film formed on the surface of the semiconductor substrate;
A V-shaped notch is formed in the semiconductor substrate surface via the gate insulating film, and at least one side surface thereof is formed in the gate length direction, and has a gate electrode connected to the signal line. A semiconductor device.   The diffusion region includes a first region having a predetermined impurity concentration and a second region formed in at least a part of the surface of the first region and having a higher impurity concentration than the first region. The semiconductor device according to claim 1.   11. A semiconductor device using the semiconductor device according to claim 1 as a protection element for measures against static electricity.   A semiconductor device comprising the semiconductor device according to claim 1 in an input stage or an output stage.   13. A semiconductor device comprising an input device including the semiconductor device according to claim 1.   13. A semiconductor device, comprising: an output device including the semiconductor device according to claim 1.   A semiconductor device comprising an input / output device including the semiconductor device according to claim 1. Preparing a semiconductor substrate;
Forming a pair of first diffusion regions on the surface of the semiconductor substrate;
Forming a gate insulating film on the semiconductor substrate surface;
At least one side surface is a first side surface parallel to the gate width direction, a second side surface projecting in the gate length direction from the first side surface, and the first side surface and the second side surface at both ends of the second side surface. And forming a gate electrode connected to a predetermined signal line on the gate insulating film. The method of manufacturing a semiconductor device, comprising:   17. The method of manufacturing a semiconductor device according to claim 16, wherein both side surfaces of the gate electrode include the first side surface, the second side surface, and the third side surface, respectively.   18. The method of manufacturing a semiconductor device according to claim 16, wherein the second side surface is periodically provided on the side surface at a predetermined interval.   19. The angle formed by the second side surface and the third side surface and / or the angle formed by the first side surface and the third side surface is 90 °. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   The angle formed by the second side surface and the third side surface and / or the angle formed by the first side surface and the second side surface is an acute angle or an obtuse angle, respectively. A method for manufacturing a semiconductor device according to claim 1.   The horizontal length of the first to third side surfaces is an angle formed by the second side surface and the third side surface when a predetermined voltage is applied to the gate electrode and / or the first side surface. The length of the depletion layer formed in the semiconductor substrate below the corner formed by the third side surface is longer than twice the horizontal extent, 21. A method for manufacturing a semiconductor device.   The second side surface forming one side surface of the gate electrode and the second side surface forming the other side surface are alternately arranged so as not to overlap in the gate length direction. Item 18. A method for manufacturing a semiconductor device according to Item 17.   The one side surface of the gate electrode is located on one first diffusion region of the pair of first diffusion regions, and the other side surface is on the other first diffusion region of the pair of first diffusion regions. The method of manufacturing a semiconductor device according to claim 16, wherein the semiconductor device is formed so as to be located at a position. Preparing a semiconductor substrate;
Forming a pair of first diffusion regions on the surface of the semiconductor substrate;
Forming a gate insulating film on the semiconductor substrate surface;
And a step of forming a gate electrode connected to a predetermined signal line on the gate insulating film, having a V-shaped notch in the gate length direction on at least one side surface. Manufacturing method.   25. The method according to claim 16, further comprising forming a second diffusion region having an impurity concentration higher than that of the pair of first diffusion regions on at least a part of the surfaces of the pair of first diffusion regions. A method for manufacturing a semiconductor device according to claim 1.

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