JPH1187694A - Field-effect transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a field-effect transistor for improving high frequency characteristics. SOLUTION: A low resistance metal film 40, made of tungsten (W) or the like is formed so as to be brought into contact with at least the overall upper part surface of a folded gate electrode 30 formed on a semiconductor substrate between a source region 32 and a drain region 34 formed on the substrate. With such a configuration, a gate resistance can be very much reduced, and a drain junction capacity at a unit gate width can be reduced. Therefore, a ratio fmax/fT of the maximum oscillation frequency (fmax) to a cut-off frequency (fT) can be increased, and hence a MOSFET (field-effect transistor) can be operated in a higher frequency band.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (MOSFET) having a small gate length and a high frequency characteristic of low noise and high gain, and a method of manufacturing the same.

[0002]

2. Description of the Related Art At the front end of mobile communication equipment,
An element having high frequency characteristics with low noise and high gain is required. In these fields, GaAs ICs and bipolar LSIs have been widely used. However, when considering the realization of a one-chip analog / digital hybrid LSI with a view to miniaturization and cost reduction of communication equipment, silicon MOSFETs are becoming new candidates.

As the miniaturization of silicon MOSFETs has progressed, the switching speed of CMOS devices has increased, and the high-frequency characteristics of a single MOSFET have become comparable to GaAs devices and bipolar devices. However, silicon MOSFETs have large parasitic resistances and parasitic capacitances such as gate resistance, source resistance, drain resistance, source junction capacitance and drain junction capacitance, and these parasitic components cause high-frequency characteristics, particularly the maximum oscillation frequency (fmax). Affects deterioration.

[0004] A guideline for solving this is T. Yamamoto.
et al., Symp.on VLSI Tech.Dig., (1996) p.136-137
It is described in.

According to the above document, silicon MOSFET
Among the parasitic components, the components that greatly affect the deterioration of the maximum oscillation frequency fmax are the ratio (Cdb / Cgs) between the drain junction capacitance and the gate-source capacitance and the gate resistance (R
g). For any parasitic components towards smaller increases the ratio fmax / f _T of the cut-off frequency f _T and the maximum oscillation frequency fmax. Here, the cut-off frequency f _T is given by the following equation.

[0006]

F _T = gm / 2π (Cgs + Cgd) (1) From the equation (1), the cutoff frequency f _T is the transconductance (gm), the gate-source capacitance (Cgs), the gate
It turns out that it depends only on the capacitance between drains (Cgd).
Since the cutoff frequency f _T does not depend on the gate resistance Rg and the ratio Cdb / Cgs between the drain junction capacitance and the gate-source capacitance, if gm, Cgs, and Cgd are constant, the maximum oscillation frequency fmax is equal to the gate resistance Rg and the drain. It can be seen that the ratio Cdb / Cgs between the junction capacitance and the gate-source capacitance is reduced, that is, the drain-gate capacitance Cdb is increased because the gate-source capacitance Cgs is constant.

As one of the methods for reducing the parasitic component, a method for reducing the gate resistance Rg is reported in the above document. FIG. 12 is a diagram for explaining the above.
FIG. 2 schematically shows a cross-sectional view and a top view of an SFET.

FIG. 12A is a sectional view of a MOSFET.
It is an example. In FIG. 12A, the MOSFET is
Field oxidation for forming a substrate 10 and an element isolation region
The film 12, the gate oxide film 14, the polysilicon film 16 and the
Gusten silicide (WSi _Two) Gate made of film 18
Electrode 20, sidewall 22, source 24, drain
26, in this case M divided into four parts.
OSFETs are formed in parallel, and although not shown, each
The source 24, the drain 26 and the gate electrode 20 are respectively
And connected together to form one MOSFET as a whole
doing. In FIG. 12 (A), the source 24 other than both ends,
Rain 26 is common to adjacent MOSFETs on both sides.
ing.

FIG. 12B shows the MOSFE of FIG.
It is a top view of T. Here, each MOS divided into a plurality
Assuming that the gate width of the FET is the finger length (Wf), the gate width (W) of the divided MOSFET as a whole can be expressed by the following equation.

[0010]

## EQU00002 ## W = Wf.times.number of gates (n) (2) In the prior art described in the above document, the gate resistance is reduced by keeping the gate width W constant and shortening the finger length Wf. . When the gate resistance (Rg) is expressed using the finger length, the following equation is obtained.

[0011]

Rg = ρsWf / Lg (3) where ρs is the area resistance of the gate electrode, and Lg is the gate length. Equation (3) shows that the gate resistance can be reduced by shortening the finger length Wf.

In the above document, the gate width of the entire divided MOSFET is set to W = 20 μm, and the finger length Wf
Are 20 μm and 5 μm. When the finger length Wf is 5 μm, the number of gates is four.

NMOS FE having a gate length Lg of 0.2 μm
At T, the maximum oscillation frequency fmax is such that the finger length is 5μ.
40GHz for m, 15G for finger length of 20μm
Hz, and when the finger length becomes 5 μm, 2
The maximum oscillation frequency fmax increases up to three times or more of the case of 0 μm.

Further, the above document proposes to use titanium silicide (TiSi ₂ ) instead of tungsten silicide (WSi ₂ ) in order to reduce gate resistance. By doing so, the maximum oscillation frequency f
The ratio fmax / f _T Gayori the max and cutoff frequency f _T indicates that increased.

[0015]

However, in the prior art described above, the gate resistance Rg can be reduced, but the reduction of the ratio (Cdb / Cgs) between the drain junction capacitance and the gate-source capacitance is required. because it can not be performed, fmax / f _T value enough, it is impossible to increase enough the MOSFET operation at high frequencies, there is a problem that can not be improved.

Further, when the gate resistance is further reduced by shortening the finger length of the gate electrode of the divided MOSFET as in the above-described prior art, the peripheral region of the source and the drain increases, so that the parasitic capacitance is increased. Therefore, there has been a problem that the operation of the MOSFET in the high frequency region cannot be sufficiently improved.

The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a field-effect transistor having improved high-frequency characteristics and a method of manufacturing the same.

[0018]

According to a first aspect of the present invention, a gate electrode is provided on a semiconductor substrate between a source region and a drain region formed on the semiconductor substrate. It is formed so as to be folded back between the region and the drain region.

In the field effect transistor having the above structure, a gate electrode is formed on the semiconductor substrate between a source region and a drain region formed on the semiconductor substrate so as to be folded back between the source region and the drain region. Accordingly, the gate width W within the finger length of the gate electrode can be increased, and the drain area (the area occupied by the drain region in the semiconductor substrate) can be reduced. Therefore, the drain junction capacitance at the unit gate width can be reduced, that is, the ratio (Cdb / Cgs) of the drain junction capacitance to the gate-source capacitance can be reduced, and the maximum oscillation frequency fmax and cutoff frequency f _T
It is possible to increase the ratio fmax / f _T and allows MOSFET operation at higher frequency regions.

According to a second aspect of the present invention, a gate electrode is folded between the source region and the drain region on the semiconductor substrate between the source region and the drain region formed on the semiconductor substrate, and It is characterized by being formed so as to surround the drain region.

In the field effect transistor having the above structure, the gate electrode is folded between the source region and the drain region on the semiconductor substrate between the source region and the drain region formed on the semiconductor substrate, and By forming so as to surround the region, the gate width W within the finger length of the gate electrode can be increased and the drain area can be reduced as in the first aspect of the present invention. The drain junction capacitance in the width can be reduced, that is, the ratio of the drain junction capacitance to the gate-source capacitance (Cdb / Cgs)
Can be reduced, it is possible to increase the ratio fmax / f _T of the maximum oscillation frequency fmax and the cut-off frequency f _T, it is possible to MOSFET operation at higher frequency regions.

According to a third aspect of the present invention, in the field effect transistor according to any one of the first and second aspects, the semiconductor device is provided on the semiconductor substrate between a source region and a drain region formed in the semiconductor substrate. A low-resistance metal film is formed so as to be in contact with at least the entire upper surface of the folded gate electrode.

In the field effect transistor having the above structure, tungsten (W) is formed so as to be in contact with at least the entire upper part of the folded gate electrode formed on the semiconductor substrate between the source region and the drain region formed on the semiconductor substrate. ), The gate resistance can be made very small. Also, the gate electrode is folded back in the same manner as in the first and second aspects of the invention.
The drain area can be reduced, and the drain junction capacitance per unit gate width can be reduced, that is, the ratio of the drain junction capacitance to the gate-source capacitance (Cdb
/ Cgs) can be reduced, and the maximum oscillation frequency fma
it is possible to increase the ratio fmax / f _T of the x and the cut-off frequency f _T, it is possible to MOSFET operation at higher frequency regions.

According to a fourth aspect of the present invention, the source is formed on the semiconductor substrate between the region where the source is formed and the region where the drain is formed on the semiconductor substrate via the first insulating film. A first step of forming a conductive film serving as a gate electrode so as to be folded between a region to be formed and a region in which a drain is formed, and forming a shallow junction source region and a drain region in the semiconductor substrate. A second step of performing ion implantation, and after forming a second insulating film of the same material as the first insulating film on the semiconductor substrate including the conductive film, performing an etch back to remove the conductive film. A third step of forming a supporting sidewall, and ion implantation for forming a shallow junction source region and a drain region formed in the semiconductor substrate into a deep junction; A fourth step of performing a heat treatment for electrically activating the drain region; and a third insulating layer made of the same material as the first and second insulating films on the surface of the semiconductor substrate including the conductive film having the sidewalls. A fifth step of forming a film, and applying an organic glass having an etching rate substantially equal to that of the third insulating film on the third insulating film, and then performing a heat treatment to thereby form a surface of the third insulating film. A sixth step of flattening the third insulating film, and a seventh step of performing etch-back on the third insulating film planarized in the sixth step to expose a surface of the conductive film from the third insulating film. Forming a low-resistance metal film on the surface of the conductive film and the surface of the third insulating film, the surfaces of which are exposed in the seventh step, and performing patterning on the upper surface of the conductive film and the conductive film. Forming a low-resistance metal film in a peripheral region of the film; Comprising the step.

In the method of manufacturing a field effect transistor having the above structure, a gate electrode is formed on the semiconductor substrate between the source region and the drain region formed on the semiconductor substrate so as to be folded, and the upper surface of the gate electrode and since so as to form a low-resistance metal film such as tungsten (W) in contact with the peripheral area of the gate electrode, Hakare to reduce the gate resistance and the drain junction capacitance, the ratio of the maximum oscillation frequency fmax and the cut-off frequency f _T it is possible to increase the fmax / f _T, more MOSFET operation in a high frequency region can be field effect transistor is obtained.

According to a fifth aspect of the present invention, the source is formed on the semiconductor substrate between the region where the source is formed and the region where the drain is formed on the semiconductor substrate via the first insulating film. A conductive film serving as a gate electrode is formed so as to be folded between a region where a drain is formed and a region where a drain is formed, and the etching rate is higher on the upper surface of the conductive film than the first insulating film. A first step of forming a second insulating film formed of a material, a second step of performing ion implantation for forming a source region and a drain region having a shallow junction in the semiconductor substrate, and the conductive film And forming a third insulating film of the same material as the first insulating film on the semiconductor substrate including the portion where the second insulating film is laminated, and then performing an etch back to form the conductive film and the second insulating film. Supports the part where the insulating film is laminated A third step of forming sidewalls, and ion implantation for forming deep junctions in the shallow junction source and drain regions formed in the semiconductor substrate. A fourth step of performing a heat treatment for electrically activating, and first and third steps on a semiconductor substrate including a portion where the conductive film having the sidewall and the second insulating film are stacked.
A fifth step of forming a fourth insulating film of the same material as that of the fourth insulating film, and applying an organic glass having an etching rate substantially equal to that of the fourth insulating film on the fourth insulating film; Performing a step of flattening the surface of the fourth insulating film, and performing etch-back on the fourth insulating film planarized in the sixth step to form the second insulating film. A seventh step of exposing the surface of the second insulating film from the fourth insulating film; and performing wet etching on the second insulating film and the fourth insulating film, the surfaces of which are exposed in the seventh step. An eighth step of removing the insulating film, and the conductive step in which the surface is exposed at the bottom surface of the concave portion formed in the fourth insulating film by removing the second insulating film in the eighth step. Forming a low-resistance metal film on the film surface and the fourth insulating film surface, The conductive film and are electrically connected by performing ring includes a ninth step of forming a low-resistance metal film on top and its peripheral region of the conductive film.

In the method of manufacturing a field-effect transistor having the above structure, a gate electrode is formed on the semiconductor substrate between the source region and the drain region formed on the semiconductor substrate so as to be folded, and the upper surface of the gate electrode and A low-resistance metal film such as tungsten (W) is formed so as to be in contact with a peripheral region of the gate electrode, and an oversized portion of the low-resistance metal film formed on the gate electrode from the upper surface of the gate electrode (from an upper portion of the gate electrode). Since the distance between the drain region and the surface of the semiconductor substrate at the protruding portion is increased, the gate resistance and the drain junction capacitance of the gate electrode can be reduced, and the low resistance metal film and the source region or the drain region can be reduced. The gate-source capacitance Cgs and the gate-drain capacitance Cgd, which are parasitic capacitances generated between the region and It can be reduced. For this reason,
The maximum oscillation frequency fmax and the ratio fmax of the cut-off frequency f _T /
Since f _T can be increased, a field effect transistor capable of operating a MOSFET in a higher frequency region can be obtained.

[0028]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 schematically shows a plane configuration of a field-effect transistor (MOSFET) according to a first embodiment of the present invention.

The MOSFET shown in FIG. 1A includes a gate electrode 30, a source region 32, and a drain region 34. The gate electrode 30 is provided between a source region 32 and a drain region 34 formed on a semiconductor substrate. Are folded a plurality of times (9 times in the example of FIG. 1A) at the rectangular folded portion 31 to form a zigzag shape.

Although sidewalls are actually formed on the gate electrode 30, they are omitted in the drawings for convenience of explanation. Thus, the source region 32 and the drain region 34
The gate width W within the finger length Wf of the gate electrode 30 can be increased by forming the gate electrode 30 on the semiconductor substrate so as to be folded a plurality of times between the two. In the MOSFET having the gate electrode having the shape shown in FIG. 1A, the area occupied by the source region and the drain region in the semiconductor substrate is made smaller than that of the MOSFET having the normal linear gate electrode (see FIG. 2C). Therefore, the source junction capacitance and the drain junction capacitance can be significantly reduced.

The shape of the gate electrode 30 of the MOSFET shown in FIG. 1A is folded at a rectangular folded portion 31. When the gate electrode 30 having this shape is formed by a lithography technique such as photolithography, a line is formed. Since it is difficult to form a thin rectangular pattern at right angles, FIG.
The folded portion 31 of the gate electrode 30 is formed in a polygonal shape as shown in FIG.
It is desirable that the 0-turned portion 31 is formed in a circular shape.

Since the source junction capacitance and the drain junction capacitance are respectively proportional to the area occupied by the source region and the drain region in the semiconductor substrate, the area of the drain region of the MOSFET having the folded gate electrode shown in FIG. The advantage in the case where the shape of the electrode is a folded shape will be described. Since the calculation of the area of the source region is the same as the calculation of the drain region, only the calculation of the drain region will be described below. For simplicity, a MOS having a gate electrode 30 shown in FIG.
The area of the drain region 34 is calculated for the FET.

FIG. 2A shows the MOSF shown in FIG.
An example of the dimension of each part of ET is shown. FIG. 2 (A)
The finger length Wf of the gate electrode 30 is 10 μm.
m, the gate length Lg is 0.2 μm, and the turnback length Lz is 2.
0 μm, and the folded width Wz was 0.8 μm. Further, the distance Li between the gate electrode 30 and the field edge is set to 2.0 μm.
m.

The substantial gate width W of the MOSFET shown in FIG. 2A is 24 μm (the corner portion (FIG. 2)
(A corner portion 30C) of the gate electrode 30 that is bent at a right angle shown in FIG. 3B is not included in the calculation.

FIG. 2 shows a plan view of a normal MOSFET having a gate electrode having a linear shape and an equivalent gate width.
It is shown in (C). The area of the drain region 34 of each of the MOSFETs shown in FIGS.
2A is 27.2 μm ^{2 in} the MOSFET shown in FIG.
A 48 [mu] m ² in MOSFET (C), the 2
By using the folded gate electrode shown in FIG. 3A, the area of the drain region can be reduced to almost half as compared with a MOSFET having a normal linear gate electrode. For this reason, by making the shape of the gate electrode a folded shape, a MOSF having an ordinary linear gate electrode is formed.
It can be seen that the drain junction capacitance Cdb can be reduced to about half that of ET. Similarly, the source junction capacitance can be reduced to about half as compared with a MOSFET having a normal linear gate electrode by making the shape of the gate electrode a folded shape.

Further, the numerical values in the above description are just examples, and the unit gate width Wz can be increased by further increasing the folded length Lz of the gate electrode 30 or further decreasing the folded width Wz of the gate electrode 30. It is possible to reduce the drain junction capacitance per unit.

Field effect according to the first embodiment of the present invention
According to the transistor (MOSFET), the semiconductor substrate
The semiconductor between the formed source and drain regions;
A gate electrode on the body substrate, the source region and the drain region
The gate electrode is formed by folding back
Increase the gate width W within the finger length of the pole
And the drain area (the drain on the semiconductor substrate)
Area occupied by the region) can be reduced. did
Therefore, the drain junction capacitance at the unit gate width is reduced.
The drain junction capacitance and the gate
The ratio of capacitance between sources (Cdb / Cgs) can be reduced.
The maximum oscillation frequency fmax and the cutoff frequency f _TAnd the ratio fma
x / f_THigher frequency area
MOSFET operation in the region.

Next, FIG. 3 shows a schematic plan configuration of a field effect transistor (MOSFET) according to a second embodiment of the present invention.

The MOSFET shown in FIG.
0, a source region 32 and a drain region 34, and the gate electrode 30 is folded in a zigzag manner a plurality of times at the rectangular folded portion 31 between the source region 32 and the drain region 34. It is formed so as to surround the periphery. Although sidewalls are actually formed on the gate electrode 30, they are omitted in the drawings for convenience of explanation.

The gate electrode 30 of the MOSFET shown in FIG.
Is folded at the rectangular folded portion 31 between the source region 32 and the drain region 34. However, it is difficult to form a right-angled pattern with a small line width by a lithography technique such as photolithography. It is desirable that the folded portion 31 of the gate electrode 30 be formed in a polygonal shape as in the first embodiment, or that the folded portion 31 of the gate electrode 30 be formed in a circular shape.

As described above, the gate electrode 30 is formed so as to be folded between the source region 32 and the drain region 34 and is formed on the semiconductor substrate so as to surround the periphery of the drain region 34. It is possible to increase the gate width W within the finger length Wf of 30. When compared with the same gate width W, the MOSFET having the gate electrode having the shape shown in FIG. 3 is more than the MOSFET having the normal linear gate electrode. Since the area occupied by the drain region in the semiconductor substrate can be reduced, the drain junction capacitance can be significantly reduced.

Since the drain junction capacitance is proportional to the area occupied by the drain region in the semiconductor substrate, the area of the drain region of the MOSFET having the folded gate electrode shown in FIG. 3 is obtained, and the gate electrode 30 is formed into the shape shown in FIG. The superiority of this case will be described.

Although the MOSFET shown in FIG. 3 is different from the MOSFET according to the first embodiment in the shape of the gate electrode, FIG. 4 shows an example of the dimensions of each part with the same name of each part of the MOSFET. In FIG. 4, the finger length Wf of the gate electrode 30 is 5.6 μm, and the gate length Lg.
Is 0.2 μm, the folded length Lz is 2.0 μm, the folded width Wz is 0.8 μm, and the distance Li between the gate and the field edge is 2.0 μm.

The substantial gate width W of the MOSFET shown in FIG. 4 is 24 μm (the corner portion (gate electrode 3
Corners that are bent at a right angle of 0) are not included in the calculation). This value corresponds to the MOSFET according to the first embodiment.
Is the same as the gate width of the gate electrode. In this case, the area occupied by the drain region on the semiconductor substrate, that is, the drain area is 13.4 μm ² , and the M shown in FIG.
The area is less than half the drain area of 27.2 μm ^{2 in} the case of OSFET. In the case of a square gate shape with the same gate width, the length of one side is 6 μm. When the drain region is formed in the inner region surrounded by the square gate electrode, the drain area is 36 μm ² , which is three times or more as large as that when the gate electrode is folded.

As described above, the gate electrode 30 is formed between the source region 32 and the drain region 34 at the rectangular folded portion 31 in a zigzag manner a plurality of times while surrounding the drain region. By doing
Since the effective gate width W can be increased and the area of the drain region can be reduced, the drain junction capacitance Cdb per unit gate width can be reduced.

Further, the numerical values in the above description are just examples, and the drain junction capacitance per unit gate width can be reduced by optimizing the turn length Lz and the turn width Wz of the gate electrode. is there.

According to the field effect transistor (MOSFET) according to the second embodiment of the present invention, a gate electrode is provided on the semiconductor substrate between the source region and the drain region formed on the semiconductor substrate. The gate width W within the finger length of the gate electrode can be increased in the same manner as in the first aspect of the present invention, by forming the gate electrode so as to be folded between the gate electrode and the drain region and to surround the drain region. Since the drain area can be reduced, the drain junction capacitance per unit gate width can be reduced, that is, the ratio (Cdb / Cgs) of the drain junction capacitance to the gate-source capacitance can be reduced, and oscillation frequency fmax and the cut-off frequency f _T
It is possible to increase the ratio fmax / f _T and allows MOSFET operation at higher frequency regions.

Next, FIGS. 5 and 9 show a schematic plan configuration of a field effect transistor (MOSFET) according to a third embodiment of the present invention. MO shown in FIGS. 5A to 5C
The SFET has the same structure as the MOSFET according to the first embodiment of the present invention shown in FIGS. 1A to 1C, and includes a gate electrode 30, a source region 32, and a drain region 34. A low resistance metal film 40 such as tungsten (W) is formed so as to cover the upper surface of the gate 30 formed so as to be folded between the region 32 and the drain region 34 and the entire peripheral region. Although sidewalls are actually formed on the gate electrode 30, they are omitted in the drawings for convenience of explanation. The low resistance metal film 40 and the gate electrode 30 are in direct contact.

As described above, by forming a low resistance metal film for reducing the gate resistance Rg on the entire surface up to the upper surface of the gate electrode 30 and its peripheral region on the upper surface of the gate electrode 30 for actually performing the MOSFET operation. In addition, the resistance value of the gate electrode 30 can be made very small. Also,
Since the operation of the MOSFET is performed only by the gate electrode 30, there is no problem in any shape of the metal film formed on the gate electrode 30.

On the other hand, the MOSFET shown in FIG. 9 has the same structure as the MOSFET according to the second embodiment shown in FIG.
Gate electrode 30, source region 32 and drain region 34
And a gate electrode 3 formed so as to be folded back between the source region 32 and the drain region 34.
In this structure, a low-resistance metal film 50 such as tungsten (W) is formed so as to cover only the upper surface of the zero. Also in this case, similarly to the MOSFET shown in FIG. 5, the resistance value of the gate electrode 30 can be made very small.

Next, a method of manufacturing an N-channel MOSFET (hereinafter, referred to as an NMOSFET) having the structure shown in FIGS. 5 and 9 will be described with reference to FIGS. FIG. 6 and FIG. 7 are process diagrams schematically showing a manufacturing process of the NMOSFET with reference to a cross-sectional view taken along line AA ′ of FIG. However, since FIG. 5A schematically shows the planar structure of the MOSFET, the reference numerals of the respective parts are not the same in FIG. 5A and FIG. 6 and FIG.

First, the impurity concentration is set to 1 × 10 by a known technique.
^On a silicon substrate 60 on which a well of about ¹⁷ cm ^-3 has been formed,
The element isolation region 62 is formed to a thickness of 600 nm. Next, a resist pattern (not shown) serving as a mask for defining an ion implantation region is formed. Only this resist pattern in the region 64 to be under the mask gate, performs punch-through stop implant for suppressing the short channel effect, and the V _T control implantation for controlling a threshold voltage V _T by ion implantation. Punch-through stop implantation, for example, B and acceleration voltage 4 × 10 ¹² cm ^-2 was introduced at 45 KeV, V _T control implantation, for example, boron fluoride (BF ₂₎
By introducing 4 × 10 ¹² cm ⁻² at an acceleration voltage of 90 KeV (FIG. 6A).

Next, a gate oxide film (SiO ₂ film) 66 is formed in an oxidation furnace at 800 ° C. so as to have a thickness of 4 nm. A polysilicon film 68, which is a conductive film, is formed thereon by LPCVD so as to have a thickness of 200 nm, and then a resist pattern (not shown) serving as a mask for patterning a gate electrode is formed. Unnecessary portions of the polysilicon film 68 are etched using the resist pattern as a mask to form a gate electrode 68 having a gate length of about 0.2 μm (FIG. 6B).

Thereafter, As is introduced at 1 × 10 ¹⁵ cm ⁻² at an acceleration voltage of 10 KeV by ion implantation to form a shallow junction source region 70 and a drain region 72 (shallow junction source and drain regions). (FIG. 6 (C)).

Next, TEOS (Tetra Ethyl OrthoSil)
After forming a 200 nm thick SiO ₂ film by CVD using icate: Si (OC ₂ H ₃ ) ₃ ), etch back is performed by reactive ion etching (RIE).
A sidewall 74 that supports the gate electrode 68 is formed (FIG. 6D).

Thereafter, As is introduced at 5 × 10 ¹⁵ cm ⁻² at an acceleration voltage of 40 KeV by ion implantation to form a deep junction source region 76 and a drain region 78 (deep junction source and drain regions). At this time, an impurity (As) is also introduced into the gate electrode 68, and the gate electrode 68 becomes N-type polysilicon. Thereafter, drive-in is performed at 1000 ° C. for 10 seconds using a rapid heating apparatus (RTA) to electrically activate the deep junction source region 76 and drain region 78 (FIG. 6E).

Then, an SiO ₂ film 80 as an insulating film is formed to a thickness of about 400 nm by a CVD method, for example, a normal pressure CVD method, and an organic glass film 82 is coated thereon by a spin-on method to a thickness of about 300 nm. The coating film is cured by heat treatment or the like, and the surface of the SiO ₂ film 80 is planarized (FIG. 6F).

[0058] Then, etch back is performed, the surface of the gate electrode 68 formed of polysilicon film SiO ₂ film 8
It is exposed from 0 (FIG. 6 (G)).

Next, after a tungsten (W) film 31 is formed to a thickness of about 100 nm by a sputtering method, a resist pattern (not shown) serving as a mask for patterning the tungsten (W) film 84 is formed. Using this resist pattern as a mask, tungsten (W) film 8
The unnecessary portion 4 is etched, and a tungsten (W) film 84, which is a low-resistance metal film, is formed on the upper surface of the gate electrode 68 and its peripheral region (FIG. 6H). Therefore, the gate resistance Rg of the gate electrode 68 can be made very small.

As described above, the gate electrode 68 basically has a gate shape of a structure called a T-type gate, but the tungsten (W) film 84 formed on the gate electrode 68 is formed.
Has a length corresponding to the folded width, so that the gate resistance Rg can be made very low as compared with the usual T-shaped gate shape.

Next, the effect of reducing the gate resistance Rg when the MOSFET has the structure shown in FIGS. 5 and 9 will be described. Regarding the gate-shaped MOSFET shown in FIG.
MOSF with and without tungsten (W) film
Calculate the gate resistance Rg of ET.

When a tungsten (W) film is formed so that a protruding portion (oversized portion) having a width of 0.4 μm on one side is formed on the gate electrode 30 having a folded shape shown in FIG. 2A, FIG. The shape shown in FIG. FIG. 8 (A)
WSi ₂ instead of the tungsten (W) film 40 in FIG.
When a 150-nm-thick tungsten polycide film is formed by the film, the gate resistance Rg of the gate electrode 30 of the MOSFET is about 2.2 kΩ, and the tungsten (W) film 40 is formed on the gate electrode 30 with the dimensions shown in FIG. The gate resistance Rg when formed is about 3.6Ω. From this, the resistance value of the gate resistance Rg of the gate electrode 30 when the tungsten (W) film 40 is formed on the gate electrode 30 is the same as that when the tungsten (W) film 40 is not formed on the gate electrode. It can be seen that the resistance value of the gate resistance Rg of the gate electrode is reduced to 1/600.

On the other hand, the gate width W is equivalent (W = 24 μm)
The gate electrode 30 having a normal gate shape shown in FIG.
When a tungsten (W) film 40 is formed so as to provide a protruding portion (oversized portion) having a width of 0.4 μm on one side, the shape shown in FIG. 8B is obtained. In this case, the gate resistance Rg of the gate electrode 30 is 24Ω. This is shown in FIG.
In the MOSFET shown in FIG. 7A, the resistance is six times or more the gate resistance Rg of the folded gate electrode 30.

As described above, when the tungsten (W) film formed on the folded gate electrode is formed so as to protrude from the gate electrode (oversized portion), the adjacent folded film for forming the gate electrode is formed. Since the oversized portion of the tungsten (W) film on the portion is continuously formed without a gap, the oversized portion of the tungsten (W) film is simply provided on the gate electrode, that is, the tungsten (W) film The resistance value of the gate resistance can be greatly reduced as compared with the resistance value of the gate resistance Rg when the oversized portion is provided to be slightly larger in the direction of the gate length Lg of the gate electrode. However, the overlap region between the source or drain region and the tungsten (W) film becomes the gate-source capacitance Cgs and the gate-drain capacitance Cgd, and this overlap region is the same as that of the MOSFET shown in FIG. The area is slightly larger than the MOSFET shown in FIG. For this reason, in the MOSFET shown in FIG. 8A, if the overlap amount on both sides of the overlap region is set to about 0.2 μm on one side, the gate-source capacitance Cgs and the gate-drain capacitance Cgd are reduced. FIG.
The capacitance can be equivalent to that of the MOSFET shown in FIG. In this case, the gate resistance Rg of the gate electrode 30 is 4.2Ω.
It is possible to reduce the resistance value of the gate resistance of the T gate electrode 30 to one fifth or less.

The description of the effect of reducing the gate resistance of the MOSFET having the structure shown in FIG. 9 is omitted, but the gate resistance Rg can be sufficiently reduced similarly to the MOSFET having the structure shown in FIG.

According to the field-effect transistor (MOSFET) and the method of manufacturing the same according to the third embodiment of the present invention, the MOSFET is formed on the semiconductor substrate between the source region and the drain region formed on the semiconductor substrate. Since a low-resistance metal film such as tungsten (W) is formed so as to contact at least the entire upper surface of the folded gate electrode, the gate resistance can be extremely reduced. In addition, since the gate electrode is folded in the same manner as the field-effect transistors according to the first and second embodiments, the drain area can be reduced, and the drain junction capacitance per unit gate width can be reduced. . Therefore, it is possible to increase the ratio fmax / f _T of the maximum oscillation frequency fmax and the cut-off frequency f _T, in the higher frequency region MO
SFET operation becomes possible.

A method for manufacturing an NMOSFET having the structure shown in FIGS. 5 and 9 will be described as a fourth embodiment of the present invention with reference to FIGS. FIG. 6 and FIG.
According to the cross-sectional view taken along the line AA ′ of FIG.
FIG. 3 is a process diagram schematically showing a manufacturing process of the ET. However,
FIG. 5A schematically shows a planar structure of the MOSFET, and therefore, the reference numerals of the respective parts in FIG. 5A and FIG. 10 and FIG.

First, the impurity concentration is set to 1 × 10 by a known technique.
^On a silicon substrate 90 on which a well of about ¹⁷ cm ^-3 has been formed,
An element isolation region 92 is formed to a thickness of 600 nm. Next, a resist pattern (not shown) serving as a mask for defining an ion implantation region is formed. Only this resist pattern in the region 94 to be under the mask gate, performs punch-through stop implant for suppressing the short channel effect, and the V _T control implantation for controlling a threshold voltage V _T by ion implantation. For example, the punch-through stop implanter introduces 4 × 10 ¹² cm ^{−2 of} B at an acceleration voltage of 45 KeV,
_T control implant is, for example, boron fluoride (B
F ₂ ) is introduced at 4 × 10 ¹² cm ⁻² at an acceleration voltage of 90 KeV (FIG. 9A).

Next, a gate oxide film (SiO ₂ film) 96 is formed in an oxidation furnace at 800 ° C. so as to have a thickness of 4 nm. On this, a polysilicon film 98, which is a conductive film, is formed to a thickness of 200 nm by LPCVD. Thereafter, P was accelerated by an ion implantation method at an accelerating voltage of 30 keV to 5 ×
10 ¹⁵ cm ^{−2 is} introduced to form an N-type polysilicon film 98. PSG (Phospho-silicate glass) containing high concentration (20 wt% P ₂ O ₅ or more) of phosphorus (P) is formed on the polysilicon film 98 by a CVD method.
s) The film 100 is formed to a thickness of 250 nm. Thereafter, in order to remove the unnecessary portion of the PSG film 100, a resist pattern (not shown) is formed through a photolithography process, and the PS pattern is formed using this resist pattern as a mask.
The G film 100 is removed by reactive ion etching (RIE). After removing the resist pattern, the PSG film 1
The polysilicon film 98 in the opening is removed by reactive ion etching (RIE) using a chlorine-based gas using 00 as a mask (FIG. 9B).

Thereafter, As is introduced at 1 × 10 ¹⁵ cm ⁻² at an acceleration voltage of 10 KeV by ion implantation to form a source region 102 and a drain region 104 having a shallow junction (a source region and a drain region having a shallow junction). (FIG. 9
(C)).

Next, after a SiO ₂ film 106 having a thickness of 200 nm is formed by a CVD method using TEOS, etch back is performed by reactive ion etching (RIE) to form a sidewall 106 supporting the polysilicon film 98. (FIG. 9D).

Thereafter, As is introduced at 5 × 10 ¹⁵ cm ⁻² at an acceleration voltage of 40 keV by ion implantation to form a deep junction source region 108 and a drain region 110 (deep junction source and drain regions). Thereafter, drive-in is performed at 1000 ° C. for 10 seconds using a rapid heating apparatus (RTA) to electrically activate the deep junction source region 108 and drain region 110 (FIG. 9E).

Next, S is formed by CVD using TEOS.
An iO ₂ film 112 is formed to a thickness of about 600 nm, and an organic glass film 14 is formed thereon by a spin-on method to a thickness of 400 nm.
m, and the applied film is cured by heat treatment or the like.
The surface of the iO ₂ film 112 is flattened (FIG. 9F).

Thereafter, an etch back is performed to
The surface of the PSG film 100 on the film 98 is made of SiO_TwoMembrane 112
To expose. Next, the film thickness 25 on the polysilicon film 98 is formed.
The PSG film 100 having a thickness of 0 nm was formed using a hydrofluoric acid solution.
It is removed by wet etching. PSG film 10
In the case where the phosphorus concentration is high, the etching rate is SiO _Two
It is about 7 times that of the film 112. For this reason, the PSG film 100
At the time of etching, SiO_TwoThe film 112 is 40 nm
Etching is only about the thickness of the silicon substrate 90
Et SiO_TwoThe thickness up to the surface of the film 112 is about 400 nm.
Become. Thus, SiO_TwoThe film 112 and the PSG film 100
PS by etching due to difference in etching rate
G film 100 is removed, polysilicon film (gate electrode)
A recess 116 is formed on the upper surface 98 (FIG. 9G).

Next, after a tungsten (W) film 118 is formed to a thickness of about 100 nm by a sputtering method, a resist pattern (not shown) serving as a mask for patterning the tungsten (W) film 118 is formed. . Unnecessary portions of the tungsten (W) film 118 are etched using this resist pattern as a mask to form a gate electrode 98 having extremely low gate resistance.
(H)).

In the method of manufacturing a field effect transistor according to the fourth embodiment, a tungsten (W) film formed on a gate electrode is formed by forming a PSG film on a polysilicon film serving as a gate electrode. The distance between the gate electrode and the source region or the drain region is increased, and the gate-source capacitance Cgs and the gate-drain capacitance Cgd, which are parasitic capacitances, are obtained by the field-effect transistor manufacturing method according to the third embodiment. The number of transistors can be reduced to about half.

In the MOSFET according to the third embodiment,
Since the tungsten (W) film exists above the source region or the drain region, the gate-source capacitance Cgs
In addition, the gate-drain capacitance (Cgd) is larger than the MOSFETs according to the first and second embodiments. However, since the distance between the tungsten (W) film and the silicon substrate is about 200 nm, if the width of the portion of the tungsten (W) film protruding from the gate electrode is 0.4 μm on one side,
When converted to the amount of overlap between the gate electrode and the drain region when the thickness of the gate oxide film (SiO ₂ film) is 4 nm, it is about 0.008 μm on one side. As shown in the equation (3), the gate-source capacitance Cgs and the gate-drain capacitance Cgd directly affect the cutoff frequency f _T , and therefore are preferably as small as possible.

By using the manufacturing method of the fourth embodiment, the distance between the tungsten (W) film and the silicon substrate becomes about 400 nm, and the gate-source capacitance Cgs and the gate-source capacitance are reduced to half of those of the third embodiment. Drain capacitance Cg
d can be reduced.

According to the method of manufacturing a field effect transistor (MOSFET) according to the fourth embodiment, a low resistance metal film such as tungsten (W) formed on a folded gate electrode protrudes from the gate electrode. Since the distance between the metal film and the silicon substrate can be increased in the portion, the gate-source capacitance Cgs, which is a parasitic capacitance generated between the low-resistance metal film and the source region or the drain region, and the gate-source capacitance. The drain-to-drain capacitance Cgd is
The size can be reduced to about half of the MOSFET according to the embodiment. Therefore, the cutoff frequency f _T can be increased. Also, as in the third embodiment, the gate electrode is formed so as to be folded between the source region and the drain electrode, and a low-resistance metal film such as tungsten (W) is formed on the gate electrode. As in the third embodiment, the gate resistance and the drain junction capacitance of the gate electrode can be reduced.

[0080] Thus, it is possible to increase the ratio fmax / f _T of the maximum oscillation frequency fmax and the cut-off frequency f _T, more MOSFET operation in a high frequency region can be field effect transistor is obtained.

[0081]

As described above, according to the first aspect of the present invention, a gate electrode is provided on the semiconductor substrate between the source region and the drain region formed on the semiconductor substrate. By being formed so as to be folded back with the region, the gate width W within the finger length of the gate electrode can be increased, and the drain area (the area occupied by the drain region in the semiconductor substrate) can be reduced. Therefore, the drain junction capacitance at the unit gate width can be reduced, that is, the ratio of the drain junction capacitance to the gate-source capacitance (Cdb /
Cgs) can be reduced, and the maximum oscillation frequency fmax
It is possible to increase the ratio fmax / f _T of the cut-off frequency f _T and allows MOSFET operation at higher frequency regions.

According to the second aspect of the present invention, a gate electrode is folded back between the source region and the drain region on the semiconductor substrate between the source region and the drain region formed on the semiconductor substrate. In addition, by forming the drain region so as to surround the drain region, the gate width W within the finger length of the gate electrode can be increased, and the drain area can be reduced, as in the first aspect of the present invention. because, it is possible to reduce the drain junction capacitance per unit gate width, that is, the drain junction capacitance and gate-source capacity ratio of the (Cdb / Cgs) can be made small, and the cut-off frequency f _T and the maximum oscillation frequency fmax since the ratio fmax / f _T of it can be increased, allowing MOSFET operation at higher frequency regions.

According to the third aspect of the present invention, at least the entire upper surface of the folded gate electrode formed on the semiconductor substrate between the source region and the drain region formed on the semiconductor substrate is contacted. Since a low-resistance metal film such as tungsten (W) is formed on the substrate, the gate resistance can be extremely reduced. Also, the gate electrode is folded back in the same manner as in the first and second aspects of the invention.
The drain area can be reduced, and the drain junction capacitance per unit gate width can be reduced, that is, the ratio of the drain junction capacitance to the gate-source capacitance (Cdb
/ Cgs) can be reduced, and the maximum oscillation frequency fma
it is possible to increase the ratio fmax / f _T of the x and the cut-off frequency f _T, it is possible to MOSFET operation at higher frequency regions.

According to the fourth aspect of the present invention, the gate electrode is formed on the semiconductor substrate between the source region and the drain region formed on the semiconductor substrate so as to be folded, and the upper surface of the gate electrode is formed. and since so as to form a low-resistance metal film such as tungsten (W) in contact with the peripheral region of the gate electrode, Hakare to reduce the gate resistance and the drain junction capacitance, the maximum oscillation frequency fmax and the cut-off frequency f _T it is possible to increase the ratio fmax / f _T, more MOSFET operation in a high frequency region can be field effect transistor is obtained.

According to the fifth aspect of the present invention, a gate electrode is formed on the semiconductor substrate between the source region and the drain region formed on the semiconductor substrate so as to be folded, and the upper surface of the gate electrode is formed. A low-resistance metal film such as tungsten (W) is formed so as to be in contact with the peripheral region of the gate electrode, and an oversized portion of the low-resistance metal film formed on the gate electrode from the top surface of the gate electrode (from the top of the gate electrode) (A protruding part), the distance between the drain region and the semiconductor substrate surface is formed longer, so that the gate resistance and drain junction capacitance of the gate electrode can be reduced, and the low-resistance metal film and the source region or A gate-source capacitance Cgs and a gate-drain capacitance C, which are parasitic capacitances generated between the gate electrode and the drain region.
gd can be reduced. This makes it possible to increase the ratio fmax / f _T of the maximum oscillation frequency fmax and the cut-off frequency f _T, a MOSFET in the higher frequency region
A field effect transistor capable of performing a T operation is obtained.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a plane configuration of a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of a dimension of each part of the MOSFET shown in FIG.

FIG. 3 is a plan view showing a schematic plan configuration of a field-effect transistor according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram showing an example of a dimension of each part of the MOSFET shown in FIG. 3;

FIG. 5 is a plan view showing an example of a schematic plan configuration of a field-effect transistor according to a third embodiment of the present invention.

FIG. 6 is a process chart showing an example of a manufacturing process of an NMOSFET.

FIG. 7 is a process chart showing an example of a manufacturing process of an NMOSFET.

FIG. 8 is an explanatory diagram showing dimensions of respective portions when a protruding portion is formed on the gate electrode of the MOSFET shown in FIG.

FIG. 9 is a plan view showing another example of the schematic plane configuration of the field-effect transistor according to the third embodiment of the present invention.

FIG. 10 is a process chart showing another example of the manufacturing process of the NMOSFET.

FIG. 11 is a process chart showing another example of the manufacturing process of the NMOSFET.

FIG. 12 is a cross-sectional view and a plan view showing a configuration of a conventional MOSFET.

[Explanation of symbols]

REFERENCE SIGNS LIST 30 gate electrode 32 source region 34 drain region 40 low resistance metal film 60 silicon substrate 62 element isolation region 66 gate oxide film 68 gate electrode 70 shallow junction source region 72 shallow junction drain region 74 sidewall 76 deep junction source region 78 Deep junction drain region 80 SiO ₂ film 82 Organic glass film 84 Tungsten film 100 PSG film

Claims (5)

[Claims] 1. A field effect, wherein a gate electrode is formed on the semiconductor substrate between a source region and a drain region formed on the semiconductor substrate so as to be folded back between the source region and the drain region. Transistor. 2. A method according to claim 1, wherein a gate electrode is formed between the source region and the drain region on the semiconductor substrate between the source region and the drain region.
A field effect transistor formed so as to surround the drain region. 3. A low-resistance metal film is formed so as to be in contact with at least the entire upper surface of a folded gate electrode formed on the semiconductor substrate between a source region and a drain region formed on the semiconductor substrate. The field-effect transistor according to claim 1, wherein: 4. A region where the source is formed and a drain are formed via a first insulating film on the semiconductor substrate between the region where the source is formed and the region where the drain is formed in the semiconductor substrate. A first step of forming a conductive film serving as a gate electrode so as to be folded between the first and second regions, and a second step of performing ion implantation for forming shallow junction source and drain regions in the semiconductor substrate Forming a second insulating film of the same material as the first insulating film on a semiconductor substrate including the conductive film, performing etch back, and forming a sidewall supporting the conductive film. Performing ion implantation for forming a shallow junction source region and a drain region formed in the semiconductor substrate into a deep junction;
A fourth step of subsequently performing a heat treatment for electrically activating the deep junction source and drain regions; and a first and a second insulating film on the surface of the semiconductor substrate including the conductive film having the sidewall. A fifth step of forming a third insulating film of the same material as described above, and applying an organic glass having an etching rate substantially equal to that of the third insulating film on the third insulating film, and then performing a heat treatment. A sixth step of planarizing the surface of the third insulating film; and etching back the third insulating film planarized in the sixth step to remove the surface of the conductive film by the third step. A seventh step of exposing from the insulating film; and forming a low-resistance metal film on the conductive film surface and the third insulating film surface, the surfaces of which are exposed in the seventh step, and performing patterning to form the conductive film. Upper surface of film and peripheral region of conductive film A method for manufacturing a field effect transistor, comprising an eighth step of forming a low resistance metal film on the substrate. 5. A region where the source is formed and a drain are formed on the semiconductor substrate between the region where the source is formed and the region where the drain is formed on the semiconductor substrate via a first insulating film. A conductive film serving as a gate electrode is formed so as to be folded between the first and second insulating films, and a second film formed of a material having an etching rate higher than that of the first insulating film is formed on an upper surface of the conductive film. A first step of forming an insulating film, a second step of performing ion implantation for forming a shallow junction source region and a drain region in the semiconductor substrate, and the conductive film and a second insulating film are stacked After a third insulating film of the same material as the first insulating film is formed on the semiconductor substrate including the etched portion, etch back is performed to remove the portion where the conductive film and the second insulating film are stacked. Form supporting sidewalls A third step, the ion implantation for the deep junction source and drain regions of the shallow junction formed on the semiconductor substrate is performed,
A fourth step of subsequently performing a heat treatment for electrically activating a deep junction source region and a drain region; and a semiconductor including a portion where a conductive film having a sidewall and a second insulating film are stacked. A fifth step of forming a fourth insulating film of the same material as the first and third insulating films on the substrate; and applying an organic glass having an etching rate substantially equal to that of the fourth insulating film to the fourth insulating film. A sixth step of flattening the surface of the fourth insulating film by performing a heat treatment after being applied thereon, and performing an etch-back on the fourth insulating film flattened in the sixth step. A seventh step of exposing a surface of the second insulating film from the fourth insulating film; and a fourth step of exposing a surface of the second insulating film and a fourth step of exposing the surface in the seventh step.
An eighth step of performing wet etching on the first insulating film to remove the second insulating film; and removing the second insulating film in the eighth step to form the fourth insulating film. A low-resistance metal film is formed on the surface of the conductive film and the surface of the fourth insulating film, the surfaces of which are exposed at the bottom surface of the formed recess, and are electrically connected to the conductive film by performing patterning. A method for manufacturing a field-effect transistor, comprising a ninth step of forming a low-resistance metal film on an upper portion of a conductive film and a peripheral region thereof.