CN104241385A - Annular gate field effect transistor with small layout area and manufacturing method thereof - Google Patents
Annular gate field effect transistor with small layout area and manufacturing method thereof Download PDFInfo
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- CN104241385A CN104241385A CN201410490291.7A CN201410490291A CN104241385A CN 104241385 A CN104241385 A CN 104241385A CN 201410490291 A CN201410490291 A CN 201410490291A CN 104241385 A CN104241385 A CN 104241385A
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- 230000005669 field effect Effects 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000002955 isolation Methods 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 230000000694 effects Effects 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 238000005452 bending Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 238000002360 preparation method Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000013461 design Methods 0.000 claims description 5
- 238000013459 approach Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000007521 mechanical polishing technique Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- UBMXAAKAFOKSPA-UHFFFAOYSA-N [N].[O].[Si] Chemical compound [N].[O].[Si] UBMXAAKAFOKSPA-UHFFFAOYSA-N 0.000 claims description 2
- 238000010276 construction Methods 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims 1
- 230000005855 radiation Effects 0.000 abstract description 5
- 239000007772 electrode material Substances 0.000 abstract 2
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
An annular gate field effect transistor with the small layout area comprises a substrate (1), a shallow tank isolation area STI (5) on the substrate, a source area (2), a gate medium (7), a gate electrode material (4) and a drain area (3), wherein the source area (2) is arranged on the substrate and surrounded by the area STI, the gate medium (7) is surrounded by the source area, the gate electrode material (4) covers the gate medium, and the drain area (3) is surrounded by gates. The gate medium (7) has one or two or all the combination modes of folding, nesting and parallel distribution, so that the gate medium (7) has the larger gate width within the smaller area of an active area, wherein the active area comprises the source area, the drain area and a channel area. It is guaranteed that the field effect transistor has the radiation resistance structural characteristic of an annular gate, the gates of the transistor are bent and folded or nested or distributed in parallel, the layout area of the transistor is reduced greatly, and stray capacitance of the source area and the drain area is reduced.
Description
Technical field
The present invention relates to semiconductor integrated circuit radiation effect field, be specifically related to the ring grid field effect transistor with less chip area and preparation method thereof of resistant to total dose, micro-dose.
Background technology
Integrated circuit technique is applied in Aeronautics and Astronautics industry just more and more widely.Along with the development of microelectric technique, the total dose effect being widely used as semiconductor device and micro-dosage effect of shallow groove isolation structure (STI) bring the impact of can not ignore.Total dose effect and micro-dosage effect mainly refer to that device is after high-energy ray or particle radiation, the phenomenons such as off-state leakage current increase, threshold voltage shift, short-channel effect deterioration.These phenomenon Producing reason be due to radiation at oxide (as SiO
2) middle generation oxide-trapped charge, produce interfacial state in oxide/silicon interface, thus the threshold voltage of Effect Field effect transistor, form new current leakage passage between scene effect transistor source and drain, make the performance degradation of field-effect transistor.In scene effect transistor, shallow groove isolation structure is formed primarily of oxide, is one of radiosensitive region.
Ring grid metal-oxide semiconductor fieldeffect transistor is due to its special design feature, and after accumulated dose, micro-dose, sti structure can not introduce charge bleed-off path between source and drain, therefore has good resistant to total dose, micro-dose ability.Ring grid field effect transistor domain of the prior art as shown in Figure 1, comprising: substrate 01; Shallow trench isolation region (STI) 05 on substrate, the source region 02 surrounded on substrate and by STI region; Surrounded by source region, and ringwise gate medium 07; Cover the gate material 04 on gate medium; And the drain region 03 at center is enclosed in by grid.
Although ring gate device has the ability of good anti-integral dose radiation, micro-dose, it is very limited in actual use.One of reason is because ring gate device is compared with traditional conventional device, and when channel width W is identical, shared chip area is larger.Traditional devices chip area is directly proportional to W, the chip area of ring gate device then with W
2be directly proportional.Therefore the inferior position of ring gate device on chip area becomes more remarkable when W increases.The use of ring gate device of this drawbacks limit, especially in RF application, excessive chip area will cause parasitic capacitance too large, thus device cannot effectively work.
Summary of the invention
In order to overcome problems of the prior art, the present invention proposes several ring grid field effect transistor with less chip area.
Technical scheme provided by the invention is as follows:
Scheme 1: a kind of ring grid field effect transistor with less chip area, is characterized in that, described ring grid field effect transistor comprises: substrate 1; Shallow trench isolation region STI5 on substrate; The source region 2 surrounded on substrate and by STI region; By the gate medium 7 that source region surrounds; Cover the gate material 4 on gate medium; And the drain region 3 at center is enclosed in by grid;
Wherein, described gate medium 7 have folding, nested or side by side one of these three kinds of structures two or three combination in any, make gate medium 7 have larger grid width under less active region area, wherein active region area comprises source region, drain region and channel region (channel region area is substantially identical with grid area).
Scheme 2: the ring grid field effect transistor as described in scheme 1, is characterized in that, described foldable structure, gate medium 7 joins end to end formation closed figures, and two relative spring complications build up square sawtooth or waveform, as shown in Figure 4.
Scheme 3: the ring grid field effect transistor as described in scheme 1, is characterized in that, described nested structure, drain region 3 surrounds second layer gate medium 7 ' and gate material 4 '; And by second layer source region 2 ' that gate medium 7 ' surrounds; This structure can according to source/drain/source/drain/... mode carry out multilayer nest, as shown in Figure 5.
Scheme 4: the ring grid field effect transistor as described in scheme 1, is characterized in that, described parallel construction, gate medium 7 to be squarely tied together for a series of, as shown in Figure 7.
Scheme 5: the ring grid field effect transistor as described in scheme 1, is characterized in that, described substrate is body silicon or SOI.
Scheme 6: the ring grid field effect transistor as described in scheme 1, is characterized in that, described gate medium silicon oxide sio
2or nitrogen-oxygen-silicon SiON.
Scheme 7: the ring grid field effect transistor as described in scheme 1, is characterized in that, described gate medium high-k gate dielectric (dielectric constant K>3.9, as: HfSiO
2) material.
Scheme 8: the ring grid field effect transistor as described in scheme 2, is characterized in that, on the basis of the ring gate transistor of traditional square grid, repeatedly bending fold independently can be carried out in four limits of grid; Fig. 2 is one group of opposite side bending fold result once, forms two zigzag to domain central concave; Opposite side folds for n time and will produce 2n the zigzag to domain central concave or waveform.
Scheme 9: the ring grid field effect transistor as described in scheme 2, it is characterized in that, the turning that grid exist after bending can be right angle (as Fig. 4 (a)), knuckle (Fig. 4 (b)) or fillet (Fig. 4 (c)), two limit angulations at composition angle can from 90 ° to being less than 180 °, right angle is when 90 °, namely angle increase is transitioned into polygon knuckle from right angle gradually, final to fillet 180 °, angle is larger, is more conducive to the highfield effect improving corner.
, there is corner and have multiple design in scheme 10: the ring grid field effect transistor as described in scheme 3, is characterized in that, Fig. 6 is the schematic diagram of certain one deck grid, and turning can consist of 90 ° of angles by two limits; Or be made up of polygon, polygonal each angle is all greater than 90 °; Or circular 180 ° of turning infinite approach, reduce highfield effect with this.
, there is corner and have multiple design in scheme 11: the ring grid field effect transistor as described in scheme 4, is characterized in that, Fig. 8 is the schematic diagram of grid, and turning can consist of 90 ° of angles by two limits; Or be made up of polygon, polygonal each angle is all greater than 90 °; Or circular 180 ° of turning infinite approach, reduce highfield effect with this.
Scheme 12: a kind of preparation method with the ring grid field effect transistor of less chip area, is characterized in that, comprise the steps:
1) on substrate heat growth silicon dioxide and chemical vapor deposition silicon nitride as mask;
2) utilize photoetching technique etching silicon dioxide and silicon nitride, and etch silicon substrate-like becomes groove;
3) deposit STI oxide layer, and carry out planarizing process with chemical Mechanical Polishing Technique effects on surface;
4) doping is carried out to raceway groove and form doped region, heat growth layer of silicon dioxide gate medium, depositing polysilicon grid;
5) utilize photoetching technique to carry out photoetching to grid, form grid;
6) to source drain ion implantation.
Under radiation environment, accumulated dose or micro-dose effect will introduce trap positive charge in sti structure.For ring grid field effect transistor of the prior art, because the trap positive charge in sti structure and channel region isolate, therefore parasitic conductive passage can not be produced in channel region.For the ring grid field effect transistor that the present invention proposes, still maintain this advantage.Meanwhile, the ring grid field effect transistor in the present invention saves chip area more, grid has been carried out bending fold, nested or laid out in parallel, can share source and drain between grid, and efficiently reduced source-drain area parasitic capacitance.Approximate calculation shows, under ensureing the prerequisite that raceway groove overall width W is constant, when using folding scheme, grid symmetric curvature is folding once, and active region area reduces about 40%.Symmetric curvature folding twice, active region area reduces about 50%.The number of times of bending fold is more, and active region area is less, can select according to the actual requirements.
To sum up, advantage of the present invention has been carried out bending fold, nested or laid out in parallel to the grid of device, has greatly been reduced the chip area of device, reduced source-drain area parasitic capacitance while being to ensure that field-effect transistor has the gate-all-around structure feature of Flouride-resistani acid phesphatase.
Accompanying drawing explanation
Fig. 1 is the structural representation of ring grid field effect transistor in prior art;
Fig. 2 to Fig. 9 is the schematic diagram with the ring grid field effect transistor embodiment of less chip area of the present invention;
Figure 10 to Figure 14 is the flow chart that preparation has the ring grid field effect transistor embodiment of less chip area, and often figure left side is profile, and right side is vertical view.
Wherein:
1-substrate; 2-source electrode; 3-drains; 4-grid; 5-STI district; 6-active area; 7-gate medium; 8-earth silicon mask; 9-photoresist; 10-silicon nitride mask; 11-P type doped region.
Embodiment
Below in conjunction with accompanying drawing, describe embodiments of the present invention in detail.
For scheme one, as shown in Figure 2, ring grid field effect transistor of the present invention comprises: substrate (body silicon or PDSOI) 1; Shallow trench isolation region (STI) 5 on substrate; The source region 2 surrounded on substrate and by STI region; By the gate medium 7 that source region surrounds, gate medium joins end to end formation closed figures, but relative two spring complications build up square sawtooth or waveform; Cover the gate material 4 on gate medium; And the drain region 3 at center is enclosed in by grid.Compared with the ring grid field effect transistor of prior art in Fig. 1, the present invention still effectively can reduce total extreme, micro-dosage effect to the impact of field-effect transistor.Further, while the larger grid width of guarantee, effectively reduce the chip area of device, reduce the parasitic capacitance of source-drain area.
Preparation method's embodiment of ring grid field effect transistor of the present invention is as follows:
1) at substrate 1 (P, N-type silicon substrate or SiO
2substrate etc.) go up heat growth silicon dioxide 8 with CVD (chemical vapor deposition) silicon nitride 10 as mask, as Figure 10;
2) utilize photoetching technique etching silicon dioxide 8 and silicon nitride 10, and etch silicon substrate 1 forms groove as shown in figure 11,9 is photoresist;
3) deposit STI oxide layer 5, and carry out planarizing process with chemical Mechanical Polishing Technique effects on surface;
4) to raceway groove carry out doping formed P ?type doped region 11, heat growth layer of silicon dioxide gate medium 7, depositing polysilicon grid 4 is as Figure 12;
5) utilize photoetching technique to carry out photoetching to grid 4,6 is active area, forms figure as shown in fig. 13 that;
6) source electrode 2 is drained 3 ion implantations, form figure as shown in figure 14.
It is finally noted that, the object publicizing and implementing mode is to help to understand the present invention further, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various substitutions and modifications are all possible.Therefore, the present invention should not be limited to the content disclosed in embodiment, and the scope that the scope of protection of present invention defines with claims is as the criterion.
Claims (12)
1. have a ring grid field effect transistor for less chip area, it is characterized in that, described ring grid field effect transistor comprises: substrate (1); Shallow trench isolation region STI (5) on substrate; The source region (2) surrounded on substrate and by STI region; By the gate medium (7) that source region surrounds; Cover the gate material (4) on gate medium; And the drain region (3) at center is enclosed in by grid;
Wherein, described gate medium (7) have folding, nested or side by side one of these three kinds of structures two or three combination in any, make gate medium (7) have larger grid width under less active region area, wherein active region area comprises source region, drain region and channel region.
2. ring grid field effect transistor as claimed in claim 1, is characterized in that, described foldable structure, and gate medium (7) joins end to end formation closed figures, and two relative spring complications build up square sawtooth or waveform.
3. ring grid field effect transistor as claimed in claim 1, it is characterized in that, described nested structure, drain region (3) surround second layer gate medium (7 ') and gate material (4 '); And by second layer source region (2 ') that gate medium (7 ') surrounds; This structure can according to source/drain/source/drain/... mode carry out multilayer nest.
4. ring grid field effect transistor as claimed in claim 1, is characterized in that, described parallel construction, and gate medium (7) to be squarely tied together for a series of.
5. ring grid field effect transistor as claimed in claim 1, it is characterized in that, described substrate is body silicon or SOI.
6. ring grid field effect transistor as claimed in claim 1, is characterized in that, described gate medium silicon oxide sio
2or nitrogen-oxygen-silicon SiON.
7. ring grid field effect transistor as claimed in claim 1, is characterized in that, described gate medium high-k gate dielectric material.
8. ring grid field effect transistor as claimed in claim 2, it is characterized in that, on the basis of the ring gate transistor of traditional square grid, repeatedly bending fold independently can be carried out in four limits of grid.
9. ring grid field effect transistor as claimed in claim 2, it is characterized in that, the turning that grid exist after bending can be right angle, knuckle or fillet, two limit angulations at composition angle can from 90 ° to being less than 180 °, right angle is when 90 °, namely angle increase is transitioned into polygon knuckle from right angle, gradually finally to fillet 180 °.
10. ring grid field effect transistor as claimed in claim 3, it is characterized in that there is corner and have multiple design, turning can consist of 90 ° of angles by two limits; Or be made up of polygon, polygonal each angle is all greater than 90 °; Or circular 180 ° of turning infinite approach.
11. ring grid field effect transistors as claimed in claim 4, is characterized in that there is corner and have multiple design, and turning can consist of 90 ° of angles by two limits; Or be made up of polygon, polygonal each angle is all greater than 90 °; Or circular 180 ° of turning infinite approach.
12. 1 kinds of preparation methods with the ring grid field effect transistor of less chip area, is characterized in that, comprise the steps:
1) on substrate heat growth silicon dioxide and chemical vapor deposition silicon nitride as mask;
2) utilize photoetching technique etching silicon dioxide and silicon nitride, and etch silicon substrate-like becomes groove;
3) deposit STI oxide layer, and carry out planarizing process with chemical Mechanical Polishing Technique effects on surface;
4) doping is carried out to raceway groove and form doped region, heat growth layer of silicon dioxide gate medium, depositing polysilicon grid;
5) utilize photoetching technique to carry out photoetching to grid, form grid;
6) to source drain ion implantation.
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| CN201410490291.7A CN104241385A (en) | 2014-09-23 | 2014-09-23 | Annular gate field effect transistor with small layout area and manufacturing method thereof |
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|---|---|---|---|
| CN201410490291.7A CN104241385A (en) | 2014-09-23 | 2014-09-23 | Annular gate field effect transistor with small layout area and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104934475A (en) * | 2015-03-12 | 2015-09-23 | 西安电子科技大学 | Gate-all-around anti-irradiation MOS field effect transistor based on 65 nm technology |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1187694A (en) * | 1997-09-04 | 1999-03-30 | Oki Electric Ind Co Ltd | Field-effect transistor and its manufacture |
| JP2000012848A (en) * | 1998-06-23 | 2000-01-14 | Canon Inc | Semiconductor device |
| JP2008130581A (en) * | 2006-11-16 | 2008-06-05 | Renesas Technology Corp | Semiconductor device, and radio communication apparatus having the same |
| CN102142425A (en) * | 2010-01-29 | 2011-08-03 | 三洋电机株式会社 | Semiconductor device |
-
2014
- 2014-09-23 CN CN201410490291.7A patent/CN104241385A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1187694A (en) * | 1997-09-04 | 1999-03-30 | Oki Electric Ind Co Ltd | Field-effect transistor and its manufacture |
| JP2000012848A (en) * | 1998-06-23 | 2000-01-14 | Canon Inc | Semiconductor device |
| JP2008130581A (en) * | 2006-11-16 | 2008-06-05 | Renesas Technology Corp | Semiconductor device, and radio communication apparatus having the same |
| CN102142425A (en) * | 2010-01-29 | 2011-08-03 | 三洋电机株式会社 | Semiconductor device |
Non-Patent Citations (1)
| Title |
|---|
| A. GIRALDO ET AL: ""Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout"", 《SOLID-STATE ELECTRONICS》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104934475A (en) * | 2015-03-12 | 2015-09-23 | 西安电子科技大学 | Gate-all-around anti-irradiation MOS field effect transistor based on 65 nm technology |
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