JPH11317665A - A/d converting device - Google Patents

A/d converting device

Info

Publication number
JPH11317665A
JPH11317665A JP12318998A JP12318998A JPH11317665A JP H11317665 A JPH11317665 A JP H11317665A JP 12318998 A JP12318998 A JP 12318998A JP 12318998 A JP12318998 A JP 12318998A JP H11317665 A JPH11317665 A JP H11317665A
Authority
JP
Japan
Prior art keywords
value
digital signal
converter
storage device
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12318998A
Other languages
Japanese (ja)
Other versions
JP3965773B2 (en
Inventor
Goji Honda
剛司 本田
Itsuo Igarashi
逸夫 五十嵐
Koji Murase
孝治 村瀬
Yasuhiro Okada
康弘 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12318998A priority Critical patent/JP3965773B2/en
Publication of JPH11317665A publication Critical patent/JPH11317665A/en
Application granted granted Critical
Publication of JP3965773B2 publication Critical patent/JP3965773B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PROBLEM TO BE SOLVED: To detect the indefinitness of a digital value which is caused by the failure of an A/D converting part, in addition to disconnection detection on an analog detection signal side. SOLUTION: An A/D converting part 4 performs conversion at a fixed timing obtained from a timer device 5. An operation and storage device 6 successively stores a digital signal value that is its output signal and also calculates the difference between a digital signal value stored the last time and a digital signal value of this time. A deciding device 8 decides whether the difference of the digital signal values is within the set values stored in a setting device 7 with high accuracy in addition to whether the digital value of an analog signal is within an operation area. Thus, an A/D converting device which is highly safe can be obtained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はアナログ信号をディ
ジタル信号に変換するA/D変換装置に関する。
The present invention relates to an A / D converter for converting an analog signal into a digital signal.

【0002】[0002]

【従来の技術】従来、A/D変換装置は、アナログ信号
側回路のHi故障あるいはLO故障を防止する為に、ア
ナログ信号側回路が通常動作をしている時は、(電源電
圧−α)と(グランド+β)間の電圧で動作する様に設
計し、A/D変換結果がαからβ間に有る事を確認する
安全対策を行っていた。
2. Description of the Related Art Conventionally, in order to prevent a Hi failure or an LO failure in an analog signal side circuit, an A / D converter normally uses (power supply voltage-α) when the analog signal side circuit is operating normally. And (ground + β), and safety measures were taken to confirm that the A / D conversion result was between α and β.

【0003】図2に従来のA/D変換装置の構成を示し
ており、1はA/D変換部であり、アナログ値を入力
し、ディジタル値として次段に出力する。2はディジタ
ル基準電圧装置である。(電源電圧)から(電源電圧−
α)の一定領域、および、(グランド電圧)から(グラ
ンド電圧+β)の一定領域を異常領域として、また、β
からαの間を動作領域として、あらかじめ前述した各値
をディジタル値に変換した値を記憶している。3は判定
装置でありA/D変換部1の出力をディジタル基準電圧
装置2の基準値と比較する。
FIG. 2 shows the configuration of a conventional A / D converter. Reference numeral 1 denotes an A / D converter, which receives an analog value and outputs it as a digital value to the next stage. 2 is a digital reference voltage device. (Power supply voltage) to (power supply voltage-
α) and a constant region from (ground voltage) to (ground voltage + β) as abnormal regions.
The values obtained by converting the above-described values into digital values in advance are stored, with the range between .alpha. Reference numeral 3 denotes a determination device that compares the output of the A / D converter 1 with the reference value of the digital reference voltage device 2.

【0004】そして、A/D変換部1の出力値が動作領
域であれば、前述のA/D変換部1の出力を、異常領域
であれば異常の旨を次段に出力する様構成されている。
上記の様に、このA/D変換装置では、アナログ信号側
の回路が正常動作する領域と、回路故障時の異常領域が
あらかじめ求められている。そして、その領域をディジ
タル値としてディジタル基準電圧装置2に記憶させる。
その値を基に、判定装置3で比較する事により、アナロ
グ信号側の異常を検出していた。
When the output value of the A / D converter 1 is in the operating range, the output of the A / D converter 1 is output to the next stage. ing.
As described above, in this A / D converter, the region where the circuit on the analog signal side operates normally and the abnormal region at the time of circuit failure are obtained in advance. Then, the area is stored in the digital reference voltage device 2 as a digital value.
Abnormalities on the analog signal side were detected by comparing the values with the determination device 3 based on the values.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記構
成ではA/D変換部1の故障や、A/D変換部1と接続
する判定装置3の間の断線等により、ディジタル値が不
定となる。その値が、ディジタル基準電圧装置2に記憶
した動作領域に入れば、アナログ信号を検出したい広い
領域でアナログ信号の異常検出ができないという課題を
有していた。
However, in the above configuration, the digital value becomes indeterminate due to a failure of the A / D converter 1 or a disconnection between the A / D converter 1 and the judging device 3 connected thereto. If the value falls within the operation area stored in the digital reference voltage device 2, there is a problem that analog signal abnormality cannot be detected in a wide area where an analog signal is to be detected.

【0006】[0006]

【課題を解決するための手段】この課題を解決するため
に本発明は、従来のA/D変換装置に加え、タイマー装
置により得られる一定タイミングで、A/D変換装置か
ら出力されるディジタル信号値を逐時記憶し、また、前
回記憶のディジタル信号値との差を求める演算・記憶装
置の演算結果が、あらかじめ設定装置に記憶してある設
定値に入るかどうかを判定装置で判定する様に構成した
ものである。
In order to solve this problem, the present invention provides a digital signal output from an A / D converter at a constant timing obtained by a timer device in addition to a conventional A / D converter. The value is sequentially stored, and the determination device determines whether the calculation result of the calculation / storage device for calculating the difference from the previously stored digital signal value falls within the set value previously stored in the setting device. It is what was constituted.

【0007】上記発明によれば、アナログ検出信号の変
化が、予想される値以内であるかを判定するので、A/
D変換部の故障や、A/D変換部1と判定装置3間の断
線等により生じるディジタル値の不定を、アナログ信号
を検出している領域内で、精度良く検出することができ
る。
According to the above invention, it is determined whether or not the change in the analog detection signal is within an expected value.
An indefinite digital value caused by a failure of the D conversion unit, a disconnection between the A / D conversion unit 1 and the determination device 3, and the like can be detected with high accuracy in a region where an analog signal is detected.

【0008】[0008]

【発明の実施の形態】本発明の請求項1に記載の発明
は、A/D変換部と、このA/D変換部を設定時間毎に
動作させ、アナログ側の検出信号をディジタル信号に変
換するタイミングを与えるタイマー装置と、前記A/D
変換部と接続し、A/D変換部からのディジタル信号が
出力される度に、その値を記憶するとともに、前回記憶
しているディジタル信号値と今回のディジタル信号値と
の差を求め次段に出力する演算・記憶装置と、この演算
・記憶装置と接続し、その出力と、あらかじめタイマー
装置の設定時間内では変化不可能なアナログ検出信号の
差をディジタル値にした値を設定値として記憶した値と
を比較し、演算・記憶装置の出力が設定値以内の場合は
演算・記憶装置内の今回のディジタル信号値を次段に、
また、設定値より大きい場合は異常信号を次段に出力す
る判定装置を有するものである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, an A / D converter and this A / D converter are operated at set time intervals to convert an analog detection signal into a digital signal. A timer device for giving timing to perform
Each time a digital signal is output from the A / D converter, the value is stored, and the difference between the previously stored digital signal value and the current digital signal value is determined. Connected to this arithmetic and storage device, and stores the difference between the output and the analog detection signal that cannot be changed within the set time of the timer device in advance as a digital value as a set value If the output of the arithmetic and storage device is within the set value, the current digital signal value in the arithmetic and storage device is sent to the next stage.
In addition, a determination device that outputs an abnormal signal to the next stage when the value is larger than the set value is provided.

【0009】そして、タイマー装置により得られる一定
タイミングで、A/D変換部から出力されるディジタル
信号値を逐時記憶し、また前回の記憶のディジタル信号
値との差を求める演算・記憶装置の演算結果があらかじ
め設定装置に記憶してある設定値に入るかどうかを判定
装置で合否判定する。このことにより、アナログ検出信
号の変化が予想される値以内であるかを判定するので、
A/D変換部の故障や、A/D変換部と判定装置間の断
線により生じるディジタル値の不定を、アナログ信号を
検出している領域内で、精度良く検出することができ
る。さらに設定装置内の設定値を小さく設定する事によ
り、前記精度は向上する。
A digital signal value output from the A / D converter is stored at a constant timing obtained by the timer device, and a difference between the digital signal value and the previous stored digital signal value is calculated. The determination device determines whether or not the calculation result falls within a set value stored in the setting device in advance. As a result, it is determined whether the change in the analog detection signal is within the expected value.
A failure of the A / D converter and an indefinite digital value caused by a disconnection between the A / D converter and the determination device can be detected with high accuracy in a region where an analog signal is detected. Further, by setting the set value in the setting device small, the accuracy is improved.

【0010】この発明によると、A/D変換部の故障
や、A/D変換部と判定装置間の断線を演算・記憶装置
の演算結果を受信した判定装置が、設定値より外れるこ
とで判定すれば、ディジタル信号の不定状態を検出で
き、装置動作を停止する等により不定動作を防止でき
る。
According to the present invention, the failure of the A / D converter and the disconnection between the A / D converter and the determination device are determined by the determination device receiving the calculation result of the calculation / storage device deviating from the set value. Then, an undefined state of the digital signal can be detected, and the undefined operation can be prevented by stopping the operation of the apparatus.

【0011】また、本発明の請求項2に記載の発明は、
演算・記憶装置の出力と、設定装置内の設定値とを比較
し、演算記憶装置の出力が設定値以内の場合は演算・記
憶装置内の今回ディジタル値を次段に、また設定値より
大きい場合は、演算記憶装置内の前回ディジタル信号値
を、今回ディジタル信号値に置換えるとともに、前回デ
ィジタル信号値を次段に出力し、設定値より大きい判定
をn回くり返した場合に異常信号を次段に出力する判定
装置を有するものである。
[0011] The invention described in claim 2 of the present invention provides:
The output of the arithmetic and storage device is compared with the set value in the setting device. If the output of the arithmetic and storage device is within the set value, the current digital value in the arithmetic and storage device is set to the next stage and is larger than the set value. In this case, the previous digital signal value in the arithmetic and storage unit is replaced with the current digital signal value, and the previous digital signal value is output to the next stage. It has a determination device for outputting to a stage.

【0012】そして、演算・記憶装置の出力を受信した
判定装置が設定装置内の設定値より大きい判定をn回く
り返さない事には異常判定しない。このことにより、ア
ナログ検出信号への外来ノイズの重畳や、外来ノイズに
よる各装置の単発的な誤動作を無視することができ、外
乱に対しても影響を受けにくい装置が得られる。
An abnormality is not determined unless the determination device that has received the output of the arithmetic and storage device repeats the determination larger than the set value in the setting device n times. This makes it possible to ignore superposition of external noise on the analog detection signal and one-time malfunction of each device due to the external noise, and obtain a device that is hardly affected by disturbance.

【0013】さらに、本発明の請求項3に記載の発明
は、あらかじめ多段に設定してある設定装置内の設定値
より、演算・記憶装置の前回ディジタル信号値に基づき
値を選択し、判定に用いる判定装置を有するものであ
る。
Further, according to a third aspect of the present invention, a value is selected based on the previous digital signal value of the arithmetic / storage device from the set values in the setting device set in advance in multiple stages, and the determination is made. It has a determination device to be used.

【0014】そして、アナログ検出信号の変化が、その
信号値が取る領域で大きく異なる場合においても、判定
装置は、演算・記憶装置に記憶してある前回のディジタ
ル信号値に基づき、設定装置内に多段に設定してある設
定値を選択し、判定に用いる為、設定値を小さく決める
ことが可能となる。そのことにより、より、精度良くア
ナログ信号を検出している領域内でのディジタル信号の
不定を検出することができる。
[0014] Even when the change of the analog detection signal greatly differs in a region where the signal value takes, the judging device keeps the setting device based on the previous digital signal value stored in the arithmetic and storage device. Since the set values set in multiple stages are selected and used for the determination, the set values can be determined to be small. This makes it possible to detect digital signal indefiniteness in a region where an analog signal is detected with higher accuracy.

【0015】[0015]

【実施例】以下、本発明の実施例について図面を参照し
説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0016】(実施例1)図1は本発明のA/D変換装
置の構成を示したものである。図1においてA/D変換
部4は、タイマー装置5により得られる一定タイミング
で、A/D変換部4から出力する。その出力信号である
ディジタル信号値を、演算・記憶装置6は逐時記憶し、
また、前回記憶のディジタル信号値と今回のディジタル
信号値との差を求める。判定装置8は、演算・記憶装置
6からの演算結果が、あらかじめ設定装置7に記憶して
ある設定値に入るかどうかを判定する。
(Embodiment 1) FIG. 1 shows the configuration of an A / D converter according to the present invention. In FIG. 1, the A / D converter 4 outputs from the A / D converter 4 at a constant timing obtained by the timer device 5. The arithmetic and storage device 6 sequentially stores the digital signal value as the output signal,
Further, the difference between the digital signal value stored last time and the digital signal value this time is obtained. The determination device 8 determines whether the calculation result from the calculation / storage device 6 falls within a set value stored in the setting device 7 in advance.

【0017】この様に構成されたA/D変換装置の動作
について説明する。A/D変換部4は従来例のA/D変
換装置と等しい動作を行う。このA/D変換部4は、タ
イマー装置5により得られるアナログ検出信号の変化と
比較して充分に短い値(例えば、室温変化をアナログ検
出信号とした場合は約0.1秒〜約0.01秒)の一定
タイミングで、前述のアナログ検出信号値に相当するデ
ィジタル信号値に変換し次段に出力する。この信号を受
信する度に演算・記憶装置6は、逐時記憶する。
The operation of the A / D converter configured as described above will be described. The A / D converter 4 performs the same operation as the conventional A / D converter. The A / D converter 4 has a value that is sufficiently short compared to the change in the analog detection signal obtained by the timer device 5 (for example, when the change in room temperature is used as the analog detection signal, about 0.1 second to about 0.1 second). At a fixed timing of (01 seconds), the signal is converted into a digital signal value corresponding to the above-described analog detection signal value and output to the next stage. Each time this signal is received, the arithmetic / storage device 6 stores the signal sequentially.

【0018】また、前回(今回記憶した1回前)記憶の
ディジタル信号値と今回のディジタル信号値との差を演
算し求める。設定装置7には、あらかじめ、タイマー装
置5からの一定タイミング間では変化不可能なアナログ
検出信号値の差をディジタル値にした値(例えば、室温
変化をアナログ検出信号とした場合、タイマー装置5の
タイミングが0.1〜0.01秒であれば、必ず1K以
下の変化しかない。この1Kに余裕を加味し、求めた約
1〜3Kのアナログ検出信号値の差をディジタル値に変
換し設定値とする。
Further, a difference between the digital signal value stored last time (one time before this time stored) and the digital signal value this time is calculated and obtained. The setting device 7 has a digital value representing the difference between the analog detection signal values that cannot be changed during a certain period of time from the timer device 5 (for example, if the change in room temperature is an analog detection signal, the timer device 5 If the timing is 0.1 to 0.01 seconds, there is always only a change of 1 K or less, taking into account the 1 K with a margin, converting the obtained difference between the analog detection signal values of about 1 to 3 K into a digital value and setting it. Value.

【0019】ただし、上述の余裕により精度の良し悪し
が決まるので、検出するアナログ信号の要求精度を考慮
する必要が有る)。を設定値として記憶している。判定
装置8は演算・記憶装置6からの演算結果を、前記設定
値と比較し、演算結果が設定値に入っていれば、演算・
記憶装置6内部の今回のディジタル信号値を次段に出力
する。また、入っていない場合は異常の旨を次段に出力
する。ところで、判定装置6の初回の判定は、演算・記
憶装置6の前回のディジタル信号値がデーターとしてな
い為、正しい演算結果を得られない事から、1度だけ判
定しない様に配慮してある。
However, the degree of accuracy is determined by the above-mentioned margin, so it is necessary to consider the required accuracy of the analog signal to be detected.) Is stored as a set value. The judging device 8 compares the operation result from the operation / storage device 6 with the set value, and if the operation result is within the set value, the operation
The current digital signal value in the storage device 6 is output to the next stage. If it is not, an error message is output to the next stage. By the way, in the first judgment of the judging device 6, since the previous digital signal value of the arithmetic / storage device 6 is not used as data, a correct operation result cannot be obtained.

【0020】このことにより、従来のアナログ信号側回
路の故障検出に加え、A/D変換部4の故障や、A/D
変換部4と接続するアナログ検出信号間の断線や、A/
D変換部4と接続する演算・記憶装置6間の断線等によ
り生じるディジタル値の不定検出が可能となる。
As a result, in addition to the conventional failure detection of the analog signal side circuit, the failure of the A / D converter 4 and the A / D conversion
Disconnection between the analog detection signals connected to the conversion unit 4 and A /
Indefinite detection of a digital value caused by a disconnection or the like between the arithmetic / storage device 6 connected to the D conversion unit 4 becomes possible.

【0021】[0021]

【発明の効果】以上のように本発明によれば、従来検出
できなかったA/D変換部の故障やA/D変換部とアナ
ログ検出信号間の断線、A/D変換部と演算記憶装置間
の断線等により生じるディジタル値の不定検出ができ、
不定検出時はシステムの動作を停止する等の対策が可能
となる。したがって、より安全性の高いA/D変換装置
となるという有効な効果が得られる。
As described above, according to the present invention, the failure of the A / D converter, the disconnection between the A / D converter and the analog detection signal, the A / D converter and the arithmetic storage device, which could not be detected conventionally, can be obtained. Indefinite detection of digital value caused by disconnection between
At the time of indefinite detection, measures such as stopping the operation of the system can be taken. Therefore, an effective effect of achieving a more secure A / D converter can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例1におけるA/D変換装置の構
成を示すブロック図
FIG. 1 is a block diagram illustrating a configuration of an A / D converter according to a first embodiment of the present invention.

【図2】従来のA/D変換装置の構成を示すブロック図FIG. 2 is a block diagram showing a configuration of a conventional A / D converter.

【符号の説明】[Explanation of symbols]

4 A/D変換部 5 タイマー装置 6 演算・記憶装置 7 設定装置 8 判定装置 4 A / D conversion unit 5 Timer device 6 Arithmetic / storage device 7 Setting device 8 Judgment device

───────────────────────────────────────────────────── フロントページの続き (72)発明者 岡田 康弘 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yasuhiro Okada 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 A/D変換部と、このA/D変換部を設
定時間毎に動作させ、アナログ側の検出信号をディジタ
ル信号に変換するタイミングを与えるタイマー装置と、
前記A/D変換部と接続し、前記A/D変換部からのデ
ィジタル信号が出力される度に、その値を記憶するとと
もに、前回記憶しているディジタル信号値と今回のディ
ジタル信号値との差を求め次段に出力する演算・記憶装
置と、この演算・記憶装置と接続し、その出力と、あら
かじめ前記タイマー装置の設定時間内では変化不可能な
アナログ検出信号の差をディジタル値にした値を設定値
として記憶した値とを比較し、前記演算・記憶装置の出
力が設定値以内の場合は前記演算・記憶装置内の今回の
ディジタル信号値を次段に出力し、設定値より大きい場
合は異常信号を次段に出力する判定装置を備えたA/D
変換装置。
An A / D converter, a timer device for operating the A / D converter for each set time, and providing a timing for converting a detection signal on the analog side into a digital signal;
Each time a digital signal is output from the A / D converter, the value is stored, and the value of the previously stored digital signal is compared with the current digital signal value. A calculation / storage device for obtaining the difference and outputting it to the next stage, and connected to this calculation / storage device, the difference between the output and the analog detection signal which cannot be changed in advance within the set time of the timer device is converted into a digital value. The value is compared with a value stored as a set value, and when the output of the arithmetic / storage device is within the set value, the digital signal value of the current time in the arithmetic / storage device is output to the next stage, and is larger than the set value. A / D equipped with a determination device that outputs an abnormal signal to the next stage
Conversion device.
【請求項2】 A/D変換部と、このA/D変換部を設
定時間毎に動作させ、アナログ側の検出信号をディジタ
ル信号に変換するタイミングを与えるタイマー装置と、
前記A/D変換部と接続し、前記A/D変換部からのデ
ィジタル信号が出力される度に、その値を記憶するとと
もに、前回記憶しているディジタル信号値と今回のディ
ジタル信号値との差を求め次段に出力する演算・記憶装
置と、この演算・記憶装置と接続し、その出力と、あら
かじめ前記タイマー装置の設定時間内では変化不可能な
アナログ検出信号の差をディジタル値にした値を設定値
として記憶した値とを比較し、前記演算・記憶装置の出
力が設定値以内の場合は演算・記憶装置内の今回のディ
ジタル信号値を次段に、また設定値より大きい場合は、
演算・記憶装置内の前回のディジタル信号値を今回のデ
ィジタル信号値に置換えるとともに、前回のディジタル
信号値を次段に出力し、設定値より大きい判定をn回く
り返した場合に異常信号を次段に出力する判定装置を備
えたA/D変換装置。
2. An A / D converter, a timer device for operating the A / D converter for each set time, and providing a timing for converting a detection signal on the analog side into a digital signal.
Each time a digital signal is output from the A / D converter, the value is stored, and the value of the previously stored digital signal is compared with the current digital signal value. A calculation / storage device for obtaining the difference and outputting it to the next stage, and connected to this calculation / storage device, the difference between the output and the analog detection signal which cannot be changed in advance within the set time of the timer device is converted into a digital value. The value is compared with a value stored as a set value, and if the output of the arithmetic / storage device is within the set value, the digital signal value in the arithmetic / memory device is set to the next stage. ,
The previous digital signal value in the arithmetic and storage device is replaced with the current digital signal value, and the previous digital signal value is output to the next stage. An A / D converter having a determination device for outputting to a stage.
【請求項3】 A/D変換部と、このA/D変換部を設
定時間毎に動作させ、アナログ側の検出信号をディジタ
ル信号に変換するタイミングを与えるタイマー装置と、
前記A/D変換部と接続し、前記A/D変換部からのデ
ィジタル信号が出力される度に、その値を記憶するとと
もに、前回記憶しているディジタル信号値と今回のディ
ジタル信号値との差を求め次段に出力する演算・記憶装
置と、この演算・記憶装置と接続し、その出力と、あら
かじめ前記タイマー装置の設定時間内では変化不可能な
アナログ検出信号の差をディジタル値にした値を多段に
設定値として記憶した内の1つの値とを比較し、前記演
算・記憶装置の出力が設定値以内の場合は前記演算・記
憶装置内の今回のディジタル信号値を次段に出力し、設
定値より大きい場合は異常信号を次段に出力するととも
にあらかじめ多段に設定してある設定装置内の設定値
は、演算・記憶装置の前回ディジタル値に基づき値を選
択し、判定に用いる判定装置を備えたA/D変換装置。
3. An A / D converter, a timer device for operating the A / D converter for each set time and providing timing for converting an analog detection signal into a digital signal.
Each time a digital signal is output from the A / D converter, the value is stored, and the value of the previously stored digital signal is compared with the current digital signal value. A calculation / storage device for obtaining the difference and outputting it to the next stage, and connected to this calculation / storage device, the difference between the output and the analog detection signal which cannot be changed in advance within the set time of the timer device is converted into a digital value. The value is compared with one of the values stored as a set value in multiple stages, and if the output of the arithmetic and storage device is within the set value, the current digital signal value in the arithmetic and storage device is output to the next stage. If the set value is larger than the set value, an abnormal signal is output to the next stage, and the set value in the set device which has been set in multiple stages in advance is selected based on the previous digital value of the operation / storage device and used for determination. A / D converter having a constant device.
JP12318998A 1998-05-06 1998-05-06 A / D converter Expired - Fee Related JP3965773B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12318998A JP3965773B2 (en) 1998-05-06 1998-05-06 A / D converter

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Application Number Priority Date Filing Date Title
JP12318998A JP3965773B2 (en) 1998-05-06 1998-05-06 A / D converter

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Application Number Title Priority Date Filing Date
JP2007000368A Division JP3953093B2 (en) 2007-01-05 2007-01-05 A / D converter

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JPH11317665A true JPH11317665A (en) 1999-11-16
JP3965773B2 JP3965773B2 (en) 2007-08-29

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ID=14854404

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002084190A (en) * 2000-09-08 2002-03-22 Fuji Electric Co Ltd Method for calibrating a/d converter
JP2011135242A (en) * 2009-12-24 2011-07-07 Diamond Electric Mfg Co Ltd Load control circuit
JP2011139160A (en) * 2009-12-25 2011-07-14 Canon Inc Image processor, control method thereof, and computer program
JP4776143B2 (en) * 2000-08-29 2011-09-21 テレフオンアクチーボラゲット エル エム エリクソン(パブル) Calibration of A / D converter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4776143B2 (en) * 2000-08-29 2011-09-21 テレフオンアクチーボラゲット エル エム エリクソン(パブル) Calibration of A / D converter
JP2002084190A (en) * 2000-09-08 2002-03-22 Fuji Electric Co Ltd Method for calibrating a/d converter
JP2011135242A (en) * 2009-12-24 2011-07-07 Diamond Electric Mfg Co Ltd Load control circuit
JP2011139160A (en) * 2009-12-25 2011-07-14 Canon Inc Image processor, control method thereof, and computer program

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