JPH06188839A - Sampling rate converter - Google Patents

Abstract

PURPOSE:To provide a sampling rate converter in which the output of erroneous data can be prevented at the time of switching a sampling rate or a data format. CONSTITUTION:An input side clock signal (a), output side clock signal (b), input side data signal (c), and input side data format designation signal (d) are inputted to an arithmetic circuit 1. A prescribed arithmetic operation is performed based on those signals, and an output side data format designation signal preliminarily fixed to the inside of the arithmetic circuit 1, and an output side data signal (e) is outputted. When the input side clock signal (a) or the input side data format designation signal (d) fluctuate, the fluctuation is detected by a fluctuation detecting circuit 2 or 3. The output of the output side data signal (e) to an outside circuit is stopped by an output stopping circuit 4 receiving a detection signal (f) or (g).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling rate converter for digital audio or the like.

[0002]

2. Description of the Related Art Digital signals used for digital audio or the like have different sampling rates depending on the system. Therefore, it is necessary to convert the sampling rate in order to exchange data between different methods. A device that converts a sampling rate while maintaining the identity of a waveform signal such as an audio signal is called a sampling rate converter.

[0003]

Generally, in a sampling rate converter, the sampling rate and the data format on the output side are fixed and the sampling rate and the data format on the input side are often switched and used. In such a case, a new signal needs to be recalculated, so that it takes a certain amount of time to output a correct calculation result. In other words, incorrect data is output during the period until the correct calculation result is output. However, conventionally, sufficient measures have not been taken against such problems.

An object of the present invention is to provide a sampling rate converter capable of preventing erroneous data from being output when the sampling rate or the data format is switched.

[0005]

According to the present invention, there is provided a sampling rate converter for converting a first data signal having a first sampling rate into a second data signal having a second sampling rate, the first sampling rate corresponding to the first sampling rate. A clock signal, a second clock signal corresponding to the second sampling rate, the first data signal, the first
A first data format designating signal for designating the format of the data signal and a second data format designating signal for designating the format of the second data signal, and an arithmetic circuit for producing the second data signal; A clock signal, the second clock signal, the first data format designation signal, or the second
A variation detection circuit that detects a variation of the data format designation signal to generate a detection signal, and an output stop circuit that receives the detection signal and stops the output of the second data signal generated in the arithmetic circuit. is there.

[0006]

Embodiments of the present invention will be described below with reference to FIG.

The arithmetic circuit 1 has an input side clock signal "a" corresponding to an input side sampling rate (input side sampling frequency), an output side clock signal "b" corresponding to an output side sampling rate (output side sampling frequency), Input side data signal (input side waveform data)
“C”, an input side data format designation signal “d” that specifies the format of the input side data signal, and an output side data format designation signal that specifies the format (format) of the output side data signal (in the arithmetic circuit 1 The data is output on the output side (output side waveform data) "e" by performing a predetermined calculation based on the above (fixed in advance). The format of the input (output) side data signal means the word length or bit order (MSB first or LSB first) of the input (output) side data signal "c"("e").

The fluctuation detecting circuit 2 detects a fluctuation of the input side clock signal "a" (stop of clock signal, switching of frequency, etc.) and generates a detection signal "f".
The fluctuation detecting circuit 3 detects a fluctuation of the input side data format designation signal "d" (switching of data format, etc.) to generate a detection signal "g".

The output stop circuit 4 stops (mutes) the output of the output side data signal "e" to an external circuit (not shown) when a detection signal "f" or "g" occurs. Is. Specifically, the output signal "h" is set to 0 level or reduced for at least a period after the detection signal "f" or "g" is generated until the correct calculation result is output from the calculation circuit 1.

Next, the operation of the embodiment shown in FIG. 1 will be described.

An input side clock signal "a", an output side clock signal "b", an input side data signal "c" and an input side data format designation signal "d" are input to the arithmetic circuit 1. Then, a predetermined calculation is performed based on these signals and the output side data format designation signal fixed in advance inside the arithmetic circuit 1, and the output side data signal "e" is output. The arithmetic operation performed here is the same as the sampling rate conversion operation performed by a general sampling rate converter. Specifically, the sampling rate ratio between the input side sampling rate and the output side sampling rate is obtained based on the input side clock signal “a” and the output side clock signal “b”, and the digital sampling rate is based on the sampling rate ratio and the like. A predetermined calculation operation such as filtering calculation is performed.

On the other hand, the fluctuation detecting circuit 2 constantly monitors the fluctuation of the input side clock signal "a", and the fluctuation detecting circuit 3 constantly monitors the fluctuation of the input side data format designation signal "d". When the input side clock signal “a” or the input side data format designation signal “d” changes, the change detection circuit 2
Alternatively, the fluctuation detection circuit 3 detects the fluctuation, and the detection signal “f” or “g” is active for a certain period.

In the output stop circuit 4, the output side data signal "e" is normally output as it is as the output signal "h", but when the detection signal "f" or "g" becomes active, it is output only during the active period. The output of the side data signal "e" to the external circuit (not shown) is stopped (muted). That is, the output signal "h" is in a stopped state at least until the arithmetic circuit 1 outputs a correct arithmetic result. Therefore, the problem that incorrect data is output is solved.

In the embodiment described above, the fluctuation detection circuits 2 and 3 detect the fluctuation of the input side clock signal "a" or the fluctuation of the input side data format designation signal "d" to detect the detection signal "f" or Although "g" is generated, a detection signal may be generated similarly by detecting a change in the output clock signal "b". Further, although the output side data format designation signal is fixed in advance inside the arithmetic circuit 1, it may be given from the outside like the input side data format designation signal "d". Similarly, the fluctuation of the output side data format designation signal may be detected by the fluctuation detection circuit.

[0015]

According to the present invention, by providing the fluctuation detection circuit and the output stop circuit, it is possible to prevent erroneous data from being output when the sampling rate or the data format is switched.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

1 ... Arithmetic circuit 2 ... Variation detection circuit 3 ... Variation detection circuit 4 ... Output stop circuit a ... Input side clock signal (first clock signal) b ... Output side clock signal (second clock signal) c ...... Input side data signal (first data signal) d …… Input side data format designation signal (first data format designation signal) e …… Output side data signal (second data signal) f …… Detection signal g …… Detection signal

Claims (1)

[Claims] 1. A sampling rate converter for converting a first data signal of a first sampling rate into a second data signal of a second sampling rate, wherein a first clock signal corresponding to the first sampling rate and the second sampling rate. Corresponding to the second clock signal, the first data signal, the first data format designating signal designating the format of the first data signal, and the second data format designating signal designating the format of the second data signal. An arithmetic circuit for performing an operation to generate the second data signal, and a detection signal by detecting a variation in the first clock signal, the second clock signal, the first data format designation signal or the second data format designation signal. The fluctuation detection circuit that occurs and the output of the second data signal that occurs in the arithmetic circuit in response to the detection signal are stopped. And a sampling rate converter having an output stop circuit.