KR970004258B1 - System monitoring apparatus - Google Patents

Abstract

Disclosed is an apparatus to monitor performance of a system. The apparatus comprises the first and second input data converter, the first parity/CRC(Cylic Redundancy Check) calculator, a digital data processor, the second parity/CRC calculator, a parity/CRC detector and a comparator. The first and second input data converter convert input data into the data to be processed by the system. The first parity/CRC calculator calculates parity or CRC bit by the data from the second input data converter. The digital data processor processes the data from the first parity/CRC calculator and from the first input data converter. The second parity/CRC calculator calculates parity or CRC bit according to data from the digital data processor. The parity/CRC detector detects the parity or CRC bit from the digital data processor. The comparator campares parity or CRC bit from the parity/CRC detector with that from the second parity/CRC calculator, and generates an error signal. Thereby, the trouble state is perfectly detected according to the duplicating test.

Description

System performance monitoring device

1 is a block diagram of a performance monitoring apparatus of a conventional system.

2 is a block diagram of a performance monitoring apparatus of the present invention system.

* Description of the symbols for the main parts of the drawings *

1, 3: first and second input data conversion unit, 2: digital data processing unit,

4: the first parity / cyclic redundancy check calculation unit, 5: the second parity / cyclic redundancy check calculation unit,

6: parity / cyclic redundancy test detection unit, 7: comparison unit.

The present invention relates to a failure monitoring of a system (device), and more particularly, to a failure monitoring system failure by using a parity or a cyclic redundancy check code. It relates to a performance monitoring device of a system to detect a state.

As shown in FIG. 1, a performance monitoring apparatus of a system using a conventional parity or cyclic redundancy check code converts data input through a data input terminal (DIN) into parallel or serial data so that the system can process the data. A first parity / cyclic redundancy check calculation unit 102 for calculating a parity or a cyclic redundancy check bit for the data converted and output from the input data converter 100 and the input data converter 100 ) And a digital data processor 101 for processing the data calculated by the first parity / cyclic redundancy check calculator 102 and the data converted by the input data converter 100 and outputting the data to the data output terminal DOUT. And a second parity / cyclic redundancy check calculation unit 103 that calculates and outputs a parity or cyclic redundancy check bit for the data output from the digital data processing unit 102, and the digital data. The parity / cyclic redundancy check detector 104 which detects a parity or cyclic redundancy check bit from the data processed by the processing unit 101, and the parity or cyclic redundancy check bit detected by the parity / cyclic redundancy check detector 104 and The parity / cyclic redundancy check calculation unit 103 is configured to compare the parity or the cyclic redundancy check bit calculated by the comparison unit 105 to generate an error signal accordingly.

In the performance monitoring apparatus of the conventional system configured as described above, when data is first recorded through a data input terminal (din), the input data converter 100 converts the input data into parallel or serial data so that the system can process the digital data. Input to the processing unit 101 and the first parity / cyclic redundancy check calculation unit 102.

The first parity / cyclic redundancy check calculation unit 102 calculates a parity or cyclic redundancy check bit for the output data of the history data converter 100 which is output to monitor the digital data processing unit 101. The digital data processor 101 inputs the parity or the cyclicity calculated by the first parity / cyclic redundancy check calculator 102 to the data input from the input data converter 100. The duplicate check bit is inserted to process digital data, and the processed data is output through the data output terminal (DOUT).

In this case, the second parity / cyclic redundancy check calculation unit 103 calculates a parity or cyclic redundancy check bit based on the data output from the digital data processing unit 101 and inputs the parity / cyclic redundancy check bit to the comparison unit 105. The check detector 104 detects a parity or cyclic redundancy check bit from the data output from the digital data processor 101 and inputs it to the comparator 105.

Accordingly, the comparison unit 105 may determine the parity or cyclic redundancy check bit calculated by the second parity / cyclic redundancy check calculation unit 103 and the parity or cyclic redundancy check bit detected by the parity / cyclic redundancy check detection unit 104. The digital data processing unit 101 monitors whether the digital data has been processed without an error.

That is, if the parity or cyclic redundancy check bit calculated by the second parity / cyclic redundancy check calculation unit 103 and the parity or cyclic redundancy check bit detected by the parity / cyclic redundancy check detection unit 104 are different, the digital data processor 101 It is determined that the data processing from the error state is an error signal, and if it is the same, it is determined that the data processing is normal.

However, the performance audit apparatus of the system using the conventional parity or cyclic redundancy check bit calculates a parity or cyclic redundancy check bit based on the data output from the input data conversion unit, and the parity or cyclic redundancy in the data processed by the digital data processing unit. By detecting and comparing the check bits, an error condition generated by the digital data processing unit can be monitored, but an error state caused by a failure of the input data conversion unit can not be monitored, which causes performance degradation.

Accordingly, an object of the present invention is to provide a performance monitoring apparatus of a system to improve failure monitoring efficiency by monitoring a failure over the entire part of a system by using a parity or cyclic redundancy check bit in a device for monitoring a failure of the system. .

The object of the present invention is to calculate parity or cyclic redundancy check bits for the first and second input data converting means for converting data into parallel or serial data, and the data converted from the second input data converting means. Digital data processing means for processing the first parity / cyclic redundancy check calculation means, the data calculated by the first parity / cyclic redundancy check calculation means and the data converted by the first input data conversion means, and the digital data processing. Second parity / cyclic redundancy check calculation means for calculating and outputting parity or cyclic redundancy check bits for the data of the means, and parity / cyclic redundancy check detection means by detecting parity or cyclic redundancy check bits in the data of the digital data processing means. And the detected parity or cyclic redundancy check bit and the calculated parity or cyclic redundancy check bit Compared to that which is achieved, by providing a comparing means for generating an error signal corresponding thereto, it will now be described in detail below based on the accompanying drawings, the present invention.

FIG. 2 is a block diagram of a performance monitoring apparatus of the present invention. As shown in FIG. 1, a system converts data input through a data input terminal (DIN) into parallel or serial data so that a system can process the same. The first and second data calculated by the parity or cyclic redundancy check calculation section 4 for the data converted and output from the second input data converter 1 and 3 and the second input data converter 3, respectively. Parity or cyclic redundancy check bit for the digital data processing unit 2 for processing the data converted by the input data conversion unit 1 and outputting the data to the data output terminal DOUT, and the data output from the digital data processing unit 2 at all times. Parity / cyclic redundancy check calculation unit 5 for calculating and outputting a parity / circular redundancy check unit 5 and parity / cyclic redundancy check for detecting a parity or cyclic redundancy check bit from data processed by the digital data processing unit 2. Has a structure including chulbu 6 and the comparison unit 7 that compares the parity or cyclic redundancy check bits detected by the parity / Cyclic Redundancy Check detector 6 generates an error signal accordingly.

Referring to the operation, effects of the present invention configured as described above in detail.

First, when data is input through the data input terminal (DIN), the first and second input data converters 1 and 3 convert the input data into parallel or serial data so that the system can process the digital data processor. 2) and the first parity / cyclic redundancy check calculation unit 4.

The first parity / cyclic redundancy check calculation unit 4 calculates a parity or cyclic redundancy check bit based on the output data of the second input data conversion unit 3 outputted to monitor the digital data processing unit 2. The digital data processing unit 2 is inputted to the digital data processing unit 2, and the digital data processing unit 2 is calculated by the first parity / cyclic redundancy check calculation unit 4 to the data input from the first input data conversion unit 1, Digital data is processed by inserting an input parity or cyclic redundancy check bit, and the processed data is output through the data output terminal DOUT.

In this case, the second parity / cyclic redundancy check calculation unit 5 calculates a parity or cyclic redundancy check bit based on the data output from the digital data processing unit 2 and inputs the parity / cyclic redundancy check bit to the comparison unit 7. The check detector 6 outputs a parity or cyclic redundancy check bit from the data output from the digital data processor 2 and inputs it to the comparator 7.

Accordingly, the comparison unit 7 performs the parity or cyclic redundancy check bit calculated by the second parity / cyclic redundancy check calculation unit 5 and the parity or cyclic redundancy check bit detected by the parity / cyclic redundancy check detection unit 6. Compare and compare the data with the digital data processor 2 if the detected parity or cyclic redundancy check bit differs from the calculated parity or cyclic redundancy check bit. It is determined that the processing is in an error state and an error signal is output. If the processing is the same, it is determined that the data processing is in a normal state.

As described above, in the present invention, when a failure occurs in the first input data converter, the digital data processor calculates a parity or cyclic redundancy check bit based on the output data of the second input data converter that is identical to the first input data converter. Since the comparator can monitor an error of the system and the first input data converter is in a normal state and a failure occurs in the second input data converter, the comparator can detect an error condition. There is an effect that can completely detect the failure state of the whole part.

Claims (1)

First and second input data conversion means for converting input data into data that can be processed by the system, and first parity / circulation for calculating parity or cyclic redundancy check bits for data obtained by the second input data conversion means. Digital data processing means for processing the redundancy check calculation means, the data calculated by the first parity / cyclic redundancy check calculation means and the data converted by the first input data conversion means, and the output data of the digital data processing means. Second parity / cyclic redundancy check calculation means for calculating parity or cyclic redundancy check bits, parity / cyclic redundancy check detection means for detecting parity or cyclic redundancy check bits in the output data of the digital data processing means, and the parity Parity or cyclic redundancy check bit detected by the cyclic redundancy check detection means and the parity / Comparing means for comparing the parity or the cyclic redundancy check bit calculated in the cyclic redundancy check calculation means and generates an error signal according to the performance monitoring apparatus of the system.