JP3953093B2 - A / D converter - Google Patents

A / D converter Download PDF

Info

Publication number
JP3953093B2
JP3953093B2 JP2007000368A JP2007000368A JP3953093B2 JP 3953093 B2 JP3953093 B2 JP 3953093B2 JP 2007000368 A JP2007000368 A JP 2007000368A JP 2007000368 A JP2007000368 A JP 2007000368A JP 3953093 B2 JP3953093 B2 JP 3953093B2
Authority
JP
Japan
Prior art keywords
value
output
digital signal
digital
conversion unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007000368A
Other languages
Japanese (ja)
Other versions
JP2007110755A (en
Inventor
剛司 本田
逸夫 五十嵐
孝治 村瀬
康弘 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2007000368A priority Critical patent/JP3953093B2/en
Publication of JP2007110755A publication Critical patent/JP2007110755A/en
Application granted granted Critical
Publication of JP3953093B2 publication Critical patent/JP3953093B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Description

本発明はアナログ信号をディジタル信号に変換するA/D変換装置に関する。   The present invention relates to an A / D converter for converting an analog signal into a digital signal.

従来、A/D変換装置は、アナログ信号側回路のHi故障あるいはLO故障を防止する為に、アナログ信号側回路が通常動作をしている時は、(電源電圧−α)と(グランド+β)間の電圧で動作する様に設計し、A/D変換結果がαからβ間に有る事を確認する安全対策を行っていた。   Conventionally, in order to prevent Hi failure or LO failure of the analog signal side circuit, the A / D conversion device has (power supply voltage −α) and (ground + β) when the analog signal side circuit is operating normally. It was designed to operate at a voltage between, and safety measures were taken to confirm that the A / D conversion result was between α and β.

図2に従来のA/D変換装置の構成を示しており、1はA/D変換部であり、アナログ値を入力し、ディジタル値として次段に出力する。2はディジタル基準電圧装置である。(電源電圧)から(電源電圧−α)の一定領域、および、(グランド電圧)から(グランド電圧+β)の一定領域を異常領域として、また、βからαの間を動作領域として、あらかじめ前述した各値をディジタル値に変換した値を記憶している。3は判定装置でありA/D変換部1の出力をディジタル基準電圧装置2の基準値と比較する。   FIG. 2 shows a configuration of a conventional A / D conversion apparatus. Reference numeral 1 denotes an A / D conversion unit which inputs an analog value and outputs it as a digital value to the next stage. Reference numeral 2 denotes a digital reference voltage device. The constant region from (power supply voltage) to (power supply voltage−α) and the constant region from (ground voltage) to (ground voltage + β) are defined as abnormal regions, and the operation region is defined between β and α. A value obtained by converting each value into a digital value is stored. A determination device 3 compares the output of the A / D converter 1 with the reference value of the digital reference voltage device 2.

そして、A/D変換部1の出力値が動作領域であれば、前述のA/D変換部1の出力を、異常領域であれば異常の旨を次段に出力する様構成されている。上記の様に、このA/D変換装置では、アナログ信号側の回路が正常動作する領域と、回路故障時の異常領域があらかじめ求められている。そして、その領域をディジタル値としてディジタル基準電圧装置2に記憶させる。その値を基に、判定装置3で比較する事により、アナログ信号側の異常を検出していた。   If the output value of the A / D conversion unit 1 is an operation region, the output of the A / D conversion unit 1 described above is output to the next stage if it is an abnormal region. As described above, in this A / D converter, an area where the circuit on the analog signal side normally operates and an abnormal area when a circuit failure occurs are obtained in advance. The area is stored in the digital reference voltage device 2 as a digital value. Based on the value, an abnormality on the analog signal side was detected by comparing with the determination device 3.

しかしながら、上記構成ではA/D変換部1の故障や、A/D変換部1と接続する判定装置3の間の断線等により、ディジタル値が不定となる。その値が、ディジタル基準電圧装置2に記憶した動作領域に入れば、アナログ信号を検出したい広い領域でアナログ信号の異常検出ができないという課題を有していた。   However, in the above configuration, the digital value becomes indefinite due to a failure of the A / D conversion unit 1 or a disconnection between the determination devices 3 connected to the A / D conversion unit 1. If the value enters the operation region stored in the digital reference voltage device 2, there is a problem that the abnormality of the analog signal cannot be detected in a wide region where the analog signal is desired to be detected.

この課題を解決するために本発明は、従来のA/D変換装置に加え、タイマー装置により得られる一定タイミングで、A/D変換装置から出力されるディジタル信号値を逐時記憶し、また、あらかじめ多段に設定してある設定装置内の設定値より、演算・記憶装置の前回ディジタル信号値に基づき値を選択し、判定に用いる判定装置を有するものである。   In order to solve this problem, in addition to the conventional A / D converter, the present invention stores the digital signal value output from the A / D converter at a constant timing obtained by the timer device, It has a determination device for selecting a value based on the previous digital signal value of the arithmetic / storage device from the set values in the setting device set in advance in multiple stages, and for use in the determination.

上記発明によれば、アナログ検出信号の変化が、その信号値が取る領域で大きく異なる場合においても、判定装置は、演算・記憶装置に記憶してある前回のディジタル信号値に基づき、設定装置内に多段に設定してある設定値を選択し、判定に用いる為、設定値を小さく決めることが可能となる。そのことにより、より、精度良くアナログ信号を検出している領域内でのディジタル信号の不定を検出することができる。   According to the above invention, even when the change in the analog detection signal is greatly different in the area taken by the signal value, the determination device is based on the previous digital signal value stored in the calculation / storage device. Since the setting value set in multiple stages is selected and used for determination, the setting value can be determined small. As a result, it is possible to detect the indefiniteness of the digital signal in the region where the analog signal is detected with higher accuracy.

以上のように本発明によれば、従来検出できなかったA/D変換部の故障やA/D変換部とアナログ検出信号間の断線、A/D変換部と演算記憶装置間の断線等により生じるディジタル値の不定検出ができ、不定検出時はシステムの動作を停止する等の対策が可能となる。したがって、より安全性の高いA/D変換装置となるという有効な効果が得られる
As described above, according to the present invention, due to a failure of the A / D conversion unit that could not be detected in the past, disconnection between the A / D conversion unit and the analog detection signal, disconnection between the A / D conversion unit and the arithmetic storage device, etc. It is possible to detect indefinitely the generated digital value, and measures such as stopping the system operation when indefinite detection is possible. Therefore, it is possible to obtain an effective effect that an A / D conversion device with higher safety can be obtained.

本発明の第1の実施の形態は、A/D変換部と、このA/D変換部を設定時間毎に動作させ、アナログ側の検出信号をディジタル信号に変換するタイミングを与えるタイマー装置と、前記A/D変換部と接続し、A/D変換部からのディジタル信号が出力される度に、その値を記憶するとともに、前回記憶しているディジタル信号値と今回のディジタル信号値との差を求め次段に出力する演算・記憶装置と、この演算・記憶装置と接続し、その出力と、あらかじめタイマー装置の設定時間内では変化不可能なアナログ検出信号の差をディジタル値にした値を設定値として記憶した値とを比較し、演算・記憶装置の出力が設定値以内の場合は演算・記憶装置内の今回のディジタル信号値を次段に、また、設定値より大きい場合は異常信号を次段に出力する判定装置を有するものである。   The first embodiment of the present invention includes an A / D conversion unit, a timer device that operates the A / D conversion unit for each set time, and provides timing for converting an analog detection signal into a digital signal, Each time a digital signal is output from the A / D converter connected to the A / D converter, the value is stored and the difference between the previously stored digital signal value and the current digital signal value is stored. Is calculated and output to the next stage and connected to this calculation / storage device, and the difference between the output and the analog detection signal that cannot be changed within the set time of the timer device in advance is converted to a digital value. Compare the value stored as the set value. If the output of the calculation / storage device is within the set value, the current digital signal value in the calculation / storage device is set to the next stage. To the next stage And it has a determination device for outputting.

そして、タイマー装置により得られる一定タイミングで、A/D変換部から出力されるディジタル信号値を逐時記憶し、また前回の記憶のディジタル信号値との差を求める演算・記憶装置の演算結果があらかじめ設定装置に記憶してある設定値に入るかどうかを判定装置で合否判定する。このことにより、アナログ検出信号の変化が予想される値以内であるかを判定するので、A/D変換部の故障や、A/D変換部と判定装置間の断線により生じるディジタル値の不定を、アナログ信号を検出している領域内で、精度良く検出することができる。さらに設定装置内の設定値を小さく設定する事により、前記精度は向上する。   Then, the digital signal value output from the A / D converter is constantly stored at a fixed timing obtained by the timer device, and the calculation result of the calculation / storage device for obtaining the difference from the digital signal value of the previous storage is obtained. The determination device determines whether or not the set value stored in the setting device is entered in advance. As a result, it is determined whether the change in the analog detection signal is within an expected value. Therefore, it is possible to detect indefinite digital values caused by a failure of the A / D converter or a disconnection between the A / D converter and the determination device. In the region where the analog signal is detected, it can be detected with high accuracy. Further, the accuracy is improved by setting the setting value in the setting device small.

この発明によると、A/D変換部の故障や、A/D変換部と判定装置間の断線を演算・記憶装置の演算結果を受信した判定装置が、設定値より外れることで判定すれば、ディジタル信号の不定状態を検出でき、装置動作を停止する等により不定動作を防止できる。   According to this invention, if the determination device that has received the calculation result of the calculation / storage device determines that the A / D conversion unit has failed or the disconnection between the A / D conversion unit and the determination device is out of the set value, An indefinite state of the digital signal can be detected, and the indefinite operation can be prevented by stopping the operation of the apparatus.

また、本発明の第2の実施の形態は、演算・記憶装置の出力と、設定装置内の設定値とを比較し、演算記憶装置の出力が設定値以内の場合は演算・記憶装置内の今回ディジタル値を次段に、また設定値より大きい場合は、演算記憶装置内の前回ディジタル信号値を、今回ディジタル信号値に置換えるとともに、前回ディジタル信号値を次段に出力し、設定値より大きい判定をn回くり返した場合に異常信号を次段に出力する判定装置を有するものである。   The second embodiment of the present invention compares the output of the arithmetic / storage device with the set value in the setting device, and if the output of the arithmetic / storage device is within the set value, If the current digital value is the next stage or larger than the set value, the previous digital signal value in the arithmetic storage unit is replaced with the current digital signal value, and the previous digital signal value is output to the next stage. It has a determination device that outputs an abnormal signal to the next stage when a large determination is repeated n times.

そして、演算・記憶装置の出力を受信した判定装置が設定装置内の設定値より大きい判定をn回くり返さない事には異常判定しない。このことにより、アナログ検出信号への外来ノイズの重畳や、外来ノイズによる各装置の単発的な誤動作を無視することができ、外乱に対しても影響を受けにくい装置が得られる。   If the determination device that has received the output of the arithmetic / storage device does not repeat the determination larger than the set value in the setting device n times, no abnormality determination is made. This makes it possible to ignore the superimposition of external noise on the analog detection signal and the single malfunction of each device due to the external noise, and to obtain a device that is less susceptible to disturbances.

また、本発明の第3の実施の形態は、A/D変換部と、このA/D変換部を設定時間毎に動作させ、アナログ側の検出信号をディジタル信号に変換するタイミングを与えるタイマー装置と、前記A/D変換部と接続し、前記A/D変換部からのディジタル信号が出力される度に、その値を記憶するとともに、前回記憶しているディジタル信号値と今回のディジタル信号値との差を求め次段に出力する演算・記憶装置と、この演算・記憶装置と接続し、その出力と、あらかじめ前記タイマー装置の設定時間内では変化不可能なアナログ検出信号の差をディジタル値にした値を多段に設定値として記憶した内の1つの値とを比較し、前記演算・記憶装置の出力が設定値以内の場合は前記演算・記憶装置内の今回のディジタル信号値を次段に出力し、設定値より大きい場合は異常信号を次段に出力するとともにあらかじめ多段に設定してある設定装置内の設定値は、演算・記憶装置の前回ディジタル値に基づき値を選択し、判定に用いる判定装置を備えたものである。   Further, the third embodiment of the present invention is an A / D converter and a timer device that operates the A / D converter every set time and provides timing for converting an analog detection signal into a digital signal. Each time a digital signal is output from the A / D converter, the value is stored, and the previously stored digital signal value and the current digital signal value are stored. Is connected to this arithmetic / storage device, and the difference between the output and the analog detection signal that cannot be changed within the set time of the timer device in advance is a digital value. Is compared with one value stored as a set value in multiple stages, and if the output of the calculation / storage device is within the set value, the current digital signal value in the calculation / storage device is Output to When larger than the set value, an abnormal signal is output to the next stage, and the set value in the set device that has been set in multiple stages in advance is selected based on the previous digital value of the arithmetic / storage device, and used for determination It is equipped with.

そして、アナログ検出信号の変化が、その信号値が取る領域で大きく異なる場合においても、判定装置は、演算・記憶装置に記憶してある前回のディジタル信号値に基づき、設定装置内に多段に設定してある設定値を選択し、判定に用いる為、設定値を小さく決めることが可能となる。そのことにより、より、精度良くアナログ信号を検出している領域内でのディジタル信号の不定を検出することができる。   Even when the change in the analog detection signal varies greatly in the area taken by the signal value, the determination device is set in multiple stages in the setting device based on the previous digital signal value stored in the calculation / storage device. Since the set value is selected and used for determination, the set value can be determined to be small. As a result, it is possible to detect the indefiniteness of the digital signal in the region where the analog signal is detected with higher accuracy.

以下、本発明の実施例について図面を参照し説明する。   Embodiments of the present invention will be described below with reference to the drawings.

(実施例1)
図1は本発明のA/D変換装置の構成を示したものである。図1においてA/D変換部4は、タイマー装置5により得られる一定タイミングで、A/D変換部4から出力する。その出力信号であるディジタル信号値を、演算・記憶装置6は逐時記憶し、また、前回記憶のディジタル信号値と今回のディジタル信号値との差を求める。判定装置8は、演算・記憶装置6からの演算結果が、あらかじめ設定装置7に記憶してある設定値に入るかどうかを判定する。
Example 1
FIG. 1 shows the configuration of the A / D conversion apparatus of the present invention. In FIG. 1, the A / D conversion unit 4 outputs from the A / D conversion unit 4 at a constant timing obtained by the timer device 5. The arithmetic / storage device 6 stores the digital signal value, which is the output signal, every time, and obtains the difference between the previously stored digital signal value and the current digital signal value. The determination device 8 determines whether or not the calculation result from the calculation / storage device 6 falls within the set value stored in the setting device 7 in advance.

この様に構成されたA/D変換装置の動作について説明する。A/D変換部4は従来例のA/D変換装置と等しい動作を行う。このA/D変換部4は、タイマー装置5により得られるアナログ検出信号の変化と比較して充分に短い値(例えば、室温変化をアナログ検出信号とした場合は約0.1秒〜約0.01秒)の一定タイミングで、前述のアナログ検出信号値に相当するディジタル信号値に変換し次段に出力する。この信号を受信する度に演算・記憶装置6は、逐時記憶する。   The operation of the A / D converter configured in this way will be described. The A / D converter 4 performs the same operation as that of the conventional A / D converter. The A / D converter 4 has a sufficiently short value as compared with the change in the analog detection signal obtained by the timer device 5 (for example, about 0.1 second to about 0. At a constant timing of (01 seconds), it is converted into a digital signal value corresponding to the analog detection signal value described above and output to the next stage. Every time this signal is received, the arithmetic / storage device 6 stores it every time.

また、前回(今回記憶した1回前)記憶のディジタル信号値と今回のディジタル信号値との差を演算し求める。設定装置7には、あらかじめ、タイマー装置5からの一定タイミング間では変化不可能なアナログ検出信号値の差をディジタル値にした値(例えば、室温変化をアナログ検出信号とした場合、タイマー装置5のタイミングが0.1〜0.01秒であれば、必ず1K以下の変化しかない。この1Kに余裕を加味し、求めた約1〜3Kのアナログ検出信号値の差をディジタル値に変換し設定値とする。   Further, the difference between the digital signal value stored last time (one time before this time) and the current digital signal value is calculated and obtained. In the setting device 7, a value obtained by converting a difference between analog detection signal values that cannot be changed between certain timings from the timer device 5 into a digital value (for example, when a change in room temperature is used as an analog detection signal, the timer device 5 If the timing is 0.1 to 0.01 seconds, there will always be a change of 1K or less, with a margin added to this 1K, and the difference between the obtained analog detection signal values of about 1 to 3K is converted into a digital value and set. Value.

ただし、上述の余裕により精度の良し悪しが決まるので、検出するアナログ信号の要求精度を考慮する必要が有る)。を設定値として記憶している。判定装置8は演算・記憶装置6からの演算結果を、前記設定値と比較し、演算結果が設定値に入っていれば、演算・記憶装置6内部の今回のディジタル信号値を次段に出力する。また、入っていない場合は異常の旨を次段に出力する。ところで、判定装置6の初回の判定は、演算・記憶装置6の前回のディジタル信号値がデーターとしてない為、正しい演算結果を得られない事から、1度だけ判定しない様に配慮してある。   However, since accuracy is determined by the above-mentioned margin, it is necessary to consider the required accuracy of the analog signal to be detected). Is stored as a set value. The determination device 8 compares the calculation result from the calculation / storage device 6 with the set value, and if the calculation result is within the set value, outputs the current digital signal value in the calculation / storage device 6 to the next stage. To do. If it is not present, an error message is output to the next stage. By the way, since the previous digital signal value of the calculation / storage device 6 is not used as data for the initial determination of the determination device 6, consideration is given so that the determination is not performed once because a correct calculation result cannot be obtained.

このことにより、従来のアナログ信号側回路の故障検出に加え、A/D変換部4の故障や、A/D変換部4と接続するアナログ検出信号間の断線や、A/D変換部4と接続する演算・記憶装置6間の断線等により生じるディジタル値の不定検出が可能となる。   As a result, in addition to the conventional failure detection of the analog signal side circuit, the failure of the A / D conversion unit 4, the disconnection between the analog detection signals connected to the A / D conversion unit 4, the A / D conversion unit 4 and the An indefinite detection of a digital value caused by disconnection or the like between connected arithmetic / storage devices 6 can be performed.

本発明の実施例1におけるA/D変換装置の構成を示すブロック図1 is a block diagram illustrating a configuration of an A / D conversion device according to a first embodiment of the present invention. 従来のA/D変換装置の構成を示すブロック図Block diagram showing the configuration of a conventional A / D converter

符号の説明Explanation of symbols

4 A/D変換部
5 タイマー装置
6 演算・記憶装置
7 設定装置
8 判定装置
4 A / D converter 5 Timer device 6 Arithmetic / storage device 7 Setting device 8 Judgment device

Claims (1)

A/D変換部と、このA/D変換部を設定時間毎に動作させ、アナログ側の検出信号をディジタル信号に変換するタイミングを与えるタイマー装置と、前記A/D変換部と接続し、前記A/D変換部からのディジタル信号が出力される度に、その値を記憶するとともに、前回記憶しているディジタル信号値と今回のディジタル信号値との差を求め次段に出力する演算・記憶装置と、この演算・記憶装置と接続し、その出力と、あらかじめ前記タイマー装置の設定時間内では変化不可能なアナログ検出信号の差をディジタル値にした値を多段に設定値として記憶した内の1つの値とを比較し、前記演算・記憶装置の出力が設定値以内の場合は前記演算・記憶装置内の今回のディジタル信号値を次段に出力し、設定値より大きい場合は異常信号を次段に出力するとともにあらかじめ多段に設定してある設定装置内の設定値は、演算・記憶装置の前回ディジタル値に基づき値を選択し、判定に用いる判定装置を備えたA/D変換装置。 An A / D conversion unit, a timer device that operates the A / D conversion unit for each set time, and provides a timing for converting an analog detection signal into a digital signal, and is connected to the A / D conversion unit, Every time a digital signal is output from the A / D converter, the value is stored, and the difference between the previously stored digital signal value and the current digital signal value is obtained and output to the next stage. A value obtained by connecting a difference between an output and an analog detection signal that cannot be changed within a set time of the timer device in advance as a digital value is stored as a set value in multiple stages. Compared with one value, if the output of the calculation / storage device is within the set value, the current digital signal value in the calculation / storage device is output to the next stage, and if it is greater than the set value, an abnormal signal is output. Setting values in advance in the set to multiple stages Aru setting device to output the stage operation-select on the basis of value to the previous digital value of the memory device, A / D conversion apparatus having a determination device used for the determination.
JP2007000368A 2007-01-05 2007-01-05 A / D converter Expired - Fee Related JP3953093B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007000368A JP3953093B2 (en) 2007-01-05 2007-01-05 A / D converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007000368A JP3953093B2 (en) 2007-01-05 2007-01-05 A / D converter

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP12318998A Division JP3965773B2 (en) 1998-05-06 1998-05-06 A / D converter

Publications (2)

Publication Number Publication Date
JP2007110755A JP2007110755A (en) 2007-04-26
JP3953093B2 true JP3953093B2 (en) 2007-08-01

Family

ID=38036173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007000368A Expired - Fee Related JP3953093B2 (en) 2007-01-05 2007-01-05 A / D converter

Country Status (1)

Country Link
JP (1) JP3953093B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102340172B (en) * 2010-06-05 2013-10-16 陈家斌 Intelligent control system for distribution network
CN102271445B (en) * 2010-06-07 2014-03-12 陈家斌 Intelligent power-supply control system of street lamps
CN102340176B (en) * 2010-07-14 2013-09-18 陈家斌 Remote intelligent control device for 10-20kV building power supply
DE102012203670A1 (en) * 2012-03-08 2013-09-12 Robert Bosch Gmbh Analog-to-digital converter arrangement and associated method for checking a multiplexer for an analog-to-digital converter
JP5368601B2 (en) * 2012-04-23 2013-12-18 三菱電機株式会社 A / D converter

Also Published As

Publication number Publication date
JP2007110755A (en) 2007-04-26

Similar Documents

Publication Publication Date Title
JP3953093B2 (en) A / D converter
JP2005086883A (en) Overvoltage protection circuit, power supply using same, power supply system, and electronic device
JP2019101515A (en) Semiconductor device and power supply monitoring method therefor
JP2014064354A (en) Digitally-controlled power supply having failure detection function
JP7210763B2 (en) METHOD AND DEVICE FOR MONITORING GATE SIGNAL OF POWER SEMICONDUCTOR
JP2009111546A (en) Semiconductor integrated circuit having self-diagnostic function, imaging device, and camera system
JP6029520B2 (en) Power supply monitoring apparatus and power supply monitoring method
JP3965773B2 (en) A / D converter
JP2006304456A (en) Power converter
KR101446929B1 (en) System for controlling power-up sequence
US20130082739A1 (en) Clock diagnosis circuit
KR20140079312A (en) Mothod and device for monitoring signal levels
JP7006565B2 (en) Electrical equipment, communication equipment, and communication systems
JP5825480B2 (en) Field wiring diagnosis device
JP2006112889A (en) Power supply voltage detection circuit
KR101795464B1 (en) System Having Watchdog Processor, and Method Thereof
JP2005345380A (en) Electronic circuit with failure detecting function
JP2012080670A (en) Switching regulator
JP2016201761A (en) Failure detection circuit
JP6325217B2 (en) CIRCUIT DEVICE AND CIRCUIT DEVICE RECOVERY METHOD
JP4835207B2 (en) Temperature transmitter
US20230036211A1 (en) Control circuit and method for calibrating signal converter, and signal conversion system using the same
JP2010033119A (en) Analog output device with self-diagnostic function
JP5016538B2 (en) A / D conversion apparatus and method
JP2006211737A (en) Overcurrent limiting circuit

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070205

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070410

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070423

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110511

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees