JPH11312720A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a test element group(TEG) pattern in which a defective part can be easily detected, and a time required for measurement can be reduced by a relatively simple method. SOLUTION: This semiconductor device is provided with switching elements 1-1 to 1-n for selecting whether plural test element groups should be operated as a whole or plural test element groups should be operated individually, and when a detect is not detected at the overall test for the plural test element groups, the individual test is not operated, and when defects are detected at the overall test, the individual test is conducted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a pattern for evaluating a manufacturing process and a method of manufacturing the same.

[0002]

2. Description of the Related Art A test element group called a TEG (Test Element Group) is mounted on a chip to evaluate circuit characteristics and process characteristics before starting a new manufacturing process or changing a process. It is often done. FIG. 5 shows an example of a pattern of a conventional TEG for detecting a short circuit of a wiring. In FIG. 5, reference numeral 11 denotes a measurement pad, and reference numeral 12 denotes a test wiring pattern.
As shown in this figure, the TEG for short-circuit detection is
Are formed by alternately disposing a plurality of wirings 12 on an area of several mm square. However, such a method has a large area as compared with the width of the pattern wiring 12, so that
There is a problem that it is very difficult to detect a short-circuited portion even if the fact of the short-circuit is known.

To alleviate this problem as much as possible, a layout as shown in FIG. 6 is used. In this method, a common pad Commo is used as a measurement pad.
It is conceived to provide pads A1 to An for each of n and an area and to divide a large area TEG into several area blocks to make it possible to easily detect a defective portion. However, in this configuration, in order to check for a short-circuit failure location with respect to the entire scale of the TEG, all of the blocks that have been divided must be measured, and the measurement time increases as the number of divisions increases. was there.

[0004]

As described above, in the conventional test method using TEG, a certain pattern area is required for performing reliable measurement, and the method in which patterns are integrated into one However, there is a problem that it is difficult to detect a defective portion, and the method of dividing the pattern requires a longer measuring time for the division.

The present invention solves this problem, and realizes a semiconductor device having a TEG pattern in which a defective portion can be easily detected and the time required for measurement can be reduced by a relatively simple method, and a method of manufacturing the same. Make it an issue.

[0006]

According to the present invention, a test pattern including a plurality of test element groups for evaluating characteristics is provided on a semiconductor chip. In a semiconductor device capable of evaluating the achievement and reliability characteristics of the manufacturing process of the semiconductor chip by testing the test element groups, the plurality of test element groups may be operated as a whole or the plurality of test element groups may be individually operated. It is characterized by comprising a switch means capable of selecting whether the operation is performed.

A test pattern including a plurality of test element groups for evaluating characteristics is provided on a semiconductor chip.
In the method of manufacturing a semiconductor device having an inspection process in which a plurality of test element groups of the test pattern can be tested to evaluate the achievement and reliability characteristics of the manufacturing process of the semiconductor chip, the inspection process includes And an individual test step of individually testing the plurality of test element groups when a failure is detected in the entire test step.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows a pattern of a TEG for detecting a short circuit according to an embodiment of the present invention. This example is a conventional example of the split type shown in FIG. 6, in which switching elements 1-1 to 1-n such as FETs are provided on pads A1 to An for each area. Then, one side of the switch terminals of the switching elements 1-1 to 1-n is bundled and connected to a common pad Common2. Further, a pad φ for opening and closing the switching elements 1-1 to 1-n in common is provided to provide switching pads 1-1 to 1-n.
Connect the control terminals of

FIG. 2 shows the timing of voltage application for measurement in this embodiment. The operation for the measurement will be described. First, a high voltage is applied to the pad φ to turn on all the switching elements 1-1 to 1-n, and conduct the pads A1 to An of all the blocks to Common2. . In this state, a high voltage is applied to Common2,
Set Common1 to low. As a result, a short circuit of the entire TEG pattern can be checked.

At this stage, if a short circuit has not occurred,
Since it is not necessary to check the short-circuit of each block any more, the check proceeds to the next chip. If there is a short circuit failure at this stage, the voltage of the pad φ is first set to low, and the pads A1 to An for each area are sequentially set to high for a predetermined time. This high time is pad A1
ＡAn is not overlapped, and each block is checked for a short circuit within a predetermined high time.

In this case, if a short circuit has not occurred in the first short-circuit check of the entire TEG, it is not necessary to check the short-circuit of each block. If the number is small, the measurement time can be greatly reduced, and if there is a short circuit, it is possible to check for each block, so that it is easy to detect a defective portion.

In the above description, the timing for applying a voltage to the pad to execute the measurement is created by an external circuit. However, a timing circuit can be built in a wafer.

FIG. 3 shows a pattern of a TEG for detecting a short circuit according to another embodiment of the present invention. In the present embodiment, switching elements 1-1 to 1-n are provided for each area, and one side of the switch terminals of the switching elements 1-1 to 1-n are bundled and connected to a common pad Common2. Also, pads φ1 to φn are provided for control terminals of the switching elements 1-1 to 1-n, respectively.
1 to 1-n are independently switched.

FIG. 4 shows the timing of voltage application for measurement in this embodiment. The operation for measurement will be described. First, a high voltage is applied to all the pads φ1 to φn to turn on all the switching elements 1-1 to 1-n, and to turn on the switching elements 1-1 to 1-n of all the blocks.
-Conduct the n side to Common2. In this state, Co
A high voltage is applied to monmon2, and Common1 is set to low. As a result, a short circuit of the entire TEG pattern can be checked.

At this stage, if no short circuit has occurred,
Since it is not necessary to check the short-circuit of each block any more, the check proceeds to the next chip. If there is a short circuit failure at this stage, first, the pad φ1 is set to high for a predetermined time, and the pads φ2 to φn other than the pad φ1 are set.
Are turned to low, the switching element 1-1 side of the area A1 is made conductive to Common2, and the area A1
Check for short circuit. When the short-circuit check of the area A1 is completed, the voltage of only the pad φ2 is set to high to check the short-circuit of the area A2.
Are set high for a predetermined time, and a short-circuit check of each block is performed within the predetermined time. These pad pads φ1 to φn
The high times should not overlap each other.

In this way, if a short circuit has not occurred in the first short-circuit check of the entire TEG, a short-circuit check for each individual block is not required. If the number is small, the measurement time can be greatly reduced, and if there is a short circuit, it is possible to check for each block, so that it is easy to detect a defective portion.

In the above description, the timing for applying the voltage to the pad to execute the measurement is created by an external circuit. However, a timing circuit can be built in the wafer.

According to the present invention, as described above, when the wiring short-circuit is checked, the wiring short-circuited portion can be specified while measuring the wiring yield in the wafer, so that the measurement time can be greatly reduced.

[0019]

As described above, according to the first aspect of the present invention, a test pattern including a plurality of test element groups for evaluating characteristics is provided on a semiconductor chip. By testing the test elements,
In a semiconductor device capable of evaluating the degree of achievement and reliability of the manufacturing process of a semiconductor chip, switch means capable of selecting whether to operate a plurality of test element groups as a whole or individually to operate a plurality of test element groups is provided. It is characterized by having. This makes it possible to realize a semiconductor device having a TEG for detecting a short circuit that can easily detect a defective portion and does not require much time for measurement by a relatively simple method.

The invention according to a second aspect of the present invention is characterized in that the switch means is provided in each of the plurality of test element groups and functions to operate the corresponding test element group. The invention according to claim 3 of the present invention is characterized in that the switch means is provided in each of the plurality of test element groups and functions so as to operate the plurality of test element groups as a whole or to separate the corresponding test element groups. Thus, it is possible to realize a semiconductor device capable of easily executing a test of the entire test element group and an individual test of the test element group by simple switching of the switch means.

According to a fourth aspect of the present invention, a test pattern including a plurality of test element groups for evaluating characteristics is provided on a semiconductor chip, and the plurality of test element groups of the test pattern are tested. Thus, in the method of manufacturing a semiconductor device having a test process capable of evaluating the achievement and reliability characteristics of the process of manufacturing the semiconductor chip, the test process includes an entire test process of testing a plurality of test element groups at once. The method is characterized by having an individual test process for individually testing a plurality of test element groups when a failure is detected in the entire test process. In this way, if there is no failure in the test of the entire test element group, individual tests can be omitted, so that a relatively simple method can easily detect a defective portion and does not require much time for measurement. A method of manufacturing a semiconductor device having an inspection process using a TEG for use can be realized.

[Brief description of the drawings]

FIG. 1 is a pattern diagram of a short-circuit detection TEG according to an embodiment of the present invention.

FIG. 2 is a timing chart of voltage application for measurement in the embodiment of FIG. 1;

FIG. 3 is a pattern diagram of a short-circuit detection TEG according to another embodiment of the present invention.

FIG. 4 is a timing chart of voltage application for measurement in the embodiment of FIG. 3;

FIG. 5 is a pattern diagram of an example of a conventional short-circuit detection TEG.

FIG. 6 is a pattern diagram of another example of a conventional short-circuit detection TEG.

[Explanation of symbols]

1-1 to 1-n: Switching element, 11: Measurement pad, 12: Test wiring pattern, A1 to An: Measurement pad, Common, Common1, Common
2: Common pad for measurement, φ, φ1 to φn: Control pad.

Claims (4)

[Claims] 1. A semiconductor chip manufacturing process comprising: providing a test pattern including a plurality of test element groups for characteristic evaluation on a semiconductor chip; and testing the plurality of test element groups of the test pattern. A semiconductor device capable of evaluating characteristics of the degree of achievement and reliability of the semiconductor device, further comprising switch means for selecting whether to operate the plurality of test element groups as a whole or to individually operate the plurality of test element groups. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein said switch means is provided in each of said plurality of test element groups and functions to operate a corresponding test element group. 3. The switch device according to claim 1, wherein said switch means is provided in each of said plurality of test element groups, and functions to operate said plurality of test element groups as a whole or to separate corresponding test element groups. 3. The semiconductor device according to claim 1. 4. A manufacturing process of a semiconductor chip by providing a test pattern including a plurality of test element groups for characteristic evaluation on a semiconductor chip and testing the plurality of test element groups of the test pattern. In the method of manufacturing a semiconductor device having an inspection process capable of evaluating the degree of achievement and reliability of the semiconductor device, the inspection process includes an entire test process of testing the entire test element group at once, and a defect in the entire test process. A method for manufacturing a semiconductor device, comprising: an individual test step of individually testing the plurality of test element groups when the detection is detected.