JPH1012826A - Semiconductor device and its testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten test period by, when a chip on a semiconductor wafer is tested, grouping a plurality of chips without moving a probe of a test device. SOLUTION: A test-dedicated circuit formed on a semiconductor wafer 1 and a chip selection circuit 5a are provided, and these components and a sample chip 2 are connected together with a wiring 3 of a bus configuration. The probe is required only to be connected to the test-dedicated circuit, and the arbitrary chip 2 and arbitrary grouping are allowed owing to selection pattern to the chip selection circuit 5a, so test period is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a test method therefor, and more particularly to a method for measuring electrical characteristics of a plurality of chips formed on a semiconductor wafer. The present invention relates to a semiconductor device with an improved method of selecting a chip and a test method thereof.

[0002]

2. Description of the Related Art An example of this type of conventional test means is described in Japanese Patent Application Laid-Open No. Hei 2-16564863. Referring to FIG. 8A which shows a plan view of a wafer state of the integrated circuit device described in the publication, and FIG. 8B which shows a partial plan view in which a thick solid line frame B portion of FIG. 8A is enlarged. Has one dedicated test chip 10 for each of the eight chips 2 formed on the semiconductor wafer 1. The dedicated test chip 10 includes an integrated circuit element 9 for a chip selection circuit and an integrated circuit element 9. A pad (hereinafter, referred to as a control signal pad) 8 for inputting / outputting a predetermined control signal is connected via a wiring.

The dedicated test chip 10 is a chip 2 to be measured.
(Hereinafter, referred to as measurement pads), and these measurement pads 7 and the integrated circuit element 9 for chip selection circuit are commonly connected by individual wiring. Further, the integrated circuit element 9 for the chip selection circuit and the pad 7a of each chip 2 to be measured are similarly commonly connected by individual wiring.

Next, the operation will be described.

First, a control signal pad 8 and a measurement pad 7 of a test-dedicated chip 10 are brought into contact with a probe for measuring electrical characteristics provided in a test apparatus set outside.
Next, a control signal is supplied from the test device to the chip selection circuit integrated circuit element 9 to select the chip 2 to be measured. A signal for an electrical characteristic test is supplied to the selected chip under test 2 via the test dedicated chip 10. Next, the chip selection circuit integrated circuit element 9 sends an output signal supplied from the selected chip under test 2 to the test device, and the test device determines whether the chip is good or defective.

After the test of the chip under test 2 is completed, another control signal is input to the integrated circuit element 9 for the chip selection circuit to select the next chip under test. A signal for an electrical characteristic test is given to the selected chip under test 2 to determine whether it is good or bad.

As described above, by sequentially inputting a control signal to the integrated circuit element 9 for a chip selection circuit, chips to be measured are sequentially selected and an electrical characteristic test is performed to determine good / bad.

When the test of the eight test chips 2 is completed, the control signal pad 8 and the measurement pad 7 of the next test chip 10 are brought into contact with the probe for the electrical characteristic test of the test apparatus. Then, in the same manner as described above, chips are sequentially selected for the eight chips to be measured 2 and the test is repeated.

When a grouping test is performed on the integrated circuit device having the above-described configuration, the grouping is performed for a maximum of eight chips.

Japanese Patent Laid-Open Publication No. Hei 4-366243 discloses a conventional semiconductor wafer setting means of this kind. Referring to FIG. 9 which shows a plan view of the entire semiconductor wafer described in the publication, the conventional test means includes a multiplexer 11 for switching the chip 2 to be measured, in addition to the chip 2 to be measured on the semiconductor wafer 1, It has a measurement pad 7 for sending a signal to the chip under test 2 and a control signal pad 8 for switching the multiplexer 11. Further, the chip under test 2 and the multiplexer 11 are connected to each chip 2 under test by individual wiring.

Next, the test operation of the semiconductor wafer will be described.

First, a probe is brought into contact with a measurement pad 7 for sending a signal to the chip 2 to be measured and a control signal pad 8 for switching the multiplexer 11. A control signal from the test apparatus is sent to the control signal pad 8, and the multiplexer 11 selects the chip under test 2 in response to the signal.

Next, a test signal is sent from the test apparatus to the measurement pad 7 and supplied to the chip via the multiplexer 11 to test the chip 2 to be measured.

When the test of the chip under test is completed, a switching signal is sent from the test equipment to the control signal pad 8,
The next chip to be measured is selected and tested, and the test of another chip to be measured is repeated in the same manner.

[0015]

As described above, among the test means of the conventional semiconductor device, in the example shown in FIG. 8, the wiring connecting the corresponding pads of the chip under test and the dedicated chip for test is not provided. In addition, a large number of test wirings are required for each chip to be measured, and one dedicated test chip is required for every eight chips. However, there is a problem that the number of chips that can be collected from one semiconductor wafer is reduced correspondingly and the cost of the chips is increased.

Also, even in the case of a grouping test, since only a maximum of eight chips can be combined, it is necessary to move the probe to the next group, and a test with an arbitrary chip and an arbitrary group is desired. However, there is a problem that the effect of reducing the test time is reduced.

Similarly, in the case of the conventional example shown in FIG. 9, there is a problem that the number of test wirings becomes enormous and the cost of the chip increases. Further, in order to wire all the measurement chips, the multiplexer needs to be horizontally long in the X-axis direction. Therefore, there is a problem that the number of chips that can be collected by the multiplexer is reduced.

Furthermore, even if a grouping test is performed by providing another circuit in addition to the multiplexer, there is a problem that a pattern for selecting an arbitrary group and an arbitrary measurement chip becomes complicated due to the complexity of the circuit.

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above-mentioned drawbacks. When testing chips formed on a semiconductor wafer, a probe for measurement provided in a test apparatus is mounted on one wafer. It is an object of the present invention to provide a semiconductor device and a test method thereof, in which a test time can be reduced by setting a plurality of chips in the same chip without moving once set during measurement and by grouping a plurality of chips in the same chip.

[0020]

The semiconductor device according to the present invention is characterized in that a group of chips to be measured and one test chip having a function of selecting these chips are formed on a semiconductor wafer. The input / output pads of the chip and the dedicated test chip are arranged in the same pad arrangement state, and both corresponding pads are commonly connected by individual wiring, and the dedicated test chip separates the chip group to be measured. A test means for sequentially measuring the chip to be measured selected by the chip selecting means by bringing a measuring probe into contact with the pad of the test dedicated chip during a test. In the semiconductor device provided, a bus between the corresponding pads of the chip under test and the dedicated chip for test is replaced with the individual wiring. It is to connect the common wiring formed.

Further, the test means includes one test-dedicated chip and second switch selection means in place of the first chip selection means, and corresponds to each pad of the chip to be measured. A switch group for connecting the bus and at least one second chip selection unit for controlling on / off of these switch groups are arranged around the chip to be measured so as to surround the chip, and for each of the chips to be measured. The second chip selecting means disposed,
By controlling from an external test apparatus via the dedicated test chip, any desired chip under test is selected and connected to a pad group of the dedicated test chip.

Further, a control line connecting the second chip selecting means and the switch group is wired in series.

Further, the second chip selecting means and the switch group are arranged in a peripheral region in the chip to be measured so as to surround the pad group.

Further, two sets of the second chip selecting means are arranged in parallel connection.

Further, the second chip selecting means selects one of the chip to be measured and an input terminal of a control signal provided from the test apparatus or the second selecting means at the preceding stage, a reset signal input terminal, and one of the chips to be measured. Only a signal input terminal, a select signal input terminal for selecting two of the chips under test, a signal output terminal for controlling only the switch corresponding to only the input terminal of the chip under test, and an output terminal of the chip under test It has a signal output terminal for controlling only the switch and a control signal output terminal for the next stage selection means.

The test method of the semiconductor device according to the present invention is characterized in that a group of chips to be measured and a plurality of test-dedicated chips each having a function of selecting these chips are formed on a semiconductor wafer. The input / output pads to / from the dedicated test chip are arranged in the same pad arrangement, both corresponding pads are commonly connected by individual wiring, and the dedicated test chip individually selects the chip group to be measured. In a test method for a semiconductor device, a test probe is brought into contact with the pad of the test-only chip at the time of testing by using the first chip selecting means, and the chip under test selected by the chip selecting means is sequentially measured. Use only one test chip,
Further, between the pads of the chip under test and the dedicated chip for test, a common wiring having a bus configuration and the group of chips under test are individually or simultaneously selected in place of the individual wiring and the first chip selecting means. And a switch group that is arranged around the chip under test and connects each pad of the chip under test with the corresponding bus. By controlling from an external test device via the chip selection control means 2 of the above, any of the chips to be measured are selected and electrically connected to the pads of the test-dedicated chip in order, and these connected chips are connected. The measurement probe is brought into contact with a pad group of a dedicated test chip, and this contact state is maintained until measurement of one semiconductor wafer is completed. It is to sequentially measure the measured chip and.

Further, the control signal, which is maintained at a high level for at least one clock period of a clock signal supplied from the test apparatus by the second chip selecting means, is supplied, and the control signal synchronized with the clock signal is supplied. Controlling the switch corresponding to a period during which the signal is active;
Activating the control signal for a plurality of clock periods to select the plurality of switches as one group;
All of the chips in the selected group are measured simultaneously.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device according to the present invention, a probe of a test apparatus for measuring electrical characteristics of a chip formed on a semiconductor wafer is used as a measuring pad 7 of a dedicated test circuit 4.
Then, the pattern is brought into contact with the control signal pad 8 and a pattern for selecting a measurement chip is sent from the test apparatus to the chip selection circuit 5a. At this time, the switch 6 that passes a signal to the pad 7a of each chip is turned on and off through the chip selection circuit 5a according to a pattern from the test apparatus, and the chip to be measured can be tested.

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view showing a wiring group for connecting between a chip formed on a semiconductor wafer and chip selecting means according to an embodiment of the present invention, and FIG. 2 is a dotted frame portion of FIG. It is the top view which expanded A. FIG. 3A is a block diagram of the chip selection circuit 5a, and FIG. 3B is a timing chart for explaining a test method of each chip.

Referring to FIG. 1, a plurality of chips 2 on a semiconductor wafer 1, a wiring 3 connecting these chips 2 in a bus configuration and a common connection, and a plurality of chips 2 Test dedicated circuit 4 formed for control
The wiring 3 has a multilayer structure of two or more wiring layers.

Wiring 3 commonly connected in this bus configuration
Connects the pads 7a arranged in the internal peripheral region of the plurality of chips 2 to the measurement pads 7 arranged in the internal peripheral region of the test dedicated circuit 4 for controlling the plurality of chips 2.

Since the wiring 3 has a bus structure, the pads 7 on the four sides of the dedicated test circuit 4 located at the center of the semiconductor wafer
Wirings 3 arranged at right angles from the group and connected to these wirings 3 and arranged in parallel with these wirings 3 are arranged on a wiring area between the chips 2 and A bus is configured.

Referring to FIG. 2, a chip selection circuit 5a for selecting a plurality of chips 2 and a switch 6 whose on / off is controlled by an output signal of the chip selection circuit 5a
The group of switches 6 is arranged along the periphery of the semiconductor chip 2 so as to surround the semiconductor chip 2, and the chip selection circuit 5 a is arranged, for example, around the corner of the chip 2.

One of the control signal lines 3a is a clock signal line supplied from the test apparatus via the test dedicated circuit 4, and is connected to the clock signal input terminals of all the chip selection circuits 5a. Wiring 3b for the other control signal
Is a data wiring supplied from the test apparatus via the dedicated test circuit 4 to select which chip is to be measured.

One output wiring 3d of the chip selection circuit 5a
Are connected as data lines of the chip selection circuit 5a connected to the next stage. That is, the all-chip selection circuit 5a has a shift register configuration.

The switch wiring 3c of the other output of the chip selection circuit 5a is connected to the control terminal of the switch 6 connected between the measurement pad 7 of the test dedicated circuit 4 and the pad 7a of each chip 2. One of the input / output terminals of the switch group 6 is connected to a pad 7a of the chip under test 2, and the other input / output terminal is connected to a corresponding bus. The test of the chip under test 2 can be performed by turning on and off the switch 6.

Referring to FIG. 1, FIG. 2 and FIG. 3 together, the timing chart of FIG.
a indicates that the measurement of each chip is enabled.

First, when measuring the chips 2 to be measured formed on the semiconductor wafer 1 one chip at a time, data for one clock is input from the test dedicated circuit 4 to the first chip selection circuit 5a. At that time, the chip selection circuit 5a reads the pattern at the falling timing of the first clock, and outputs Q and Q at the falling timing of the next clock.
QB changes, and the switch Q of the first chip is turned on under the control of the output Q, so that the first chip is selected.

That is, the section A in FIG. 3B is a pattern in a state where the first chip is selected and the test is possible, and the test of the first chip is performed during the section A.

Next, when the next clock is input to the chip selection circuit 5a, the switch 6 of the first chip selected so far is turned off, and the first chip selection circuit 5a is turned off.
The second chip selection circuit 5a reads the pattern at the falling timing of the second clock from the output Q (3d) transferred from the second clock, and the outputs Q and QB change at the falling timing of the next clock. 2 controlled by output Q
The switch 6 of the second chip is turned on, and the second chip is selected. At this time, a test of the second chip is performed.

As described above, by inputting data for one clock, selection is made in order from the first chip to the last chip. At this time, the probe of the test apparatus is kept in contact with the pad of the test circuit 4. Since each chip can be tested without moving the probe, the test time can be reduced.

When measuring only an arbitrary chip,
If the clock is moved by an arbitrary chip number, that is, the output Q
Is shifted by that amount, it is possible to measure only an arbitrary chip.

Next, in the case of measuring two chips at a time, data that has been high level for a period of two clocks from the test dedicated circuit 4 is supplied to the first chip selection circuit 5a. At that time, the chip selection circuit 5a reads the pattern at the falling timing of the first clock, the outputs Q and QB change at the falling timing of the third clock, and the second chip selection circuit 5a reads the second clock. The output Q of the preceding stage is read at the fall timing, and the outputs Q and QB change at the fall timing of the fourth clock.

Under the control of the output Q, the switches 6 of the first and second chips are turned on, and 1
The second and the second two chips are selected.

That is, the section B in FIG.
This is a pattern in a state where the second chip is selected and simultaneous testing is possible.

Similarly, when the next two clocks are again input to the chip selection circuit 5a, the switches 6 of the first and second chips that have been selected are turned off, and the switches 6 are transferred from the second chip selection circuit 5a. Output Q
(3d) The third chip selection circuit 5a reads the pattern at the falling timing of the third clock, and
Output Q and QB at the falling timing of the second clock
And the fourth chip selection circuit 5a reads the output Q of the preceding stage at the falling timing of the third clock, and
The outputs Q and QB change at the falling edge of the clock. Controlled by the output Q, the switches 6 of the third and fourth chips are turned on, respectively, and the third and fourth two chips are selected.
At this time, the third and fourth chips are tested.

With the above-described operation, two chips can be grouped and measured simultaneously, and the test time can be further reduced.

Similarly to the measurement of two chips, the measurement of three chips is performed by inputting data for three clocks from the dedicated test circuit 4 and inputting three clocks. be able to.

For example, when the following measuring method is performed,
The test time can be greatly reduced. At first, all the chips on the semiconductor wafer are divided into two groups and the test is performed. Only the group with a bad test result is again divided into two groups and the test is performed. Only the group whose test result is bad is divided into two groups again and the test is performed. By repeating these, the test time can be significantly reduced.

Next, referring to FIG. 4 which shows a modification of the embodiment in a plan view, the difference from the embodiment is that the chip selection circuit 5a is provided at the corner of the chip, and the switch 6 is provided. The pads are arranged in a peripheral region in each chip so as to surround the pad group.

The other configuration is the same as that of the embodiment, and the same components are denoted by the same reference numerals, and the description of the configuration is omitted.

As described above, even if the chip selection circuit 5a and the switch 6 are mounted in each chip, the same effect as in the embodiment can be obtained.

Next, as another modified example of the embodiment,
Referring to FIG. 5A showing a block diagram of the chip selection circuit 5b and FIG. 5B showing a truth table thereof, the chip selection circuit 5b is a modified example of the chip selection circuit 5a and includes a clock signal. An input terminal C, an input terminal D for a control signal provided from the test dedicated circuit 4 or the chip selection circuit in the preceding stage, a reset signal input terminal R, a select signal input terminal S1 for selecting one chip under test 2, A select signal input terminal S2 for selecting two measurement chips 2;
A signal output terminal QI for controlling only the switch 6 corresponding to only the input terminal of the chip under test 2; a signal output terminal QO for controlling only the switch 6 corresponding to only the output terminal of the chip 2 to be measured; And a control signal output terminal Q to the selection circuit 5a.

With such a configuration of the chip selection circuit 5b, the initial setting of the chip selection circuit 5b and the setting of the input terminal switch and the output terminal switch can be performed independently. A grouping test of only the output terminals becomes possible.

The operation when the chip selection circuit 5b is used instead of the chip selection circuit 5a in the above-described embodiment and its modification will be described with reference to FIGS. 1, 2, 5 and 6. . When grouping measurement is performed only on the input terminals of two chips, data for two clocks is input from the test dedicated circuit 4 to the first chip selection circuit 5b.

At this time, the outputs Q and Q of the chip selection circuit 5b
B is the data D at the falling timing of the first clock.
And outputs a high level, and changes to a low level at the falling timing of the third clock. In response to the output Q, the switch 6 of the first chip is turned on, and
The th chip is in the selected state.

When the clock is input again, the switches 6 of the first and second chips are turned on, and the first and second chips are selected.

At this time, the selectors S1 and S2 each have 1
When the level and the 0 level are input, only the switch 6 for the input terminal is turned on.

That is, the section D in FIG. 6 is a pattern in which only the input terminals of the first and second chips are selected, and the simultaneous test of the input terminals of the two chips is possible.

Next, in FIG.
FIG. 7 is a plan view showing another modified example of the dotted frame portion A of FIG.
Is different from the embodiment in that two chip selection circuits 5a are connected in parallel. The circuit operation of this configuration is the same as that of the single chip selection circuit 5a. However, if the chip selection circuit 5a fails, it becomes impossible to select an arbitrary chip. In parallel, it is possible to prevent an arbitrary chip from being unselectable due to a failure of the chip selection circuit 5a.

Further, in order to eliminate the failure of the bus configuration wiring 3 and the test dedicated circuit 4, the bus configuration wiring is made as thick as possible, and no extra circuit is mounted on the test dedicated circuit 4. In the worst case, when a failure occurs in the wiring of the bus configuration or the test-dedicated circuit, the test-dedicated circuit 4 and each chip under test 2 can be switched to the test by the conventional method by setting the same pad position to the same pad position. Becomes

In the above-described embodiment and its modified example, a probe is used for inputting and outputting a signal by contacting with a pad. For example, the same applies to all bump-type probe boards.

[0064]

According to the semiconductor device and the test method of the present invention described above, the corresponding pads of the chip under test and the dedicated chip for test are connected by a common wiring having a bus configuration instead of the individual wiring, and As selection means, a switch group for connecting each pad of the chip to be measured and a bus corresponding thereto and at least one chip selection means for controlling on / off of these switch groups are arranged around the chip to be measured so as to surround the chip. Since the chip selecting means arranged for each chip to be measured is controlled from an external test device, an arbitrary chip to be measured is selected and connected to a pad group of a chip dedicated for testing.
The first effect is that the chip to be measured can be arbitrarily selected, and the test can be performed with an arbitrary grouping. As a result, the test time can be reduced.

The reason for this is that each chip has been good.
This is because, although the failure is determined, by performing the grouping test, the test time is shortened by the grouping. For example, if there are 1000 chips to be measured on one semiconductor wafer and all the chips are subjected to the IDD test, the time will be 1/1000 hours at the maximum.

The second effect is that the number of test wirings is reduced. Since the number of chips that can be collected from one semiconductor wafer increases, the cost of the chips can be reduced.

The reason for this is that the test wiring occupying one semiconductor wafer is reduced because the test wiring has a bus configuration.

A third effect is that the test equipment can be made cheaper. This will be reflected in the cost of the chip.

The reason is that a high-precision test apparatus for accurately contacting the pads of each chip is not required.

The fourth effect is that the life of the probe is extended. Therefore, the cost of the chip can be reduced.

The reason is that the probe, which has been in contact with the pad of each chip for each chip to be measured every time, can now be contacted only once.

[Brief description of the drawings]

FIG. 1 is a plan view of an entire semiconductor wafer showing an embodiment of the present invention.

FIG. 2 is an enlarged plan view of a dotted frame portion A in FIG.

FIG. 3 is a timing chart for explaining the operation of the embodiment.

FIG. 4 is a plan view showing a modification of the dotted frame portion A in FIG.

FIG. 5A is a block diagram of a chip selection circuit 5b in which the chip selection circuit 5a in FIG. 4 is modified. FIG. 13B is a diagram illustrating a truth table of the chip selection circuit 5b.

FIG. 6 is a timing chart for explaining operation when the chip selection circuit 5b is used.

FIG. 7 is a plan view showing another modified example of the dotted frame portion A in FIG. 1;

8A is a plan view of an entire semiconductor wafer for explaining a conventional integrated circuit device. FIG. 8B is a partial plan view showing a conventional integrated circuit device in which a portion B in FIG. 8A is enlarged. is there.

FIG. 9 is a plan view of an entire semiconductor wafer showing another conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor wafer 2 chip under test 3 wiring 3a chip selection circuit clock wiring 3b chip selection circuit data wiring 3c switch wiring 3d next-stage chip selection circuit data wiring 4 test-dedicated circuits 5a, 5b chip selection circuit 6 switch 7 Measurement pad 7a Pad 8 Control signal pad 9 Integrated circuit element for chip selection circuit 10 Test dedicated chip 11 Multiplexer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 21/66 H01L 21/82 D 21/82

Claims (8)

[Claims] 1. A group of chips to be measured and one dedicated test chip having a function of selecting these chips are formed on a semiconductor wafer, and input / output pads of the plurality of chips and the dedicated test chip are mutually connected. Are arranged in the same pad arrangement state, both corresponding pads are commonly connected by individual wiring, and the test-specific chip has first chip selecting means for individually selecting the chip group to be measured. In a semiconductor device having test means for sequentially measuring the chip to be measured selected by the chip selecting means by bringing a measurement probe into contact with the pad of the chip for test only during the test, the chip to be measured and the test The semiconductor device according to claim 1, wherein the corresponding pads of the dedicated chip are connected by a common wiring having a bus configuration instead of the individual wiring. Body device. 2. The test means includes one test-dedicated chip and second chip select means in place of the first chip select means, and corresponds to each pad of the chip under test. A switch group for connecting the bus and at least one second chip selection unit for controlling on / off of these switch groups are arranged around the chip to be measured so as to surround the chip, and for each of the chips to be measured. By controlling the arranged second chip selecting means from an external test apparatus via the dedicated test chip, any desired chip to be measured is selected and connected to a pad group of the dedicated test chip. 2. The semiconductor device according to claim 1, wherein the semiconductor device is configured. 3. The semiconductor device according to claim 2, wherein a control line connecting said second chip selection means and said switch group is wired in series. 4. The semiconductor device according to claim 2, wherein said second chip selecting means and said switch group are arranged in a peripheral region in said chip under test so as to surround said pad group. 5. The semiconductor device according to claim 2, wherein two sets of said second chip selection means are arranged in parallel connection. 6. A select for selecting one of the chip to be measured and an input terminal of a control signal, a reset signal input terminal, and a control signal supplied from the test apparatus or the second selector of a preceding stage. Only a signal input terminal, a select signal input terminal for selecting two of the chips under test, a signal output terminal for controlling only the switch corresponding to only the input terminal of the chip under test, and an output terminal of the chip under test 3. The semiconductor device according to claim 2, further comprising: a signal output terminal for controlling only the switch; and a control signal output terminal to a next-stage selection unit. 7. A chip group to be measured and a plurality of dedicated test chips having a function of selecting these chips are formed on a semiconductor wafer, and input / output pads of the plurality of chips and the test dedicated chip are mutually connected. And the corresponding pads are connected in common by individual wiring, and the dedicated test chip performs test by using first chip selecting means for individually selecting the chip group to be measured. Sometimes, in a test method of a semiconductor device in which a measurement probe is brought into contact with the pad of the test dedicated chip to sequentially measure the chip to be measured selected by the chip selecting means, only one test dedicated chip is used, Further, the space between the pads of the chip under test and the chip dedicated for test is replaced by the individual wiring and the first chip selecting means. In addition, a common wiring having a bus configuration and second chip selecting means for individually or simultaneously selecting a plurality of the chips to be measured are used, and are arranged around the chip to be measured and each of the pads of the chip to be measured. A switch group for connecting to the corresponding bus is controlled from an external test apparatus via the test dedicated chip and at least one of the second chip selection control means, thereby selecting an arbitrary chip to be measured. Electrically connected to the test-dedicated chip pads in sequence, bringing the measurement probe into contact with the connected test-dedicated pads, and measuring this contact state with one semiconductor wafer. A test method for a semiconductor device, wherein the chips to be measured are sequentially measured while maintaining the measurement until the end. 8. The control signal, wherein the control signal is maintained at a high level for at least one clock period of the clock signal supplied from the test device by the second chip selecting means,
Controlling the switch corresponding to a period in which the control signal synchronized with the clock signal is active, selecting the plurality of switches as one group by activating the control signal for a plurality of clock periods, 8. The method according to claim 7, wherein all of the selected chips in the group are measured simultaneously.