JPH11297754A - Board - Google Patents
BoardInfo
- Publication number
- JPH11297754A JPH11297754A JP9491698A JP9491698A JPH11297754A JP H11297754 A JPH11297754 A JP H11297754A JP 9491698 A JP9491698 A JP 9491698A JP 9491698 A JP9491698 A JP 9491698A JP H11297754 A JPH11297754 A JP H11297754A
- Authority
- JP
- Japan
- Prior art keywords
- test pad
- substrate
- pitch
- width
- product
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000011295 pitch Substances 0.000 claims abstract description 19
- 238000003780 insertion Methods 0.000 claims abstract description 7
- 230000037431 insertion Effects 0.000 claims abstract description 7
- 238000011156 evaluation Methods 0.000 abstract description 6
- 238000000059 patterning Methods 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Landscapes
- Wire Bonding (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
(57)【要約】
【課題】半導体製品の評価・解析用基板に関する。最終
形状に切断された後のＴＣＰ製品を評価・解析する場
合、製品毎に端子のピッチと幅が異なるため、製品仕様
に応じて基板を開発していた。
【解決手段】プリント基板の表・裏両面に複数のピッチ
と幅を有するテストパットを直列にコネクター挿入部ま
で結線し、コネクターを介して電気信号を与えることの
できる構造とした。ベース基板１０１にテストパット１
０２を形成するが、テストパットの幅１０３とテストパ
ットのピッチ１０４の異なるパターンを形成し、テスト
パット１０２を直列に結線１０５する。テストパットの
幅１０３とテストパットのピッチ１０４は、製品仕様に
合わせて設定しベース基板１０１上に複数パターニング
することで、汎用性を持たせることが可能となる。テス
トパット１０２と結線１０５は電気的な導通の取り易い
金属（はんだや金）などとする。
(57) [Summary] A substrate for evaluation and analysis of semiconductor products. When evaluating and analyzing a TCP product that has been cut into a final shape, since the pitch and width of the terminal differ for each product, a substrate has been developed according to the product specifications. A test pad having a plurality of pitches and widths is serially connected to a connector insertion portion on both front and back surfaces of a printed circuit board, and an electric signal can be given via the connector. Test pad 1 on base substrate 101
No. 02 is formed, but a pattern having a different test pad width 103 and a different test pad pitch 104 is formed, and the test pads 102 are connected 105 in series. The width 103 of the test pad and the pitch 104 of the test pad are set in accordance with the product specifications, and by patterning a plurality of patterns on the base substrate 101, versatility can be provided. The test pad 102 and the connection 105 are made of a metal (solder or gold) or the like that is easily electrically connected.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体製品の評価
・解析用基板に関する。The present invention relates to a substrate for evaluating and analyzing semiconductor products.
【０００２】[0002]
【従来の技術】従来、最終形状に切断されたＴＣＰ（テ
ープキャリアーパッケージ）製品の評価・解析を行う場
合、製品毎に入力信号用端子のピッチとパターン幅が異
なるため、個々の製品に対して評価用基板を開発してい
た。2. Description of the Related Art Conventionally, when evaluating and analyzing a TCP (tape carrier package) product cut into a final shape, a pitch of an input signal terminal and a pattern width are different for each product. An evaluation board was being developed.
【０００３】[0003]
【発明が解決しようとする課題】しかし、従来の基板
は、製品毎に基板を製造していたため、基板１枚で複数
の製品を評価することができず汎用性が全く無いといっ
た問題点を有していた。However, the conventional substrate has a problem in that since a substrate is manufactured for each product, a plurality of products cannot be evaluated with one substrate, and there is no general versatility. Was.
【０００４】[0004]
【課題を解決するための手段】上記課題を解決するた
め、本発明の基板は、１枚の基板に複数のピッチと幅を
有したテストパットを設け、それらを電気的に結線する
ことを特長とする。また、基板両面にパターンを形成す
ることで２倍の汎用性が得られる。In order to solve the above-mentioned problems, the substrate of the present invention is characterized in that a single substrate is provided with a plurality of test pads having a plurality of pitches and widths, and the pads are electrically connected. And Further, by forming a pattern on both surfaces of the substrate, double versatility can be obtained.
【０００５】[0005]
【作用】上記のようにパターニングされた基板を製造す
ると、ＴＣＰのような半導体製品を評価する際、あらか
じめ製品仕様に合わせた複数のピッチと幅を形成してお
くことで１枚の基板を用いて複数の製品評価・解析が出
来るのである。When a substrate patterned as described above is manufactured, when evaluating a semiconductor product such as TCP, a plurality of pitches and widths are formed in advance according to the product specifications so that one substrate can be used. It is possible to evaluate and analyze multiple products.
【０００６】[0006]
【発明の実施の形態】以下に本発明の実施例を図面にも
とづいて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【０００７】図１は、本発明の平面図（表面図）であ
り、１０１はベース基板、１０２はテストパット、１０
３はテストパットの幅、１０４はテストパットのピッ
チ、１０５はテストパット間の結線、１０６はコネクタ
ー挿入部である。FIG. 1 is a plan view (surface view) of the present invention, wherein 101 is a base substrate, 102 is a test pad,
3 is the width of the test pad, 104 is the pitch of the test pad, 105 is the connection between the test pads, and 106 is the connector insertion portion.
【０００８】ここでベース基板１０１にテストパット１
０２を形成するが、テストパットの幅１０３とテストパ
ットのピッチ１０４の異なるパターンを形成し、テスト
パット１０２を直列に結線１０５する。テストパットの
幅１０３とテストパットのピッチ１０４は、製品仕様に
合わせて設定しベース基板１０１上に複数パターニング
することで、汎用性を持たせることが可能となる。テス
トパット１０２と結線１０５は電気的な導通の取り易い
金属（はんだや金）などとするが、これ以外の金属
（銅）を用いることも可能である。Here, the test pad 1 is mounted on the base substrate 101.
No. 02 is formed, but a pattern having a different test pad width 103 and a different test pad pitch 104 is formed, and the test pads 102 are connected 105 in series. The width 103 of the test pad and the pitch 104 of the test pad are set in accordance with the product specifications, and by patterning a plurality of patterns on the base substrate 101, versatility can be provided. The test pad 102 and the connection 105 are made of a metal (solder or gold) or the like that is easily electrically conductive, but other metals (copper) can be used.
【０００９】図２は本発明の平面図（裏面図）であり、
２０１、２０２、２０３は表側とは異なるピッチと幅を
有したテストパットであり、裏面側にもパターニングす
ることで２倍の汎用性を持たすことが出来る。FIG. 2 is a plan view (back view) of the present invention.
Reference numerals 201, 202, and 203 denote test pads having a different pitch and width from the front side. By patterning the back side, double versatility can be obtained.
【００１０】また、コネクター挿入部１０６を設けるこ
とによって、コネクターを介して外部から電気信号を与
えることで評価・解析が容易に行うことができる。Further, by providing the connector insertion portion 106, evaluation and analysis can be easily performed by supplying an electric signal from outside through the connector.
【００１１】図３は本発明の平面図（評価・解析状態を
表した図）であり、３０１はＴＣＰのＩＣチップ、３０
２はＴＣＰの信号入力用端子、３０３は液晶パネルであ
る。FIG. 3 is a plan view of the present invention (a diagram showing the state of evaluation and analysis). Reference numeral 301 denotes a TCP IC chip;
Reference numeral 2 denotes a TCP signal input terminal, and reference numeral 303 denotes a liquid crystal panel.
【００１２】本発明は、ＴＣＰの信号入力用端子３０２
をテストパット１０２にはんだ付けし、液晶パネル駆動
用ＴＣＰの場合、本発明のコネクター挿入部１０６から
電気信号を与えることで液晶パネルの表示品質の確認が
可能となる。According to the present invention, a TCP signal input terminal 302 is provided.
Is soldered to the test pad 102 and, in the case of a liquid crystal panel driving TCP, by applying an electric signal from the connector insertion portion 106 of the present invention, the display quality of the liquid crystal panel can be confirmed.
【００１３】このように、種々のピッチ、幅を有したテ
ストパットをあらかじめプリント基板上にパターニング
しておくことによって、最終形状に切断されたＴＣＰ製
品の評価・解析を可能とし、ＴＣＰ製品の信頼性向上を
図ることができる。As described above, by preliminarily patterning test pads having various pitches and widths on a printed circuit board, it is possible to evaluate and analyze a TCP product cut into a final shape, thereby improving the reliability of the TCP product. Performance can be improved.
【００１４】[0014]
【発明の効果】本発明の基板は、以上説明したように、
複数のピッチと幅のテストパットを直列に結線するとい
う簡単な構造によって、製品毎に基板を製造することな
く１枚の基板で複数製品の評価・解析を実施できる効果
がある。As described above, the substrate of the present invention has the following features.
With a simple structure in which test pads of a plurality of pitches and widths are connected in series, there is an effect that evaluation and analysis of a plurality of products can be performed on one board without manufacturing a board for each product.
【００１５】また、基板のコネクター挿入部の形状を規
格化されたものと同一にすることによってコネクターを
介して外部から容易に電気信号を取り入れることが可能
となり非常に便利である。Further, by making the shape of the connector insertion portion of the board the same as that standardized, it is possible to easily take in an electric signal from the outside via the connector, which is very convenient.
【図１】本発明の基板の平面図（表面図）である。FIG. 1 is a plan view (surface view) of a substrate of the present invention.
【図２】本発明の基板の平面図（裏面図）である。FIG. 2 is a plan view (back view) of the substrate of the present invention.
【図３】本発明の基板の平面図（評価・解析状態を表し
た図）である。FIG. 3 is a plan view (a diagram showing a state of evaluation and analysis) of the substrate of the present invention.
１０１・・・ベース基板 １０２・・・テストパット １０３・・・テストパットの幅 １０４・・・テストパットのピッチ １０５・・・テストパット間の結線 １０６・・・コネクター挿入部 ２０１・・・テストパット（ピッチ、幅 大） ２０２・・・テストパット（ピッチ、幅 中） ２０３・・・テストパット（ピッチ、幅 小） ３０１・・・ＴＣＰのＩＣチップ ３０２・・・ＴＣＰの信号入力用端子 ３０３・・・液晶パネル DESCRIPTION OF SYMBOLS 101 ... Base board 102 ... Test pad 103 ... Test pad width 104 ... Test pad pitch 105 ... Connection between test pads 106 ... Connector insertion part 201 ... Test pad (Pitch, width large) 202: Test pad (pitch, width medium) 203: Test pad (pitch, width small) 301: TCP IC chip 302: TCP signal input terminal 303 ..Liquid crystal panels
Claims (4)
るテストパットを設け、各々のテストパットを結線する
ことを特長とする基板。1. A board characterized in that test pads having a plurality of pitches and widths are provided on a printed board, and each test pad is connected.
直列に結線させることを特長とする基板。2. A substrate characterized in that test pads having a plurality of pitches and widths are connected in series.
ットが基板の表裏両面にパターニングされていることを
特長とする基板。3. A substrate characterized in that the test pads connected in series according to claim 2 are patterned on both front and back surfaces of the substrate.
ットに、外部から電気信号を与えられるようコネクター
差し込み構造を設けたことを特長とする基板。4. A board characterized in that a connector insertion structure is provided on the test pads connected in series according to claim 2 so that an electric signal can be given from outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9491698A JPH11297754A (en) | 1998-04-07 | 1998-04-07 | Board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9491698A JPH11297754A (en) | 1998-04-07 | 1998-04-07 | Board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11297754A true JPH11297754A (en) | 1999-10-29 |
Family
ID=14123333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9491698A Withdrawn JPH11297754A (en) | 1998-04-07 | 1998-04-07 | Board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11297754A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030043599A (en) * | 2001-11-27 | 2003-06-02 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device having a semiconductor chip and a lead substrate connected with each other through pads and patterned lead wires without short-circuiting the pads |
| KR100443906B1 (en) * | 2000-10-02 | 2004-08-09 | 삼성전자주식회사 | chip scale package, printed circuit board, and method of designing a printed circuit board |
| CN115166375A (en) * | 2022-07-27 | 2022-10-11 | 景旺电子科技(珠海)有限公司 | Insertion loss test port |
-
1998
- 1998-04-07 JP JP9491698A patent/JPH11297754A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100443906B1 (en) * | 2000-10-02 | 2004-08-09 | 삼성전자주식회사 | chip scale package, printed circuit board, and method of designing a printed circuit board |
| KR20030043599A (en) * | 2001-11-27 | 2003-06-02 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device having a semiconductor chip and a lead substrate connected with each other through pads and patterned lead wires without short-circuiting the pads |
| CN115166375A (en) * | 2022-07-27 | 2022-10-11 | 景旺电子科技(珠海)有限公司 | Insertion loss test port |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20050607 |