JPH0563331A - Printed circuit board - Google Patents

Printed circuit board

Info

Publication number
JPH0563331A
JPH0563331A JP3221993A JP22199391A JPH0563331A JP H0563331 A JPH0563331 A JP H0563331A JP 3221993 A JP3221993 A JP 3221993A JP 22199391 A JP22199391 A JP 22199391A JP H0563331 A JPH0563331 A JP H0563331A
Authority
JP
Japan
Prior art keywords
soft
pad
gold plating
circuit board
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3221993A
Other languages
Japanese (ja)
Inventor
Kiyoshi Tomita
清 冨田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Ibaraki Ltd
Original Assignee
NEC Ibaraki Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Ibaraki Ltd filed Critical NEC Ibaraki Ltd
Priority to JP3221993A priority Critical patent/JPH0563331A/en
Publication of JPH0563331A publication Critical patent/JPH0563331A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To satisfy the respective functions of an OLD pattern and an I/O pattern and moreover, to make it possible to form simultaneously both of the patterns by a method wherein soft gold-plated patterns are respectively formed on the lowest layers of both of the OLD pattern and the I/O pattern, hard gold-plated patterns are respectively formed on the intermediate layers thereon and soft gold-plated patterns are respectively formed on the uppermost layers thereon. CONSTITUTION:Soft gold-plated patterns 2 containing soft crystal grains are respectively formed using a soft type gold plating solution on the lowest layers of both of an OLD pad 7 for bonding leads 4 of an IC 5 on a board parent material 1 and an I/O pad 8 for installing a connector terminal 6 for installation use on a host device, hard gold-plated patterns 3 containing a cobalt metal are respectively formed using a hard type gold plating solution on the intermediate layers thereon and moreover, soft gold-plated patterns 2 containing soft crystal grains are respectively formed on the uppermost layers thereon. By this constitution, the pads 7 and 8 are both satisfied their respective functions, which are required to them, and moreover, it becomes possible to form both pads simultaneously.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は印刷回路基板に関し、特
にＴＡＢチップタイプのＩＣのリードをボンディングす
るためのＯＬＢパッドと、上位装置に装着するためのコ
ネクタ端子用のＩ／Ｏパッドとを有する印刷回路基板に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board, and more particularly, it has an OLB pad for bonding a lead of a TAB chip type IC and an I / O pad for a connector terminal to be mounted on a host device. The present invention relates to a printed circuit board.

【０００２】[0002]

【従来の技術】図２は従来の印刷回路基板の一例を示す
断面図である。2. Description of the Related Art FIG. 2 is a sectional view showing an example of a conventional printed circuit board.

【０００３】テープ・オートメイテッド・ボンディング
（Ｔａｐｅ ＡｕｔｏｍａｔｅｄＢｏｎｄｉｎｇ）チッ
プタイプ（ＴＡＢチップタイプ）のＩＣのリードをボン
ディングするためのアウタ・リード・ボンディング（Ｏ
ｕｔｅｒ Ｌｅａｄ Ｂｏ−ｎｄｉｎｇ）パッド（ＯＬ
Ｂパッド）と、上位装置に装着するためのコネクタ端子
用のインプット・アウトプット（ＩＮＰＵＴ／ＯＵＴＰ
ＵＴ）パッド（Ｉ／Ｏパッド）とを有する従来の印刷回
路基板は、ＯＬＢパッドとＩ／Ｏパッドに要求される機
能が異るため、２種類の金めっき液を使用して、ＯＬＢ
パッドとＩ／Ｏパッドとを、それぞれ独立にパターン形
成を行っている。Outer lead bonding (O) for bonding the leads of a tape automated bonding chip type (TAB chip type) IC
uter Lead Bo-nding pad (OL
B pad) and input / output (INPUT / OUTP) for connector terminals to be mounted on the host device
The conventional printed circuit board having the (UT) pad (I / O pad) has different functions required for the OLB pad and the I / O pad.
The pad and the I / O pad are formed independently of each other.

【０００４】すなわち、図２に示すように、ＯＬＢパッ
ド１７は、基板母材１１の上にＩＣ１５のリード１４を
ボンディングすることに重点が置かれるため、ソフトタ
イプ金めっき液を使用して、結晶粒子が柔かいソフトタ
イプの金めっきパターン（ソフト金めっきパターン）１
２を形成し、Ｉ／Ｏパッド１８は、上位装置に装着する
ときにコネクタ端子１６が接触するため、結晶粒子が硬
いコバルト系金属を含むハードタイプの金めっきパター
ン（ハード金めっきパターン）１３を形成する。しかし
ハードタイプ金めっき液で形成するハード金めっきパタ
ーン１３は、内部応力が高いために基板母材１１との接
着力が弱い。このため、基板母材１１とハード金めっき
パターン１３との間にソフト金めっきパターン１２を形
成して接着力の強化を図っている。That is, as shown in FIG. 2, since the OLB pad 17 is focused on bonding the leads 14 of the IC 15 on the substrate base material 11, a soft type gold plating solution is used to crystallize it. Soft type gold plating pattern with soft particles (soft gold plating pattern) 1
2, the I / O pad 18 contacts the connector terminal 16 when it is mounted on the host device, so that the hard-type gold plating pattern (hard gold plating pattern) 13 containing a cobalt-based metal with hard crystal particles is formed. Form. However, the hard gold plating pattern 13 formed by the hard type gold plating solution has a high internal stress, and thus has a weak adhesive force with the substrate base material 11. Therefore, the soft gold plating pattern 12 is formed between the substrate base material 11 and the hard gold plating pattern 13 to enhance the adhesive force.

【０００５】[0005]

【発明が解決しようとする課題】上述したように、従来
の印刷回路基板は、ＯＬＢパッドとＩ／Ｏパッドとに対
してそれぞれ異なるめっき液を使用しなければならない
ため、２回のレジストパターニングを行わなければなら
ず、作業工程が複雑であるという欠点を有している。As described above, in the conventional printed circuit board, it is necessary to use different plating solutions for the OLB pad and the I / O pad, so that the resist patterning is performed twice. It has the disadvantage that it has to be performed and the working process is complicated.

【０００６】[0006]

【課題を解決するための手段】本発明の印刷回路基板
は、ＴＡＢチップタイプのＩＣのリードをボンディング
するためのＯＬＢパッドと、上位装置に装着するための
コネクタ端子用のＩ／Ｏパッドとを有する印刷回路基板
において、前記ＯＬＢパッドおよび前記Ｉ／Ｏパッドの
両者に対して、最下層に結晶粒子が柔かいソフト金めっ
きパターンを設け、中間層にコバルト系金属を含むハー
ド金めっきパターンを設け、最上層に結晶粒子が柔かい
ソフト金めっきパターンを設けたものである。A printed circuit board of the present invention comprises an OLB pad for bonding a lead of a TAB chip type IC and an I / O pad for a connector terminal to be mounted on a host device. In the printed circuit board having, for both the OLB pad and the I / O pad, a soft gold plating pattern having soft crystal grains is provided in the lowermost layer, and a hard gold plating pattern containing a cobalt-based metal is provided in the intermediate layer, The uppermost layer is provided with a soft gold plating pattern having soft crystal grains.

【０００７】[0007]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.

【０００８】図１は本発明の一実施例を示す断面図であ
る。FIG. 1 is a sectional view showing an embodiment of the present invention.

【０００９】図１の実施例は、基板母材１の上に、ＩＣ
５のリード４をボンディングするためのＯＬＢパッド７
と、上位装置に装着するときにコネクタ端子６が接触す
るためのＩ／Ｏパッド８とを形成しているが、ＯＬＢパ
ッド７およびＩ／Ｏパッド８は共に、最下層にソフトタ
イプ金めっき液を使用して結晶粒子が柔かいソフト金め
っきパターン２を形成し、その上の中間層に、ハードタ
イプ金めっき液を使用してコバルト系金属を含むハード
金めっきパターン３を形成し、更にその上の最上層に結
晶粒子が柔かいソフト金めっきパターン２を形成してい
る。In the embodiment shown in FIG. 1, an IC is formed on a substrate base material 1.
OLB pad 7 for bonding lead 4 of 5
And an I / O pad 8 for contacting the connector terminal 6 when it is mounted on a host device. Both the OLB pad 7 and the I / O pad 8 are formed of a soft type gold plating solution on the bottom layer. Is used to form a soft gold plating pattern 2 having soft crystal particles, and a hard gold plating pattern 3 containing a cobalt-based metal is formed on the intermediate layer thereon using a hard type gold plating solution. A soft gold plating pattern 2 having soft crystal grains is formed on the uppermost layer of the.

【００１０】このように構成することにより、ＯＬＢパ
ッド７およびＩ／Ｏパッド８は共に、それらに要求され
る機能を満足し、しかも両者を同時に形成することが可
能となる。With this structure, both the OLB pad 7 and the I / O pad 8 satisfy the functions required for them, and both can be formed at the same time.

【００１１】[0011]

【発明の効果】以上説明したように、本発明の印刷回路
基板は、ＯＬＢパッドおよびＩ／Ｏパッドの両者に対し
て、共に最下層に結晶粒子が柔かいソフト金めっきパタ
ーンを形成し、中間層にコバルト系金属を含むハード金
めっきパターンを形成し、最上層にソフト金めっきパタ
ーンを形成することにより、それぞれに要求される機能
を満足し、しかも１回のレジストパターニングで両者を
同時に形成することが可能となるという効果があり、従
って作業工程を簡素化できるという効果がある。As described above, in the printed circuit board of the present invention, the soft gold plating pattern having soft crystal grains is formed in the lowermost layer of both the OLB pad and the I / O pad, and the intermediate layer is formed. By forming a hard gold plating pattern containing a cobalt-based metal on the top and forming a soft gold plating pattern on the uppermost layer, the functions required for each are satisfied, and both can be formed simultaneously by one resist patterning. Therefore, the working process can be simplified.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図２】従来の印刷回路基板の一例を示す断面図であ
る。FIG. 2 is a cross-sectional view showing an example of a conventional printed circuit board.

【符号の説明】[Explanation of symbols]

１ 基板母材 ２ ソフト金めっきパターン ３ ハード金めっきパターン ４ リード ５ ＩＣ ６ コネクタ端子 ７ ＯＬＢパッド ８ Ｉ／Ｏパッド １１ 基板母材 １２ ソフト金めっきパターン １３ ハード金めっきパターン １４ リード １５ ＩＣ １６ コネクタ端子 １７ ＯＬＢパッド １８ Ｉ／Ｏパッド 1 substrate base material 2 soft gold plating pattern 3 hard gold plating pattern 4 leads 5 IC 6 connector terminal 7 OLB pad 8 I / O pad 11 board base material 12 soft gold plating pattern 13 hard gold plating pattern 14 lead 15 IC 16 connector terminal 17 OLB pad 18 I / O pad

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 ＴＡＢチップタイプのＩＣのリードをボ
ンディングするためのＯＬＢパッドと、上位装置に装着
するためのコネクタ端子用のＩ／Ｏパッドとを有する印
刷回路基板において、前記ＯＬＢパッドおよび前記Ｉ／
Ｏパッドの両者に対して、最下層に結晶粒子が柔かいソ
フト金めっきパターンを設け、中間層にコバルト系金属
を含むハード金めっきパターンを設け、最上層に結晶粒
子が柔かいソフト金めっきパターンを設けたことを特徴
とする印刷回路基板。1. A printed circuit board having an OLB pad for bonding a lead of a TAB chip type IC and an I / O pad for a connector terminal to be mounted on a host device, wherein the OLB pad and the I / O pad are provided. /
For both of the O pads, a soft gold plating pattern having soft crystal particles is provided in the lowermost layer, a hard gold plating pattern containing a cobalt-based metal is provided in the intermediate layer, and a soft gold plating pattern having soft crystalline particles is provided in the uppermost layer. A printed circuit board characterized by the above. 【請求項２】 ＴＡＢチップタイプのＩＣのリードをボ
ンディングするためのＯＬＢパッドと、上位装置に装着
するためのコネクタ端子用のＩ／Ｏパッドとを有する印
刷回路基板において、前記ＯＬＢパッドおよび前記Ｉ／
Ｏパッドの両者に対して、２種類の金めっき液を使用し
て、最下層に結晶粒子が柔かいソフト金めっきパターン
を設け、中間層にコバルト系金属を含むハード金めっき
パターンを設け、最上層に結晶粒子が柔かいソフト金め
っきパターンを設けたことを特徴とする印刷回路基板。2. A printed circuit board having an OLB pad for bonding a lead of a TAB chip type IC and an I / O pad for a connector terminal to be mounted on a host device, wherein the OLB pad and the I / O pad are provided. /
For both of the O pads, two kinds of gold plating solutions are used, a soft gold plating pattern with soft crystal grains is provided in the lowermost layer, and a hard gold plating pattern containing a cobalt-based metal is provided in the intermediate layer. A printed circuit board, wherein a soft gold plating pattern having soft crystal particles is provided on the printed circuit board.
JP3221993A 1991-09-03 1991-09-03 Printed circuit board Pending JPH0563331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3221993A JPH0563331A (en) 1991-09-03 1991-09-03 Printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3221993A JPH0563331A (en) 1991-09-03 1991-09-03 Printed circuit board

Publications (1)

Publication Number Publication Date
JPH0563331A true JPH0563331A (en) 1993-03-12

Family

ID=16775407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3221993A Pending JPH0563331A (en) 1991-09-03 1991-09-03 Printed circuit board

Country Status (1)

Country Link
JP (1) JPH0563331A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0884935A3 (en) * 1997-06-11 2000-03-08 International Business Machines Corporation Universal surface finish for DCA SMT, and pad on pad interconnections
US7514156B1 (en) * 2004-09-14 2009-04-07 Precision Manufacturing Group, Llc Layered article
KR101009204B1 (en) * 2008-06-16 2011-01-19 삼성전기주식회사 Printed circuit board and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0884935A3 (en) * 1997-06-11 2000-03-08 International Business Machines Corporation Universal surface finish for DCA SMT, and pad on pad interconnections
US7514156B1 (en) * 2004-09-14 2009-04-07 Precision Manufacturing Group, Llc Layered article
KR101009204B1 (en) * 2008-06-16 2011-01-19 삼성전기주식회사 Printed circuit board and method of manufacturing the same

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