JPH11275866A - Control method of three-phase rectifier power factor improving circuit - Google Patents

Control method of three-phase rectifier power factor improving circuit

Info

Publication number
JPH11275866A
JPH11275866A JP10096668A JP9666898A JPH11275866A JP H11275866 A JPH11275866 A JP H11275866A JP 10096668 A JP10096668 A JP 10096668A JP 9666898 A JP9666898 A JP 9666898A JP H11275866 A JPH11275866 A JP H11275866A
Authority
JP
Japan
Prior art keywords
control
dead time
phase
power factor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10096668A
Other languages
Japanese (ja)
Inventor
Tetsuya Oshikata
哲也 押方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP10096668A priority Critical patent/JPH11275866A/en
Publication of JPH11275866A publication Critical patent/JPH11275866A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00Climate change mitigation technologies for sector-wide applications
    • Y02P80/10Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

PROBLEM TO BE SOLVED: To attain stable operation of a three-phase rectifier, by changing the dead time of control pulses of control elements on positive and negative potential sides of respective arms, based on input phase voltage. SOLUTION: A dead time duration computing circuit detects input phase voltage, computes desired dead time duration so as to meet the voltage value, generates a control pulse which has generated dead time based on computed results to supply to a drive circuit. Two control signals as a pair for controlling meet one control pulse, the other control pulse is inverted by an inverting circuit to be generated, and these control pulses are applied to a control element. The dead time of the control pulses of control elements on positive and negative potential sides of the respective arms can be changed with input phase voltage. It is thus possible to attain a three-phase rectifier power factor improving circuit which can prevent failures which are caused by simultaneous on-operations of the respective arms, and has few harmonic components.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する分野】本発明は三相整流器力率改善回路
の制御方式に関するものである。
The present invention relates to a control method for a three-phase rectifier power factor correction circuit.

【0002】[0002]

【従来の技術】図1は、従来から用いられている三相整
流器の力率改善回路である。又、図2は、三相交流入力
電圧の波形である。U相電圧Vuが45°の時の各相電
圧は、図の45°の点線の示す通りである。さらに、図
3は、Vuが45°付近の時の各相の制御パルス波形例
である。図3では説明しないが、各アームの正電位側の
制御素子と負電位側の制御素子の制御パルス間には、短
絡を防止する為の非導通期間、いわゆる、デッドタイム
が存在する。図4は、制御素子Q3とQ6に関してデッ
ドタイムを表記した制御パルス波形 (2) 例である。デッドタイムの幅は使用する制御素子の種
類、スイッチング周期等によって違うが、一度設定され
れば、入力電圧等によらず一定である。
2. Description of the Related Art FIG. 1 shows a power factor improving circuit of a conventionally used three-phase rectifier. FIG. 2 shows a waveform of a three-phase AC input voltage. Each phase voltage when the U-phase voltage Vu is 45 ° is as shown by a dotted line of 45 ° in the figure. FIG. 3 is an example of a control pulse waveform of each phase when Vu is around 45 °. Although not described in FIG. 3, there is a non-conduction period for preventing a short circuit, a so-called dead time, between the control pulses of the control element on the positive potential side and the control element on the negative potential side of each arm. FIG. 4 is an example of a control pulse waveform (2) showing the dead time for the control elements Q3 and Q6. The width of the dead time varies depending on the type of the control element used, the switching cycle, and the like, but once set, it is constant regardless of the input voltage or the like.

【0003】デッドタイムは各アームの正電位側の制御
素子と負電位側の制御素子とが同時オンするのを避ける
ために設けられている。従って、制御素子のオン時間が
温度によって変化することや、誤動作に強い設計が望ま
しいことを考えると、デッドタイムの幅は広いほうがよ
い。実際の三相整流器力率改善回路において、デッドタ
イムの幅を相当に広げてもほぼ正常な動作をする。これ
について以下に簡単に説明をする。
The dead time is provided to prevent the control element on the positive potential side and the control element on the negative potential side of each arm from being simultaneously turned on. Therefore, considering that the ON time of the control element changes with temperature and that a design that is strong against malfunction is desirable, a wider dead time is better. In an actual three-phase rectifier power factor correction circuit, almost normal operation is performed even if the width of the dead time is considerably widened. This will be briefly described below.

【0004】図5は、図3のゲート信号のスイッチング
モード毎の電流の流れを示す等価回路である。例えば、
図3のモードでは、Q1、Q2、Q3の制御素子がオ
ンであるので、図1の整流回路は、図5のの様な電流
の流れを示す等価回路となる。ここで、Q3・D3とQ
6・D6に注目すると、これらの素子に流れる電流は、
図5に示すように、入力側から三相整流器力率改善回路
へ流れ込む方向である。図5のモード・はQ3がオ
ンしている期間であるが、電流の流れる方向が、D3の
順方向であるため、電流はD3を通って流れる。従っ
て、Q3はオフしたままでも動作上問題がないだけでな
く、デッドタイムの幅を最大限に広げた状態と考えら
れ、正電位側の制御素子と負電位側の制御素子の同時オ
ンを避けるためには、最良の状態と考えられる。ところ
が、電流のゼロクロス付近、すなわち、図3において、
60°付近では、前記のQ3をオフした状態のままで
は、問題がある。これについて、以下に簡単に説明す
る。
FIG. 5 is an equivalent circuit showing a current flow in each switching mode of the gate signal of FIG. For example,
In the mode of FIG. 3, since the control elements of Q1, Q2, and Q3 are on, the rectifier circuit of FIG. 1 is an equivalent circuit showing a current flow as shown in FIG. Here, Q3 · D3 and Q3
Focusing on 6.D6, the current flowing through these elements is
As shown in FIG. 5, the flow direction is from the input side to the three-phase rectifier power factor correction circuit. The mode in FIG. 5 is a period in which Q3 is on, but the current flows through D3 because the current flows in the forward direction of D3. Therefore, it is considered that there is no operational problem even if Q3 remains off, and that the dead time width is maximized, and simultaneous control of the positive potential side control element and the negative potential side control element is avoided. In order to be considered the best. However, near the zero cross of the current, that is, in FIG.
In the vicinity of 60 °, there is a problem if Q3 is kept off. This will be briefly described below.

【0005】図5において、モード〜の間、電流の
流れる方向に変化はないが、モード〜の状態に変化
により、電流の増減を繰り返している。この電流の様子
は、 (3) 入出力電圧や、負荷の状態等によって異なるが、例え
ば、60°付近では図6のようである。図6の〜は
それぞれ図5の〜に対応している。ここで、負側に
波形がある部分は、電流の流れる方向が、三相整流器力
率改善回路から入力に向かって流れる場合である。従っ
て、図6において、モードの負側に波形がある部分に
ついては、電流の方向が、D3にとって逆方向となるた
め、Q3がオンしていなければ流れられない。もし、モ
ードで、Q3がオフしたままで、負側に電流を流さな
かった場合、あるいは、デッドタイムの幅が広い場合、
W相の電流波形にひずみが生じ、高調波電流成分が増加
してしまう。この高調波成分は、比較的高次の成分であ
り、高調波電流規格値を満足することが非常に困難とな
る。この現象は、U相、V相についても全く同様であ
る。
In FIG. 5, there is no change in the direction of current flow during the mode .about., But the increase and decrease of the current are repeated by the change in the state of the mode. The state of this current varies depending on (3) the input / output voltage, the state of the load, etc., for example, as shown in FIG. 6 near 60 °. 6 in FIG. 6 correspond to in FIG. Here, the portion having a waveform on the negative side is the case where the current flows from the three-phase rectifier power factor correction circuit toward the input. Therefore, in FIG. 6, in the portion where the waveform is on the negative side of the mode, the current does not flow unless Q3 is on because the direction of the current is opposite to that of D3. If Q3 remains off and no current flows to the negative side in the mode, or if the dead time is wide,
Distortion occurs in the W-phase current waveform, and the harmonic current component increases. This harmonic component is a relatively high-order component, and it is very difficult to satisfy the harmonic current standard value. This phenomenon is exactly the same for the U phase and the V phase.

【0006】[0006]

【発明が解決しようとする課題】以上の説明で明らかな
ように、デッドタイムの幅は、入力相電圧が高いときは
できるだけ広く、また、入力相電圧が低いときはできる
だけ狭くとりたいわけである。ところが、従来の、デッ
ドタイム固定の三相整流器力率改善回路の制御方式や正
負どちらかの電位側の制御素子をオフしたままとする従
来の三相整流器力率改善回路の制御方式では不可能であ
った。そこで本発明は、上記問題点を解決するためにな
されたものであり、その目的は入力電圧の変動にかかわ
らず、適正なデッドタイムをとる事によって、三相整流
器を安定して動作させるための、三相整流器力率改善回
路の制御方式を実現することにある。
As is apparent from the above description, it is desired that the width of the dead time be as wide as possible when the input phase voltage is high and as narrow as possible when the input phase voltage is low. . However, this is not possible with the conventional control method of the dead-time fixed three-phase rectifier power factor correction circuit or the conventional three-phase rectifier power factor correction circuit control method in which the control element on either the positive or negative potential side remains off. Met. Therefore, the present invention has been made to solve the above problems, and has as its object to stably operate a three-phase rectifier by taking an appropriate dead time irrespective of input voltage fluctuations. Another object of the present invention is to realize a control method of a three-phase rectifier power factor correction circuit.

【0007】[0007]

【問題を解決するための本発明の手段】本発明は、三相
交流入力の各相のインダクタンスを接続して整流器入力
とし、三相ブリッジを構成する各制御素子の各々にダイ
オードを逆並列に接続した三相整流器力率改善回路にお
いて、入力相電圧に対応して、各アームの正電位側の制
御素子と負電位側の制御素子の制御のパルスのデッドタ
イムを変化させることを特徴とする三相整流器力率改善
回路の制御回路である。これを実現するための一つの手
段は、各々の相電圧を検出し、その相電圧に対 (4) 応したアームのデッドタイムを与えることである。
According to the present invention, a rectifier input is formed by connecting the inductance of each phase of a three-phase AC input, and a diode is connected in anti-parallel to each control element constituting a three-phase bridge. In the connected three-phase rectifier power factor correction circuit, the dead time of the control pulse of the control element on the positive potential side and the control element on the negative potential side of each arm is changed according to the input phase voltage. It is a control circuit of a three-phase rectifier power factor improvement circuit. One means for achieving this is to detect each phase voltage and provide a dead time of the arm corresponding to the phase voltage.

【0008】[0008]

【発明の実施の形態】図7は本発明の制御方式の一実施
例である。図7は、図1における制御素子Q1、Q4の
1アーム分の制御ブロックである。従って、三相回路全
体としては、電圧制御系と鋸歯状波発生部を共通部分と
して、図7と同じブロックが3個で構成されることにな
る。図7において、デッドタイム幅計算回路は、入力相
電圧の絶対値が大きいときは、デッドタイム幅が広く、
入力相電圧の絶対値が小さいときはデッドタイム幅が狭
くなるように計算される。
FIG. 7 shows an embodiment of a control system according to the present invention. FIG. 7 is a control block for one arm of the control elements Q1 and Q4 in FIG. Therefore, the three-phase circuit as a whole has the same block as that of FIG. 7 with three blocks, with the voltage control system and the sawtooth wave generator as common parts. In FIG. 7, when the absolute value of the input phase voltage is large, the dead time width is large, and the dead time width is large.
When the absolute value of the input phase voltage is small, the calculation is performed so that the dead time width becomes narrow.

【0009】図7において、動作を説明すると、入力相
電圧を検出してその電圧値に対応して、デッドタイム幅
計算回路が所望のデッドタイム幅を計算する。そして、
計算結果に基づいて、デッドタイムを生成した制御パル
スを作り、ドライブ回路に供給する。制御の対となる2
つの制御素子の制御信号は、1つの制御パルスに対応し
て、もう1つの制御パルスは反転回路により反転して生
成する。そして、これらの制御パルスを制御素子Q1と
Q4に印加する。他の対となる制御素子(Q2、Q5)
及び(Q3、Q6)についても同様である。各アームの
正電位側の制御素子と負電位側の制御素子の制御パルス
のデッドタイムは、入力相電圧値に対応して可変するこ
とが出来る。具体的には、入力相電圧の絶対値が高い時
は、デッドタイムの幅が広く、入力相電圧の絶対値が小
さい時は、デッドタイム幅が狭くなるように可変させ
る。
Referring to FIG. 7, the operation will be described. An input phase voltage is detected, and a dead time width calculation circuit calculates a desired dead time width according to the detected voltage value. And
Based on the calculation result, a control pulse that generates a dead time is generated and supplied to the drive circuit. Control pair 2
The control signal of one control element is generated corresponding to one control pulse, and the other control pulse is inverted by an inversion circuit. Then, these control pulses are applied to the control elements Q1 and Q4. Other paired control elements (Q2, Q5)
And (Q3, Q6). The dead time of the control pulses of the control element on the positive potential side and the control element on the negative potential side of each arm can be varied according to the input phase voltage value. Specifically, when the absolute value of the input phase voltage is high, the dead time width is wide, and when the absolute value of the input phase voltage is small, the dead time width is narrowed.

【0010】もちろん、入力相電圧が高いときには、デ
ッドタイム幅が広がった結果、片側の制御素子がオフす
る状態がある場合も考えられる。また、入力電圧の絶対
値がある一定の値以下になったとき設定されたデッドタ
イム幅を生成し、それ以外の期間では片側の制御素子を
オフさせておく場合も、もちろん本発明に含まれる。 (5)
Of course, when the input phase voltage is high, there may be a case where one of the control elements is turned off as a result of an increase in the dead time width. The present invention also includes a case where the set dead time width is generated when the absolute value of the input voltage becomes equal to or less than a certain value, and the control element on one side is turned off in other periods. . (5)

【0011】[0011]

【発明の効果】以上の説明から明らかなように、本発明
により、各アームの同時オンによる障害を防止しつつ、
高調波成分の少ない三相整流器力率改善回路を提供する
ことができる。
As is apparent from the above description, according to the present invention, it is possible to prevent a failure due to simultaneous turning on of each arm,
It is possible to provide a three-phase rectifier power factor improvement circuit with less harmonic components.

【図面の簡単な説明】[Brief description of the drawings]

【図1】三相整流器の力率改善回路。FIG. 1 is a power factor correction circuit of a three-phase rectifier.

【図2】三相交流入力相電圧の波形。FIG. 2 is a waveform of a three-phase AC input phase voltage.

【図3】U相電圧Vuが45°付近の時の各相ゲートド
ライブ波形。
FIG. 3 is a gate drive waveform of each phase when the U-phase voltage Vu is around 45 °.

【図4】デッドタイムを表記した制御パルス波形例。FIG. 4 is a control pulse waveform example showing a dead time.

【図5】各スイッチングモード時の電流の流れを示す等
価回路。
FIG. 5 is an equivalent circuit showing a current flow in each switching mode.

【図6】入力電流波形例。FIG. 6 is an example of an input current waveform.

【図7】本発明の一実施例。FIG. 7 shows an embodiment of the present invention.

【符号の簡単な説明】[Brief description of reference numerals]

Q1〜Q6 制御素子 D1〜D6 ダイオード CO 出力平滑コンデンサ C1〜C3 入力平滑コンデンサ L1〜L3 入力インダクタ Vu U相の相電圧 Vv V相の相電圧 (6) Vw W相の相電圧 Ec 基準三角波 GQ1〜GQ6 制御素子のQ1〜Q6の制御パルス Eu GQ1とGQ4の制御用比較電圧 Ev GQ2とGQ5の制御用比較電圧 Ew GQ3とGQ6の制御用比較電圧 DT デッドタイム Q1 to Q6 Control elements D1 to D6 Diode CO Output smoothing capacitor C1 to C3 Input smoothing capacitor L1 to L3 Input inductor Vu U-phase phase voltage Vv V-phase phase voltage (6) Vw W-phase phase voltage Ec Reference triangular wave GQ1 to GQ6 Control pulse for control elements Q1 to Q6 Eu Comparison voltage for controlling GQ1 and GQ4 Ev Comparison voltage for controlling GQ2 and GQ5 Ew Comparison voltage for controlling GQ3 and GQ6 DT Dead time

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 三相交流入力の各相にインダクタンスを
接続し、三相ブリッジを構成する各制御素子の各々にダ
イオードを逆並列に接続した三相整流器力率改善回路に
於いて、 各アームの正電位側の制御素子と負電位側の制御素子を
共に非導通にさせる、制御パルスのデッドタイムが商用
入力電圧1周期の間一定ではない事を特徴とする三相整
流器力率改善回路の制御方式。
In a three-phase rectifier power factor improving circuit, an inductance is connected to each phase of a three-phase AC input, and a diode is connected in anti-parallel to each of control elements constituting a three-phase bridge. A dead time of a control pulse is not constant during one cycle of a commercial input voltage, wherein the control element on the positive potential side and the control element on the negative potential side are both non-conductive. control method.
【請求項2】 請求項1記載の制御方式に於いて、前記
各アームの正電位側の制御素子と負電位側の制御素子の
デッドタイムが、各々のアームに接続されている相電圧
に応じて変化することを特徴とする三相整流器力率改善
回路の制御方式。
2. The control method according to claim 1, wherein the dead time of the control element on the positive potential side and the control element on the negative potential side of each arm are determined according to the phase voltage connected to each arm. Control method for a three-phase rectifier power factor correction circuit, characterized in that
JP10096668A 1998-03-25 1998-03-25 Control method of three-phase rectifier power factor improving circuit Pending JPH11275866A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10096668A JPH11275866A (en) 1998-03-25 1998-03-25 Control method of three-phase rectifier power factor improving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10096668A JPH11275866A (en) 1998-03-25 1998-03-25 Control method of three-phase rectifier power factor improving circuit

Publications (1)

Publication Number Publication Date
JPH11275866A true JPH11275866A (en) 1999-10-08

Family

ID=14171196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10096668A Pending JPH11275866A (en) 1998-03-25 1998-03-25 Control method of three-phase rectifier power factor improving circuit

Country Status (1)

Country Link
JP (1) JPH11275866A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100423437C (en) * 2004-08-05 2008-10-01 尼克森微电子股份有限公司 Bridge synchronization rectification circuit with dead time adjustment
WO2014034530A1 (en) * 2012-08-27 2014-03-06 富士電機株式会社 Switching power supply apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100423437C (en) * 2004-08-05 2008-10-01 尼克森微电子股份有限公司 Bridge synchronization rectification circuit with dead time adjustment
WO2014034530A1 (en) * 2012-08-27 2014-03-06 富士電機株式会社 Switching power supply apparatus
US9647566B2 (en) 2012-08-27 2017-05-09 Fuji Electric Co., Ltd. Switching power supply apparatus

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