JPH04295279A - Controller of neutral point clamp type power converter - Google Patents

Abstract

PURPOSE:To prevent the DC shortcircuit and remove wasteful time, which has been regarded as necessary conventionally, by limiting the gate signal of four elements constituting a neutral point clamp type power converter according to the direction of the output current. CONSTITUTION:When the output current IU>=0, the lower elements S3 and S4 are put in off condition. Moreover, when the output current IU<=0, the upper elements S1 and S2 are put in off condition. Either pair of the upper two elements S1 and S2 and the lower two elements S3 and S4 are in off condition, so the converter never short-circuits. Moreover, when the output current IU>=0, the element S3 is in always on, so there is no necessity for providing the wasteful time in the gate signal of the element S1. Moreover, when the output current IU<0, the element S1 is always off, so there is no necessity for providing wasteful time in the gate signal of the element S3 likewise. It is the same between the elements S2 and S4.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

[Industrial Application Field] The present invention is applicable to pulse width modulation control (PWM control) converters that convert AC power to DC power, PWM control inverters that convert DC power to AC power, etc. The present invention relates to a control device for a neutral point clamp type power converter that generates three levels of output voltage.

0002

2. Description of the Related Art FIG. 7 shows a main circuit and control circuit configuration diagram of a conventional neutral point clamp type inverter. The figure shows one phase (
In the case of a 3-phase output inverter, V, W,
The phases are similarly constructed.

[0003] In the figure, Vd1 and Vd2 are DC power supplies, S1
-S4 are self-extinguishing elements, D1-D4 are free-wheeling diodes, D5 and D6 are clamp diodes, LOAD is a load, and CTU is a current detector. Further, as a control circuit, comparators CU, C1, C2,
Current control compensation circuit GU(s), triangular wave generator TRG
, Schmitt circuits SH1 and SH2 are provided.

The output voltage VU of this inverter is determined by turning on and off the four elements S1 to S4.
It changes as follows. However, the overall DC voltage is Vd
and Vd1=Vd2=Vd/2. That is, S1
When and S2 are on, VU = +Vd /2S2
When S3 and S3 are on, VU =0. When S3 and S4 are on, VU = -Vd /2. At this time, the elements must be turned on two at a time. If all three of them turn on at the same time, they will short-circuit the DC power supply and destroy the elements due to overcurrent.

For example, when an on signal is applied to the elements S1 to S3, the DC voltage Vd1 is applied to the elements S1 to S3.
A short circuit occurs in diode D6, and an excessive short circuit current flows through the element, destroying the element.

In order to prevent such a DC short circuit, elements S1 and S3 are operated in reverse, and element S2S4 is operated in reverse. That is, when element S1 is on, element S3
is turned off, and when element S3 is on, element S1 is turned off. Similarly, when element S2 is on, element S4 is turned off, and when element S4 is on, element S2 is turned off. FIG. 8 is a time chart for explaining a conventional pulse width modulation control method for a neutral point clamp type inverter.

In the figure, X and Y are carrier wave signals of PWM control, X is a triangular wave varying between +EMAX and 0, and Y is -
It is a triangular wave that changes between EMAX and 0. Also, e
i is a PWM control input signal. Input signal ei and triangular waves X and Y are compared to generate gate signals g1 and g2 for elements S1 to S4. That is, when ei > X, g1 = 1, S1 is turned on, S3
turn off. When ei ≦X, g1 = 0, S1 is turned off, S3
Turn on. When ei ≧Y, g2 = 0, S4 is turned off, S2
Turn on. When ei <Y, g2 = 1, S4 is turned on, S2
turn off.

As a result, the output voltage VU becomes as shown in the bottom row of the figure, and its average value (indicated by a broken line) becomes a value proportional to the input signal ei. In this way, in the neutral point clamp type inverter, voltages of three levels (+Vd/2, 0, -Vd/2) are obtained as the output voltage VU, resulting in a voltage waveform with few harmonic components. In the case of a motor load, there is an advantage that current pulsation is small and torque ripple is also reduced.

[0009]

However, the conventional neutral point clamp type inverter control device has the following problems.

That is, the elements S1 . . .
There is no problem if S4 is an ideal switching element, but in reality, even if an off signal is applied to the element, it does not turn off immediately, but turns off after a certain period of time. The same applies when switching from off to on, but generally the turn-off time is longer than the turn-on time.

Therefore, for example, if an off signal is given to element S1 and an on signal is given to element S3 at the same time, element S3 is turned on before element S1 is turned off, and 3
A period occurs in which the two elements S1 to S3 are turned on, shorting the DC power supply and causing an excessive current to flow and destroy the elements.

FIGS. 9 and 10 are time charts for explaining a conventional PWM control method for solving this problem. In the figure, g1 and g2 are signals obtained by the PWM control method shown in FIG.

Gate signal g of element S1 from signal g1
s1 is generated, and a gate signal gs3 of the element S3 is generated from the inverted signal of the signal g1. Gate signal gs1 is signal g1
After changing from "0" to "1", the state remains "0" for ΔtD (dead time), and then gs1=g1. Furthermore, the gate signal gs3 is an inverted signal of the signal g1.
After changing from "0" to "1", the "0" state is maintained for ΔtD (dead time), and then the signal becomes an inverted signal of gs3=g1. The dead time ΔtD is determined in consideration of the turn-off time of the device and the like. In this way, elements S1 and S
By shortening the ON periods of gate signals gs1 and gs3 of 3 by the dead time ΔtD, the elements S1 and S
3 are prevented from being turned on at the same time. Element S2
The same applies to the gate signals gs2 and gs4 of and S4. This conventional method of preventing DC short circuits using dead time has the following drawbacks. That is, the dead time ΔtD
During the period, the inverter output voltage V depends on the direction of the output current.
This means that the value of U will change.

FIG. 9 shows the output voltage of the inverter when elements S1 and S3 are alternately turned on and off while maintaining dead time ΔtD when element S2 is on (S4 is off).

VU(+) is the output voltage when the output current IU is flowing in the direction of the arrow (positive direction) in FIG.
U(-) indicates the output voltage when the output current IU is flowing in the opposite direction (negative direction) to the arrow in FIG. Dead time Δt
During D , both elements S1 and S3 are in the off state, and when IU is positive, current flows through element S2;
VU (+) = 0, and when IU is negative, current flows through diodes D1 and D2 and VU (-) = Vd.
/2. That is, if the output voltage when the elements S1 and S3 are turned on and off according to the first gate signal g1 is VU, then when IU > 0, VU (+) = VU - ΔVD
When IU<0, VU(-)=VU+ΔVD. However, ΔVD is a bias voltage based on the dead time ΔtD.

Further, in FIG. 10, element S3 is on (S1
is off), the dead time ΔtD of elements S2 and S4 is
This shows the inverter output voltage when the inverter is turned on and off alternately while maintaining the voltage. VU (+) is the output voltage when the output current IU is flowing in the direction of the arrow in Figure 7 (positive direction), and VU (-) is the output voltage when the output current IU is flowing in the opposite direction (negative direction) to the arrow in Figure 7. Indicates the output voltage when flowing. During the dead time ΔtD, both elements S2 and S4 are in the off state, and when IU is positive, the diodes D3 and D4
Current flows through element S3, resulting in VU(+)=-Vd/2, and when IU is negative, current flows through element S3, resulting in VU(-)=0. That is, if the output voltage when the elements S2 and S4 are turned on and off according to the first gate signal g2 is VU, then as explained in FIG. 10, when IU > 0, VU(+) =VU-ΔVD
When IU<0, VU(-)=VU+ΔVD. Bias voltage ΔV based on this dead time ΔtD
D is determined by the direction of the output current IU and PW
When the carrier wave (triangular wave) frequency of M control is fc,
It is expressed as follows. ΔVD = (Vd /2)・fc・ΔtD For example, f
When c = 1 KHZ and ΔtD = 100 μsec, ΔVD = 0.1·(Vd /2). This bias voltage ΔVD is the output current IU
When controlling the current waveform, the problem remains that it acts as a disturbance source and distorts the current waveform. Conventionally, in order to cancel out this disturbance source, a compensation voltage ±ΔeD proportional to ΔVD is applied to the PWM control input signal ei according to the direction of the output current. However, it is difficult to completely cancel out the distortion, and the reality is that waveform distortion remains in the output current. Furthermore, the control range of PWM control becomes narrower by the addition of this compensation voltage ±ΔeD, resulting in a reduction in the utilization rate of the neutral point clamp type inverter.

As described above, in the PWM control of the conventional neutral point clamp type inverter, in order to prevent DC short circuits, dead time is provided when switching between elements S1 and S3 and between elements S2 and S4. This dead time distorts the output current and reduces the utilization rate of the inverter.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a control device for a neutral point clamp type power converter that can eliminate dead time and prevent DC short circuits. [Structure of the invention]

[0019]

[Means for Solving the Problems] In order to achieve the above object, the present invention comprises four self-extinguishing elements S1,
S2, S3, S4, and free-wheeling diodes D1, D2, connected in antiparallel to each of these elements.
D3, D4 and clamp diodes D5, D6
In a neutral point clamp type power converter consisting of, as carrier waves for pulse width modulation control, one is a triangular wave X that changes between zero and the positive side, and the other is a triangular wave Y that changes between zero and the negative side. Triangular wave generating means to generate a triangular wave, and an output current of the power converter or a signal IU corresponding to the output current.
means for determining the direction of the PWM control input signal ei and the triangular wave X,
When ei > X, the upper two self-extinguishing elements S1 and S2 are turned on.
(turn off S1) When ei <Y, the two upper self-extinguishing elements S1
. When the arc-extinguishing elements S3 and S4 are turned off when Y≦ei≦X, the lower self-extinguishing element S3
(turn off S4) When ei <Y, the lower two self-extinguishing elements S3
, S4.

[0020]

[Operation] The present invention converts the gate signals of the four elements S1 to S4 constituting the neutral point clamp type power converter into an output current I
By limiting the direction of U, DC short circuits are prevented and the wasted time that was conventionally required is eliminated.

That is, when IU≧0, the output current I
Since U does not flow through elements S3 and S4, elements S3 and S4 are kept in the off state. vice versa,
When IU < 0, the output current IU does not flow through the elements S1 and S2, so the output current IU does not flow through the elements S1 and S2.
2 is turned off. In this way, either the upper two elements or the lower two elements are in the off state,
There will be no direct current short circuit in the converter.

In the conventional control device, elements S1 and S3
A dead time was provided to prevent both from turning on at the same time, but
According to the present invention, when IU≧0, the element S3 is always in the on state, and there is no need to provide a dead time for the gate signal of the element S1. Further, when IU <0, the element S1 is always off, and there is no need to provide a dead time to the gate signal of the element S3. Similarly, there is no need to provide dead time between elements S2 and S4.

That is, according to the present invention, the signal obtained by comparing the PWM control input signal ei with the triangular wave X or Y can be directly used as the gate signal of the elements S1 to S4. , the output voltage is the input signal ei
A value proportional to is obtained, making it possible to control the output current without distortion. In addition, there is no reduction in the utilization rate of the converter due to dead time, and the conventional problems can be solved.

[0024]

[Example] Figure 1 shows the neutral point clamp type inverter of the present invention.
1 shows an example of a main circuit configuration diagram and a block diagram of the control device for explaining the control device of the computer.

In the figure, Vd1 and Vd2 are DC power supplies, S1
, S2, S3, S4 are self-extinguishing elements, D1D2
, D3, D4 are free-wheeling diodes, D5
, D6 is the clamp diode, LOAD is the load,
CTU is a current detector. Also, as a control circuit, comparators CU, C1, C2, and a current control compensation circuit GU
(s), triangular wave generator TRG, Schmitt circuit SH1
, SH2, hysteresis circuit HS, inverter IV~I
V3 and AND circuits AND1 to AND4 are provided. Although this figure shows only one phase (U phase), in the case of a three-phase load, the other two phases (V phase, W phase) are configured in the same way.

The U-phase load current IU is detected by the current detector CTU.
and input it to the comparator CU of the current control circuit. Comparator CU compares current command value IU* and current detected value IU to obtain deviation εU=IU*-IU. The deviation εU is converted to the next control compensation circuit GU (s
) is amplified and used as the input signal ei for PWM control.

The triangular wave generator TRG generates two triangular waves X, Y
is generated and input to comparators C1 and C2. Comparator C
1 compares the triangular wave X with the input signal ei and generates a gate signal g1 for the elements S1 and S3 via the Schmitt circuit SH1. Also, comparator C2 is a triangular wave Y
and the input signal ei, and the Schmitt circuit SH2
gate signal g2 for elements S2 and S4 via
make. The hysteresis circuit HS detects the direction of the inverter's output current IU, and its output sig is as follows. When IU ≧0, sig=1 When IU <0, sig=0

The following logical operations are performed via inverters IV1 to IV3 and AND circuits AND1 to AND4 to obtain gate signals gs1 to gs4 of elements S1 to S4. That is, it becomes. FIG. 2 is a time chart diagram for explaining the operation of the present invention.

[0029] PWM control carrier wave X is 0 to +EMAX
It is a triangular wave with a constant frequency that changes between . Further, the carrier wave Y is a triangular wave with a constant frequency varying between 0 and -EMAX, and is in phase with the carrier wave X. The PWM control input signal ei and the triangular waves X, Y are compared, and the signals g1,
Make g2. That is, when ei>X, g1=1 when ei≦X, g1=0 when ei<Y, and g2=1 when ei≧Y, g2=0.

Furthermore, when the output current IU of the inverter changes as shown by the broken line, the output s of the hysteresis circuit HS
ig changes from "0" to "1" at point a and "1" at point b.
” becomes “0”. When sig=1 (IU ≧0), the gate signal gs1 of the element S1 becomes gs1=g1, which turns the element S1 on and off, and when sig=0 (IU <
0), gs1=0, turning off element S1. When sig=0 (IU <0), the gate signal gs2 of the element S2 becomes gs2=0, turning off the element S2. When sig=1 (IU≧0), the gate signal gs3 of the element S3 becomes gs3=0, turning off the element S3. Gate signal gs4 of element S4
is, when sig=0 (IU <0), gs4=g2
The element S4 is turned on and off, and sig=1(IU
≧0), gs4=0 and element S4 is turned off.

That is, when IU≧0, the lower element S
3 and S4 are in the off state, and the upper elements S1 and S
2 performs PWM control by turning on and off according to the original signals g1 and g2.

Furthermore, when IU <0, the upper element S
1 and S2 are in the off state, and the lower elements S3 and S
4 performs PWM control by turning on and off in accordance with the original signals g1 and g2.

Therefore, the conventional dead time ΔtD is no longer necessary, and the inverter output voltage VU is equal to the original signal g obtained by comparing the triangular waves X and Y of PWM control with the input signal ei.
1, g2, and its average value is proportional to the input signal ei.

FIG. 3 is a configuration diagram of a control circuit showing another embodiment of the present invention, in which MM1 and MM2 are monomulti circuits, AND1 to AND9 are AND circuits, and MT1 to M
T4 is a minimum on-time setting circuit, and OR1 and OR2 are OR circuits. Other symbols correspond to those shown in FIG. Moreover, FIG. 4 shows a specific circuit example of the minimum on-time setting circuit in FIG. 3, where MM11 is a monomulti circuit, O
R11 is an OR circuit. 5 and 6 are time charts for explaining the operation of the control circuit shown in FIG. 3. FIG. 3 and 4 while referring to FIGS. 5 and 6.
I will explain.

FIG. 5 is an enlarged view of point b in the time chart of FIG. 2, and the direction of the output current IU switches from positive to negative at point b. At the timing when the signal sig changes from "1" to "0", the monomulti circuit MM1 shown in FIG. 3 is triggered and its output m1 is set to "0" for a time Δt1. Near point b, g1 = 0, and g2 is the time ψ from point b.
It was switched from "0" to "1" just before. sig=
1 (IU≧0), gs3 and gs4 become 0 regardless of signals g1 and g2, and elements S3 and S4 are turned off. Switch from on to off before ψ. At point b, sig is “
When switching from "1" to "0", gs1, gs2 become "0" regardless of signals g1, g2, and elements S1,
S2 is turned off. That is, in this case, after a time ψ after the off signal is given to the element S2, the on signals are given to the elements S3 and S4.

Generally, the switching elements S1 to S4 constituting an inverter cannot be turned off immediately even if an off signal is applied, and there is a certain delay time. Similarly, there is a delay time when a device turns on, but the turn-off time is generally longer than the turn-on time. Therefore, if time ψ is shorter than the turn-off time of element S2, element S3 will turn off before element S2 turns off near point b.
, S4 is turned on, and the DC power supply Vd2 in Fig. 1 is turned on.
A short circuit occurs along the path D5 - element S2 - element S3 - element S4. This causes an excessive current to flow and destroy the element.

Therefore, as shown in FIG. 3, a monomulti circuit MM1 that operates at the rising edge of the signal sig and
A mono multi-circuit MM2 that operates at the falling edge of g is prepared, and its output signals m1 and m2 are connected to an AND circuit AN.
A logical product is obtained by D5, and m3 = m1 .m2 is inputted to the next logical product circuits AND6 to AND9.

As shown in FIG. 5, the monomulti circuit MM1
, MM2 output signals m1 and m2 become "0" only for the time Δt1. Logical product circuit AND6 ~ AND9
is the output signal gs1 of the AND circuits AND1 to AND4
~gs4 and the signal m3 are ANDed, as shown in Figure 5.
In the case of , the mono-multi circuit MM1 operates at point b and turns off all the elements S1 to S4 for a period of Δt1. As a result, the gate signal gs of elements S3 and S4
3 and gs4 are gs31 and gs4, respectively, as shown by the broken lines.
It becomes 1. If the setting time Δt1 of the monomulti circuits MM1 and MM2 is made longer than the turn-off time of the element,
The aforementioned DC short circuit can be prevented. FIG. 6 is an enlarged view of the vicinity of point b' in FIG. 2, assuming that the direction of the current changes at point b'.

At point b', the monomulti circuit MM1 operates, and gate signals gs11, gs21, gs31, and gs41 are applied so as to turn off all the elements by Δt1. As a result, the gate signal gs1 of element S1
1, the width of the on-period becomes narrower, and the minimum on-time of the element Δt
ON becomes unsatisfactory.

Generally, in a large-capacity inverter, a GTO (gate turn-off thyristor) or the like is used as a self-extinguishing element, and a snubber circuit is installed to suppress overvoltage at the time of turn-off. In order to initialize (discharge) the voltage of this snubber circuit capacitor, when the GTO is turned on, it must be kept on for a certain period of time (minimum on-time: about 100 microseconds, for example). If the element is turned off again before the voltage of this snubber capacitor becomes sufficiently low, the capacitor voltage becomes abnormally high, and an overvoltage is applied to the element, damaging the element.

In the case of FIG. 6, since the ON period of the element S1 is short, the snubber capacitor is not sufficiently discharged, and there is a risk that the element S1 will be broken due to overvoltage. Therefore, in FIG. 3, the gate signals gs11, gs21, gs31, gs
41 through the minimum on-time setting circuits MT1 to MT4, the signals gs12, gs22, gs32, gs
42.

A specific circuit example of the minimum on-time setting circuit MT1 is shown in FIG. Mono multi circuit MM11 has signal gs
11, and becomes "1" for a time Δt11. Mono-multi circuit MM by logical sum circuit OR11
The output signal m11 of No. 11 and the output signal gs11 of the AND circuit AND6 are logically summed to obtain the signal gs12 shown by the broken line in FIG. By making the set time Δt11 slightly longer than the above-mentioned minimum on-time ΔtON, the voltage of the snubber capacitor can be sufficiently discharged, and overvoltage will not occur.

However, one more problem remains here. That is, when the on-time of the element S1 is lengthened as described above, the element S1 is on and the element S2 is off during the period δ in FIG. During this period of δ, if the direction of the output current Iu of the inverter in Fig. 1 is flowing in the direction of the arrow in the figure, then the element S
Since 2 is off, the current IU is lower than diode D3.
, D4, and the cathode side terminal of element S2 is connected to the negative side of DC power supply Vd2, and since element S1 is on, the anode side terminal of element S2 is connected to the positive side of DC power supply Vd1. connected to the side. Therefore, a DC total voltage Vd=Vd1+Vd2 is applied to the element S2, and the overvoltage will destroy the element S2.

In order to solve this problem, the present invention provides logical sum circuits OR1 and OR2 as shown in FIG. That is, the gate signal gs11 of the element S1 is "
When the voltage is ``1'', the logical sum circuit OR1 causes the element S2 to also become ``1'', thereby preventing the full DC voltage from being applied to the element S2. To explain this with reference to FIG. 6, when the on period of the gate signal gs11 of the element S1 is expanded as in gs12, the gate signal gs of the element S2 is
21 also eliminates the above-mentioned mode in which the full DC voltage is applied to the element S2 by widening the on-period as in gs22 (indicated by a broken line). The upper two elements S1,
When S2 is on, the lower two elements S3 and S4 are always off, so the DC power supply will not be short-circuited.

This also applies to elements S3 and S4, and when element S4 is on, element S3 is always turned on by the logical sum circuit OR2.
This prevents the full DC voltage Vd from being applied to the At this time, since the upper two elements S1 and S2 are off, the DC power supply is not short-circuited.

As described above, according to the neutral point clamp type inverter control device of the present invention, either the upper two elements or the lower two elements can be turned off depending on the direction of the output current of the inverter. This eliminates the mode in which the DC power supply is short-circuited in the current state, eliminating the dead time that was previously considered indispensable. This improves the utilization rate of the converter, making it possible to reduce the size and weight of the device or reduce the cost. Further, disturbance to the current control system due to dead time is eliminated, and a distortion-free sinusoidal current can be supplied to the load.

In the apparatus shown in FIG. 1, the actual current IU is detected and used to determine the direction of the output current. In this case, when there is a ripple in the output current, the positive and negative states are frequently switched near the zero point, making it difficult to judge.

When controlling the output current of the inverter, it is preferable to use the current reference signal IU* to determine the direction of the output current. That is, there is no ripple in the current reference IU*, and the zero point can be easily determined.In particular, if it is considered that IU=IU* is established by current control, the error in determining the direction will be small. Even if the phase is slightly shifted, the current control waveform will be slightly distorted and there is no risk of damaging the device. Although the above description has been made regarding the U-phase inverter, the V-phase and W-phase are similarly controlled, and the conventional problems are solved. It goes without saying that the present invention can also be applied to three-phase, three-wire loads. Furthermore, although the explanation has been made assuming that the frequencies of the carrier waves X and Y are constant, it goes without saying that the same application can be made even if the frequencies are changed as long as the phases of the carrier waves are the same.

Furthermore, although the above embodiments have been shown as hardware control block diagrams to make the explanation easier to understand, it goes without saying that the present invention can be carried out by software calculations using a microcomputer or the like. stomach.

Although the inverter that converts DC power to AC power has been described above, it goes without saying that the present invention can be similarly applied to a converter that converts AC power to DC power.

[0051]

[Effects of the Invention] As explained above, according to the control device for a neutral point clamp type power converter of the present invention, it is possible to prevent DC power supply short circuits without providing dead time, which was conventionally required. It becomes possible. As a result, the utilization rate of the converter is improved, the device is made smaller and lighter, and costs are reduced. Also, disturbances to the current control system due to dead time are eliminated, and a distortion-free sine wave current is supplied to the load. It is possible to provide a control device for a neutral point clamp type power converter that can perform the following functions.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a main circuit and a block diagram of a control device showing an embodiment of a control device for a neutral point clamp type power converter according to the present invention.

FIG. 2 is a time chart diagram for explaining the operation of the present invention.

FIG. 3 is a control block diagram showing another embodiment of the present invention.

FIG. 4 is a partially detailed circuit diagram of FIG. 3;

FIG. 5 is a time chart diagram for explaining the operation of another embodiment of the modified invention shown in FIG. 3;

FIG. 6 is a time chart diagram for explaining the operation of another embodiment of the modified invention shown in FIG. 3;

FIG. 7 is a block diagram of a main circuit of a neutral point clamp type power converter and a lock diagram of a conventional control device.

FIG. 8 is a time chart diagram for explaining operations by a conventional control device.

FIG. 9 is a time chart diagram for explaining operations by a conventional control device.

FIG. 10 is a time chart diagram for explaining operations by a conventional control device.

[Explanation of symbols]

Vd1, Vd2...DC power supply, S1 to S4...Self-extinguishing element, D1 to D4...Free wheeling diode,
D5, D6...Clamp diode, LOAD...Load, CTU...Current detector, CU, C1, C2, C
3...Comparator, GU(s)...Current control compensation circuit, T
RG...Triangular wave generator, SH1, SH2, SH3...
Schmitt circuit, HS...Hysteresis circuit, IV1 ~
IV3...Inversion circuit, AND1 to AND9...AND circuit, MM1, MM2, MM11...Mono multi circuit,
MT1 to MT4...Minimum on-time setting circuit, OR1
, OR2, OR11...OR circuit.

Claims (4)

[Claims] Claim 1: Four self-extinguishing elements S1, S2, S3, S4 connected in series, and free-wheeling diodes D1, D connected antiparallel to each of these elements.
2, D3, D4 and clamping diode D5,
In a neutral point clamp type power converter configured with D6, one is a triangular wave X that changes between zero and the positive side, and the other is a triangular wave Y that changes between zero and the negative side, as carrier waves for pulse width modulation control. and a triangular wave generating means for generating an output current of the power converter or a signal I corresponding to the output current.
a means for determining the direction of U, and a means for determining the direction of IU;
Under the condition of 0, the lower two self-extinguishing elements S3 and S4
is turned off, the PWM control input signal ei is compared with the triangular waves X and Y, and when ei > X, the two upper self-extinguishing elements S1 and S2 are turned on. Self-extinguishing element S2 of
(turn off S1) When ei <Y, the two upper self-extinguishing elements S1
. When the arc-extinguishing elements S3 and S4 are turned off when Y≦ei≦X, the lower self-extinguishing element S3
(turn off S4) When ei <Y, the lower two self-extinguishing elements S3
, S4. [Claim 2] The upper two self-extinguishing elements S1
, S2, when an on-gate signal is given to the self-extinguishing element S1, an on-gate signal is always given to the self-extinguishing element S2, and the two lower self-extinguishing elements S3, S
4. The neutral point according to claim 1, characterized in that when an on-gate signal is given to the self-arc extinguishing element S4 among the self-arc extinguishing elements S4, a means for always giving an on-gate signal to the self-arc extinguishing element S3 is provided. Control device for clamp type power converter. 3. Four self-extinguishing elements S1, S2, S3, S4 connected in series, and free-wheeling diodes D1, D connected in antiparallel to each of these elements.
2, D3, D4 and clamping diode D5,
In a neutral point clamp type power converter configured with D6, one is a triangular wave X that changes between zero and the positive side, and the other is a triangular wave Y that changes between zero and the negative side, as carrier waves for pulse width modulation control. and a triangular wave generating means for generating an output current of the power converter or a signal I corresponding to the output current.
a means for determining the direction of U, and a means for determining the direction of IU;
Under the condition of 0, the lower two self-extinguishing elements S3 and S4
is turned off, the PWM control input signal ei is compared with the triangular waves X and Y, and when ei > X, the two upper self-extinguishing elements S1 and S2 are turned on. Self-extinguishing element S2 of
(turn off S1) When ei <Y, the two upper self-extinguishing elements S1
. When the arc-extinguishing elements S3 and S4 are turned off when Y≦ei≦X, the lower self-extinguishing element S3
(turn off S4) When ei <Y, the lower two self-extinguishing elements S3
, S4, and locking the gate signal for a predetermined time Δt1 when the direction of the output current of the power converter or the signal IU corresponding to the output current is switched. A control device for a neutral point clamp type power converter, comprising means. 4. When locking the gate signal for the predetermined time Δt1, the device further comprises means for ensuring a minimum on-time of a self-extinguishing element that has been on until then. A control device for a neutral point clamp type power converter according to item 3.