JP2006014532A - Three-level power converting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a three-level power converting device that reduces device capacity reduction rate in a low frequency range. <P>SOLUTION: This device is provided with: a three-level power converter 3 that converts DC electric power to three-phase AC electric power, a main controlling means 72 for controlling a load; a voltage reference converting means 73 that converts a biaxial voltage reference outputted from the main controlling means into a three-phase output voltage reference; and a PWM modulating means 74 that compares the output voltage reference with a carrier to generate a gate signal of the three-level power converter. The voltage reference converting means is configured to comprise a coordinate transforming means that converts the biaxial voltage reference into the three-phase basic voltage reference based on a phase reference; a bias adding means that adds a bias value, switching the positive/negative polarity in prescribed cycles, to the three-phase basic voltage reference, and an output of the coordinate transforming means; and a trapezoidal wave modulating means that limits the amplitude of each phase of the three-phase basic voltage reference by a prescribed limit value, and that adds correction to other phases in such a way as not to cause distortion to line-to-line voltages. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a three-level power conversion device, and more particularly to a three-level power conversion device with an improved control method in a low frequency region.

  2. Description of the Related Art Conventionally, a power converter that controls an output voltage by a so-called PWM (pulse width modulation) control system, for example, an inverter device, uses a self-extinguishing element such as an IGBT in its main circuit and is turned on for a predetermined period for each modulation period. A pulsed voltage that is in a state is output, and the average voltage is controlled. When the inverter device reaches the 3rd level, a mode for outputting a zero voltage is added in addition to the positive voltage and the negative voltage, and PWM of four self-extinguishing elements per arm which is doubled as compared with the 2 level inverter device. Although it is necessary to perform control, the basic concept of control remains the same.

  In a three-level inverter device, when the output frequency is low and therefore the output voltage is low, when the voltage reference and the modulation carrier are compared to create a gate control pulse, the pulse is allowed due to the characteristics of the self-extinguishing element. There has been a problem that the pulse width cannot be reduced (hereinafter referred to as the minimum on-pulse width).

In order to solve this problem, a so-called rectangular PWM method has been proposed. In this rectangular PWM method, a predetermined bias value is added to the three-phase voltage reference to avoid PWM modulation near zero voltage, and the polarity of the three-phase voltage reference is controlled as the same polarity, and this polarity is switched at a predetermined cycle. Is. (For example, refer to Patent Document 1).
JP-A-5-268773 (page 4-6, FIG. 1)

  In the conventional method shown in Patent Document 1, since a predetermined bias value, for example, the minimum value of the three-phase voltage reference is added, a pulse having a width less than the minimum on-pulse width is not generated, and This is switched at a predetermined cycle so as to balance the energization rates of the positive and negative self-extinguishing elements.

  However, the energization balance between the outer self-extinguishing element connected to the DC bus constituting the positive and negative arms of the three-level inverter device and the inner self-extinguishing element connected to the load. As a result, the current concentrates on the two self-extinguishing elements inside the positive side and the negative side in the low frequency region, and the inverter device cannot pass a sufficient current in the low frequency region. There was a problem that the reduction rate of the device capacity had to be increased.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a three-level power conversion device that can reduce the device capacity reduction rate in the low frequency region.

In order to achieve the above object, a three-level power converter of the present invention includes a three-level power converter that converts DC power supplied from a DC power source into three-phase AC power and supplies it to a load such as an electric motor,
Main control means for controlling the speed of the motor, voltage reference conversion means for converting the D-axis voltage reference and the Q-axis voltage reference output from the main control means into a three-phase output voltage reference, and the output PWM modulation means for generating a gate signal of the three-level power converter by comparing a voltage reference with a carrier, the voltage reference conversion means based on the phase reference based on the D-axis voltage reference and the Q-axis voltage reference A coordinate conversion means for converting to a three-phase basic voltage reference; a bias addition means for adding a bias value to the three-phase basic voltage reference, which is an output of the coordinate conversion circuit; And a trapezoidal wave modulation means for limiting the amplitude of each phase of the phase basic voltage reference with a predetermined limit value and correcting other phases so as not to cause distortion in the line voltage. .

  According to the present invention, since PWM modulation is performed in consideration of the current-carrying balance of the self-extinguishing element, it is possible to provide a three-level power converter that can reduce the device capacity reduction rate in the low frequency region. .

  Embodiments of the present invention will be described below with reference to the drawings.

  A first embodiment of a three-level power converter according to the present invention will be described with reference to FIGS. FIG. 1A is a circuit configuration diagram showing Embodiment 1 of the present invention.

  The DC power supply 1 supplies three levels of DC voltage, and supplies DC power to the three-level converter 3 via the positive-side smoothing capacitor 2A and the negative-side smoothing capacitor 2B. The three-level converter 3 converts this DC power into three-phase AC power and drives the motor 4. The electric motor 4 is provided with a rotation angle detector 5 for detecting the rotation phase thereof, and a current detector 6 for detecting an input current. The rotation angle detector 5 and the current detector 6 can be omitted.

  The self-extinguishing element constituting the three-level converter 3 is PWM-controlled by a gate signal from the control unit 7. The configuration of the control unit 7 will be described below.

  The phase angle detected by the rotation angle detector 5 is converted into the rotation speed ωr by the differentiator 71, and is compared and amplified by the given speed reference ω * and the motor controller 72 which is the main controller, and further becomes a current reference. This current reference is similarly amplified and compared with the output of the current detector 6 by the motor controller 72 to obtain d-axis and q-axis voltage references ED_R and EQ_R. The phase reference θ1 based on the phase angle detected by the rotation angle detector 5 is used for these two-axis conversions. The d-axis voltage reference ED_R and the q-axis voltage reference EQ_R are converted into three-phase voltage references VU_REF, VV_REF, and VW_REF by the voltage reference converter 73.

  A detailed circuit configuration of the voltage reference converter 73 is shown in FIG. As shown in FIG. 1B, the d-axis voltage reference ED_R and the q-axis voltage reference EQ_R are first converted into three-phase basic voltage references EU_R, EV_R, and EW_R by the coordinate conversion circuit 731 using the phase reference θ1. .

  A bias value obtained by the bias addition circuit 732 is added to each of the three-phase basic voltage references EU_R, EV_R, and EW_R. The bias addition circuit 732 outputs a pulsed bias in which the reference bias value BIAS is switched between positive and negative at a constant switching cycle by a timer. In this way, the signal in which the bias is added to each of the three-phase basic voltage references EU_R, EV_R, and EW_R is transformed by the trapezoidal wave modulation circuit 733 so that the peak portion of the sine wave is cut to a constant value. Converted to output voltage references VU_REF, VV_REF and VW_REF.

  The trapezoidal wave modulation circuit 733 has a limit circuit at the input part of each of the three phases, a value obtained by subtracting the original signal from the limit circuit output of each phase, and each original signal from the limit circuit output for the other two phases. The original signal is added to the value obtained by adding the value obtained by subtracting. In this way, when a certain phase is applied to the limit circuit, the other two phases are corrected so that the line voltage does not change.

  The three-phase output voltage references VU_REF, VV_REFEF, and VW_REF obtained as described above are compared with the carrier from the carrier generation circuit 75 by the PWM modulation circuit 74, and as a result, the self-extinguishing constituting the three-level converter 3 is performed. A gate signal of the mold element is obtained.

  FIG. 2 is an internal configuration diagram showing one arm of the three-level converter 3.

  As shown in FIG. 2, one arm is formed by connecting self-extinguishing elements Q1, Q2, Q3 and Q4 in series. Flywheel diodes D1, D2, D3 and D4 are connected in antiparallel to the self-extinguishing elements Q1, Q2, Q3 and Q4, respectively. Further, the potential between the self-extinguishing elements Q1 and Q2 is clamped to the clamp diode Dp, and the potential between the self-extinguishing elements Q3 and Q4 is clamped to the zero potential by the clamp diode Dn.

  In the above configuration, when the self-extinguishing elements Q1 and Q2 are on and the self-extinguishing elements Q3 and Q4 are off, a DC voltage + Ed is supplied to the output terminal, and conversely, the self-extinguishing elements Q1 and Q2 are When the off and self-extinguishing elements Q3 and Q4 are on, a DC voltage -Ed is supplied to the output terminal. When the self-extinguishing elements Q1 and Q4 are off and the self-extinguishing elements Q2 and Q3 are on, the output terminal voltage is zero.

  FIG. 3 shows an example of a three-phase output voltage reference waveform obtained by the three-level power converter of the present invention. In the case of FIG. 3, the bias value BIAS is about 50% of the carrier amplitude, and the limit value of the trapezoidal wave modulation circuit 733 is a value obtained by subtracting a predetermined value from the carrier amplitude. The other phases are corrected so that the inter-voltage does not change to ensure the minimum on-pulse width.

  FIG. 4 shows an example of PWM modulation in which the three-phase output voltage reference shown in FIG. 3 is compared with a carrier to create a gate pulse of each element, and shows the time scale of the period T in FIG. The three-phase output voltage reference VV_REF is compared with the positive and negative carriers, and when VV_REF> positive carrier, the self-extinguishing element Q1 is turned on, and when VV_REF <positive carrier, the self-extinguishing element Q1 is turned off. The self-extinguishing element Q3 is the opposite. Similarly, when VV_REF <negative carrier, the self-extinguishing element Q4 is turned on. When VV_REF> negative carrier, the self-extinguishing element Q4 is turned off, and the self-extinguishing element Q2 is reversed.

  Here, the energization balance between the self-extinguishing elements Q1 and Q4 which are elements outside the arm and the self-extinguishing elements Q2 and Q3 which are elements inside the arm will be considered.

  As can be seen from FIG. 4, even when the bias value BIAS is about 50% of the carrier amplitude, the energization rates of the self-extinguishing elements Q2 and Q3 are considerably higher than the energization rates of the self-extinguishing elements Q1 and Q4. It turns out that the burden is large. Here, considering the case where the bias value BIAS is further reduced from the state of FIG. 4, the energization pulse width of the self-extinguishing element Q3 in the positive bias period and the energization pulse width of the self-extinguishing element Q2 in the negative bias period It can be seen that the self-extinguishing elements Q2 and Q3 are almost always energized. This is because the self-extinguishing elements Q2 and Q3 are both turned on when the reference voltage is small, and the period during which zero voltage is output increases.

  Conversely, when the bias value BIAS is further increased from the state of FIG. 4, the energization pulse width of the self-extinguishing element Q3 in the positive bias period and the energization pulse width of the self-extinguishing element Q2 in the negative bias period are As a result, the conduction rate of the self-extinguishing elements Q2 and Q3 approaches the conduction rate of the self-extinguishing elements Q1 and Q4.

  As described above, if the bias value in the rectangular modulation mode is increased, the conduction ratio of the self-extinguishing elements Q2 and Q3 and the conduction ratio of the self-extinguishing elements Q1 and Q4 in the low frequency and low voltage range are Come to balance. In terms of device design, it is preferable to suppress the reduction rate of the inverter capacity, that is, the above-described imbalance of the current supply rate to about 10%. For this purpose, the ratio of the bias value to the carrier amplitude should be about 90%, but in practice, a slight increase in the current ratio is allowed, and the ratio of the bias value to the carrier amplitude is 80%. That's all you need to do.

  FIG. 5 is a circuit configuration diagram showing Embodiment 2 of the three-level power converter of the present invention. In the second embodiment, the same parts as those of the voltage reference conversion circuit of the three-level power converter according to the first embodiment shown in FIG. 1B are denoted by the same reference numerals, and the description thereof is omitted. The second embodiment differs from the first embodiment in that a bias changing circuit 734 is provided so that the bias value is automatically changed according to the change in the rotational speed ωr or the speed reference ωr *.

  As described above, the energization rate of the self-extinguishing elements Q2 and Q3 and the conduction rate of the self-extinguishing elements Q1 and Q4 are unbalanced when the voltage is low, that is, when the rotational speed ωr of the motor 4 is low. is there. Therefore, the bias value is increased to balance the power supply rate when the rotational speed ωr is low. As a characteristic of the bias changing circuit 734, the bias value may be increased smoothly according to the decrease in the rotational speed ωr, or may be switched stepwise. Further, it may be switched in two steps so that the bias value becomes 80% or more of the carrier amplitude at a certain speed or less. In consideration of application when the load is not an electric motor, the output frequency of the three-level converter 3 may be used instead of the rotational speed ωr.

According to the second embodiment, it is possible to suppress an increase in current ripple caused by increasing the bias value more than necessary in a high speed or medium speed range.

The circuit block diagram which shows Example 1 of the three-level power converter device by this invention. The circuit block diagram of the 3 level power converter used for the 3 level power converter by this invention. The wave form diagram which shows an example of the output voltage reference | standard of the 3 level power converter device by this invention. The wave form diagram which shows an example of the PWM modulation of the 3 level power converter device by this invention. The circuit block diagram which shows Example 2 of the three-level power converter device by this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC power supply 2A, 2B Smoothing capacitor 3 3 level converter 4 Electric motor 5 Phase angle detector 6 Current detector 7 Control part 71 Differentiator 72 Electric motor controller 73 Voltage reference conversion part 74 PWM modulation circuit 75 Carrier generation circuit 731 Coordinate conversion Circuit 732 Bias addition circuit 733 Trapezoidal wave modulation circuit 734 Bias change circuit

Claims (3)

A three-level power converter that converts DC power supplied from a DC power source into three-phase AC power and supplies it to a load such as an electric motor;
Main control means for controlling the speed and the like of the motor;
Voltage reference conversion means for converting the D-axis voltage reference and the Q-axis voltage reference output from the main control means into a three-phase output voltage reference;
PWM modulation means for comparing the output voltage reference with a carrier to generate a gate signal of the three-level power converter;
The voltage reference conversion means includes
Coordinate conversion means for converting the D-axis voltage reference and the Q-axis voltage reference into a three-phase basic voltage reference based on a phase reference;
Bias adding means for adding a bias value while switching positive and negative polarities with a predetermined period to a three-phase basic voltage reference that is an output of the coordinate conversion circuit;
Trapezoidal wave modulation means for limiting the amplitude of each phase of the three-phase basic voltage reference with a predetermined limit value and correcting other phases so as not to cause distortion in the line voltage. A three-level power converter.   The three-level power converter according to claim 1, wherein the bias value is 80% or more of the amplitude of the carrier. 2. The three-level power converter according to claim 1, wherein the bias value is increased in accordance with a decrease in an output frequency of the three-level power converter.

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