JP2018057157A - Electric power conversion system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electric power conversion system which prevents mutual intervention between a neutral point potential variation inhibitory control and a conduction balance control to be capable of securing conduction balance while suppressing variation in the neutral point potential.SOLUTION: An electric power conversion system comprises: a voltage command calculation unit which calculates a voltage command value to a three level inverter on the basis of an input from outside; a conduction balance control unit which adds a bias value while switching the positive/negative polarity in prescribed cycles set to the voltage command value on the basis of an input from outside; a PWM generation unit which generates a gate signal to the switching element of the three level inverter by use of the voltage command value to which the bias value is added; a voltage detection unit which detects voltages of a positive electrode side capacitor and a negative electrode side capacitor as the positive electrode side voltage and the negative electrode side voltage; and a dead time setting unit which sets, on the basis of the potential difference between the positive electrode side voltage and the negative electrode side voltage, a dead time of the switching element with respect to the gate signal generated by the PWM generation unit to reduce the potential difference.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a power conversion device using a three-level inverter.

  Conventionally, two carrier waves, which are a triangular wave that changes between zero and the plus side and a triangular wave that changes between zero and the minus side, are compared with the voltage command value, and based on the magnitude relationship of the comparison results, There is known a power conversion device that generates a gate signal for turning on or off a switching element and controls a three-level inverter in accordance with the gate signal.

  In addition, in a power converter using a three-level inverter, neutral point potential fluctuation suppression control for calculating a neutral point bias voltage to be added to the voltage command value in order to suppress fluctuations in the neutral point potential of the DC power supply. A polarity determination unit that determines the polarity of the neutral point bias voltage and outputs a polarity signal, and a voltage obtained by adding a neutral point bias voltage in order to ensure a predetermined minimum on-pulse width for the gate signal The neutral point bias voltage and the on-pulse bias voltage are provided with a minimum on-pulse control unit that calculates an on-pulse bias voltage that is a value that is added to the command value and is determined based on the polarity signal. Has been proposed to suppress interference with each other (see, for example, Patent Document 1).

  Here, in the three-level inverter, when the modulation rate obtained by standardizing the voltage command value with the rated DC voltage is 0.5 or less, compared to the conduction rate of the P / N side element arranged on the outside. Further, the flow rate of the neutral point side element arranged on the inner side is increased.

  For this reason, for example, in V / F control, during low frequency operation where the modulation factor is low, current concentrates on the neutral point side element, and sufficient current cannot flow in the low frequency region as an inverter device. There was a problem that the reduction rate of the capacity had to be increased. Therefore, flow balance control has been proposed as a method for improving the flow rate of the neutral point side element during low-frequency operation (see, for example, Patent Document 2).

  In the current balance control, a neutral wave during low frequency operation is added by adding a rectangular wave pulse whose amplitude increases as the frequency is low, that is, as the modulation rate is small, to the voltage command value according to the output frequency of the inverter. The flow rate of the point side element and the flow rate of the P / N side element are made close to ensure a flow balance.

JP 2013-110815 A JP 2006-14532 A

  However, even if the current balance control is applied in the problem of Patent Document 1, the neutral point potential fluctuation suppression control and the current balance control are both methods in which a bias value is added to the voltage command value. Therefore, there are problems that these bias values interfere with each other, the neutral point potential fluctuates, and the control becomes unstable.

  The present invention has been made to solve the above-described problems, and prevents neutral point potential fluctuations by preventing mutual interference between neutral point potential fluctuation suppression control and flow balance control. At the same time, an object is to obtain a power conversion device capable of ensuring a flow balance.

  The power conversion device according to the present invention includes a positive-side capacitor and a negative-side capacitor that are connected in series between a positive electrode side and a negative electrode side of a DC power source and that have a connection point as a neutral point. A three-level inverter that converts DC power to AC power and supplies it to the motor, a voltage command calculation unit that calculates a voltage command value for the three-level inverter based on an external frequency command or speed command, and an external frequency Based on the command or speed command, a current balance control unit that adds a bias value while switching between positive and negative polarities at a preset period to the voltage command value, and 3 based on the voltage command value to which the bias value is added PWM generator that generates a gate signal for the switching element of the level inverter, and positive and negative capacitors The switching element dead time for the gate signal generated by the PWM generator so that the potential difference is reduced based on the potential difference between the positive voltage and the negative voltage, and the voltage detector that detects the voltage and the negative voltage. And a dead time setting unit for setting.

According to the power converter of the present invention, based on an external frequency command or speed command, a voltage command calculation unit that calculates a voltage command value for the three-level inverter, and on the basis of an external frequency command or speed command A current balance control unit that adds a bias value while switching between positive and negative polarities at a preset period to a voltage command value, and a gate for a switching element of a three-level inverter based on the voltage command value to which the bias value is added Based on the potential difference between the positive voltage and negative voltage, the PWM generator that generates the signal, the voltage detector that detects the voltages of the positive and negative capacitors as the positive and negative voltages, For the gate signal generated by the PWM generator, the dead time of the switching element And a dead time setting unit for setting.
Therefore, it is possible to prevent the neutral point potential fluctuation suppression control and the flow balance control from interfering with each other, thereby suppressing the fluctuation of the neutral point potential and ensuring the flow balance.

It is a circuit diagram which shows the 3 level inverter of the power converter device which concerns on Embodiment 1 of this invention with a DC power supply and a motor. It is a block block diagram which shows the control part of the power converter device which concerns on Embodiment 1 of this invention. (A)-(d) is explanatory drawing which shows the circuit operation mode for one phase of the 3 level inverter shown in FIG. It is a block block diagram which shows the neutral point electric potential fluctuation suppression control part shown in FIG. It is a block block diagram which shows the dead time production | generation part shown in FIG. It is explanatory drawing which shows the simulation result of the dead time in the power converter device which applied the neutral point potential fluctuation | variation control and the current balance control simultaneously in the past. It is explanatory drawing which shows the simulation result of the dead time in the power converter device which applied simultaneously neutral point potential fluctuation | variation suppression control and flow balance control which concern on Embodiment 1 of this invention. It is explanatory drawing which shows the simulation result of the electrical potential difference in the power converter device which applied the neutral point electric potential fluctuation | variation suppression control and conventional flow balance control simultaneously. It is explanatory drawing which shows the simulation result of the electric potential difference in the power converter device which applied simultaneously neutral point electric potential fluctuation | variation suppression control and flow balance control which concern on Embodiment 1 of this invention.

  Hereinafter, preferred embodiments of a power conversion device according to the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts will be described with the same reference numerals.

  First, prior to description of the embodiments, an outline of a power conversion device according to the present invention will be described. The power conversion device of the present invention detects a DC voltage of the positive side capacitor and the negative side capacitor of the three-level inverter, and normally suppresses fluctuations in the neutral point potential according to the potential difference between them. The dead time of the switching element of a certain inverter is changed.

  Specifically, the DC voltage is fed back, and PI control is performed so that the DC voltage is balanced. At this time, since the output of the PI controller becomes a dead time correction amount, the dead time is changed in accordance with the degree of imbalance of the DC voltage. This is performed individually for each of the three phases.

  Thus, by adopting neutral point potential fluctuation suppression control that changes the dead time of the switching element of the inverter, it is possible to achieve both neutral point potential fluctuation suppression control and flow balance control.

  Moreover, since the imbalance of the DC voltage is improved by suppressing the fluctuation of the neutral point potential, the apparatus can be miniaturized without increasing the withstand voltage and the capacitance of the capacitor more than necessary. In addition, since current does not concentrate on the neutral point side element during low frequency operation, the reduction rate of the device capacity can be reduced and the device can be downsized. The power converter according to the present invention can be applied regardless of the control type, such as V / F control and vector control.

Embodiment 1 FIG.
1 is a circuit diagram showing a three-level inverter of a power conversion device according to Embodiment 1 of the present invention, together with a DC power supply and a motor. In FIG. 1, a three-level inverter 10 is connected to a DC power source 1 and a motor 2 whose neutral points are grounded.

  The three-level inverter 10 is connected in series between the positive electrode side and the negative electrode side of the DC power source 1, and includes a positive electrode capacitor 11 and a negative electrode capacitor 12 having a connection point as a neutral point, and four capacitors per phase. A three-phase three-level inverter composed of switching elements Q1 to Q4 is provided, and DC power from the DC power source 1 is converted into AC power and supplied to the motor 2.

  Here, the four switching elements constituting one phase 13 of the three-level inverter include two neutral point elements Q3 and Q4 connected as a bidirectional switch to the neutral point, and the positive side of the DC power source 1. The positive electrode element Q1 and the negative electrode element Q2 connected in series with each other between the negative electrode side and the negative electrode side, thereby realizing a three-level inverter.

  Further, the three-level inverter 10 is provided with voltage sensors 14 and 15 for detecting the voltages of the positive side capacitor 11 and the negative side capacitor 12 as the positive side voltage Vc1 and the negative side voltage Vc2, respectively.

  FIG. 2 is a block configuration diagram showing a control unit of the power conversion apparatus according to Embodiment 1 of the present invention. In FIG. 2, this control unit includes a V / F control unit 20, a flow balance control unit 30, a trapezoidal wave modulation circuit 40, a PWM (Pulse Width Modulation) generation unit 50, and neutral point potential fluctuation suppression control. Unit 60 and dead time generation unit 70.

  The V / F control unit 20 realizes a general motor variable speed control by inverter driving, and uses a frequency command f * corresponding to the rotation speed of the motor 2 to perform a voltage command after the flow balance control. The values Vuu *, Vvv *, Vww * are output. The V / F control unit 20 includes a V / F pattern 21, an integrator 22, a three-phase sin table 23, and an adder 24.

  The V / F pattern 21 stores the relationship between the frequency f and the modulation factor a, and outputs the modulation factor a in response to the input frequency command f *. Here, in the V / F control, the frequency f and the modulation factor a are in a proportional relationship, and when the frequency f is low, the modulation factor a is also low. The integrator 22 integrates the frequency command f * and calculates the phase angle θ.

  The three-phase sin table 23 stores the relationship between the modulation factor a and the phase angle θ and the voltage command values Vu *, Vv *, and Vw *. For the input modulation factor a and the phase angle θ, Three-phase voltage command values Vu *, Vv *, Vw * are output.

  The adder 24 adds the pulse-shaped bias output from the flow balance control unit 30 to the voltage command values Vu *, Vv *, Vw * output from the three-phase sin table 23, thereby performing flow balance control. The subsequent voltage command values Vuu *, Vvv *, and Vww * are output.

  The flow balance control unit 30 generates a pulse-like bias to be added to the voltage command values Vu *, Vv *, and Vw * using the frequency command f *. Further, the flow balance control unit 30 includes a bias pattern 31 and a multiplier 32.

  The bias pattern 31 stores the relationship between the frequency f and the bias value, and outputs a bias value in response to the input frequency command f *. Here, the frequency f and the bias value are in an inversely proportional relationship, and when the frequency f is low, the bias value becomes high. The multiplier 32 multiplies the bias value output from the bias pattern 31 by a rectangular wave pulse that vibrates on the + side and the − side at a preset period to generate a pulse-like bias.

  The trapezoidal wave modulation circuit 40 cuts the peak portion of the sine wave to a constant value with respect to the voltage command values Vuu *, Vvv *, and Vww * after the flow balance control output from the V / F control unit 20. The voltage command values Vuuu *, Vvvv *, and Vwww * after the trapezoidal wave modulation are output after being deformed.

  The trapezoidal wave modulation circuit 40 has a limit circuit 41 at each of the three-phase input units, and the value obtained by subtracting the original signal from the limit circuit output of each phase and the limit circuit output for the other two phases, respectively. The original signal is added to the value obtained by adding the value obtained by subtracting the original signal. Thereby, when a certain phase is applied to the limit circuit 41, the other two phases are corrected so that the line voltage does not change.

  The PWM generation unit 50 generates a gate signal for the three-level inverter 10 based on the voltage command values Vuu *, Vvvv *, and Vwww * after the trapezoidal wave modulation. Here, the PWM generation unit 50 compares the voltage command value with two carrier waves that are a triangular wave that changes between zero and the positive side and a triangular wave that changes between the zero and the negative side. Based on this, a gate signal for turning on or off switching elements Q1-Q4 is generated.

  Here, since the operation of a general PWM generation unit is described in, for example, Patent Document 2 and the like, description thereof is omitted. Note that the gate signal output from the PWM generator 50 does not include the dead time Td. Further, the neutral point potential fluctuation suppression control unit 60 and the dead time generation unit 70 suppress the fluctuation of the neutral point potential by changing the dead time Td of the twelve switching elements constituting the three-level inverter 10. .

  Hereinafter, with reference to FIGS. 3A to 3D, a method for suppressing the fluctuation of the neutral point potential by changing the dead time Td of the switching elements Q1 to Q4 of the three-level inverter 10 will be described. To do. FIGS. 3A to 3D are explanatory diagrams showing circuit operation characteristics for one phase of the three-level inverter shown in FIG. In order to make the explanation easy to understand, attention is paid to only one phase, but the actual control operates in all three phases.

  First, FIG. 3A shows a state where the output current (neutral point current) of the three-level inverter 10> 0 and the switching elements Q1 and Q3 are switched (voltage command> 0). In FIG. 3A, a solid line indicates a current path in which the switching element Q1 is on, and a dotted line indicates a current path during a dead time period.

  Note that, during the dead time period, both the switching elements Q1 and Q3 are in the off state, and the switching element Q4 is always in the on state, so that a current flows through the diode D3 and the switching element Q4.

  FIG. 3B shows a state where the output current of the three-level inverter 10 <0 and the switching elements Q1 and Q3 are switched (voltage command> 0). In FIG. 3B, a solid line indicates a current path in which the switching element Q3 is on, and a dotted line indicates a current path during the dead time period. Note that during the dead time period, since both the switching elements Q1 and Q3 are in the off state, a current flows through the diode D1.

  FIG. 3C shows a state where the output current of the three-level inverter 10> 0 and the switching elements Q2 and Q4 are switched (voltage command <0). In FIG. 3C, a solid line indicates a current path in which the switching element Q4 is turned on, and a dotted line indicates a current path during the dead time period. During the dead time period, since both switching elements Q2 and Q4 are in the off state, a current flows through diode D2.

  FIG. 3D shows a state where the output current of the three-level inverter 10 <0 and the switching elements Q2 and Q4 are switched (voltage command> 0). In FIG. 3D, a solid line indicates a current path in which the switching element Q2 is on, and a dotted line indicates a current path during the dead time period.

  During the dead time, both switching elements Q2 and Q4 are in the off state and switching element Q3 is always in the on state, so that a current flows through diode D4 and switching element Q3.

  Here, it can be seen from FIG. 3A and FIG. 3B that the negative-side capacitor 12 is discharged or the positive-side capacitor 11 is charged during the dead time period of the switching elements Q1 and Q3. That is, in this case, it can be seen that the positive side voltage Vc1 of the positive side capacitor 11 is increased and the negative side voltage Vc2 of the negative side capacitor 12 is decreased.

  3C and 3D show that the negative capacitor 12 is charged during the dead time period of the switching elements Q2 and Q4. That is, in this case, it can be seen that the negative electrode side voltage Vc2 of the negative electrode side capacitor 12 increases and the positive electrode side voltage Vc1 of the positive electrode side capacitor 11 decreases.

In view of the above-described circuit operation characteristics, the neutral point potential fluctuation suppression control unit 60 and the dead time generation unit 70 constitute a control system that satisfies the following conditions.
Positive side voltage Vc1 <negative side voltage Vc2: The dead time Td of the switching elements Q1 and Q3 is lengthened, and the dead time Td of the switching elements Q2 and Q4 is shortened.
Positive side voltage Vc1> Negative side voltage Vc2: Dead time Td of switching elements Q1 and Q3 is shortened, and dead time Td of switching elements Q2 and Q4 is lengthened.

  Hereinafter, the detailed configuration of the neutral point potential fluctuation suppression control unit 60 and the dead time generation unit 70 will be described with reference to FIGS. 4 and 5. FIG. 4 is a block configuration diagram showing the neutral point potential fluctuation suppression control unit shown in FIG. 2, and FIG. 5 is a block configuration diagram showing the dead time generation unit shown in FIG.

  In FIG. 4, the neutral point potential fluctuation suppression control unit 60 includes a subtractor 61, a PI controller 62, an upper / lower limiter 63, an adder 64, an upper / lower limiter 65, a subtractor 66, an inverting circuit 67, and an upper / lower limiter 68. have.

  The subtractor 61 calculates a deviation ΔV between the positive side voltage Vc1 and the negative side voltage Vc2. The PI controller 62 executes PI control so that the deviation ΔV becomes zero, and calculates the amount of change in the dead time Td by multiplying the deviation ΔV by a preset coefficient K. The upper / lower limiter 63 limits the upper / lower limit value so that the amount of change in the dead time Td falls within a preset range.

  The adder 64 adds the amount of change in the dead time Td whose upper and lower limits are limited and the initial value of the dead time Td (usually 3 to 5 μsec). The upper / lower limiter 65 limits the upper / lower limit value so that the output from the adder 64 falls within a preset range, and outputs it as an N-side Td bias value. The N-side Td bias value is used to change the dead time Td of the switching elements Q2 and Q4.

  The subtractor 66 subtracts the initial value of the dead time Td from the change amount of the dead time Td whose upper and lower limit values are limited. The inversion circuit 67 inverts the sign by multiplying the output from the subtractor 66 by -1. The upper / lower limiter 68 limits the upper / lower limit value so that the output from the inverting circuit 67 falls within a preset range, and outputs the result as a P-side Td bias value. The P-side Td bias value is used to change the dead time Td of the switching elements Q1 and Q3.

  Here, the PI controller 62 calculates a dead time correction amount according to the deviation ΔV. For example, when the output of the PI controller 62 is 1 μsec and the initial value of the dead time Td is 5 μsec in the case of a certain deviation ΔV, the N-side Td bias value is 6 μsec and the P-side Td bias value is 4 μsec. Become. The upper and lower limiters 63, 65, and 68 are provided to limit the variable range of the dead time when the amount of change in the dead time Td is extremely large or extremely small.

  In FIG. 5, the dead time generation unit 70 receives a gate signal that does not include the dead time Td for the switching elements Q <b> 1 to Q <b> 4 from the PWM generation unit 50. Here, since the dead time generation unit 70 is provided with an equivalent circuit for each of the switching elements Q1 to Q4, the Q1 gate signal will be described here.

  The dead time generation unit 70 includes an integrator 71, a NOT circuit 72, a comparator 73, and an AND circuit 74. The integrator 71 outputs a value counted up by one for each calculation cycle. The NOT circuit 72 resets the count value of the integrator 71 when the Q1 gate signal on the input side is turned off.

  The comparator 73 outputs a signal that is turned on when the output from the integrator 71 becomes larger than the P-side Td bias value. The AND circuit 74 calculates the logical product of the Q1 gate signal not including the dead time Td and the signal including the dead time Td output from the comparator 73, and outputs a Q1 gate signal including the dead time Td.

  Here, when the P-side Td bias value is 4 μsec, the dead time Td of the Q1 gate signal and the Q3 gate signal output from the AND circuit 74 is 4 μsec, and therefore, from the initial value of the dead time Td that is 5 μsec. It can be seen that the length is shortened.

  Similarly, when the N-side Td bias value is 6 μsec, the dead time Td of the Q2 gate signal and Q4 gate signal output from the AND circuit 74 is 6 μsec, so that the dead time Td of 5 μsec is obtained. It can be seen that it is longer than the initial value.

  That is, for example, when there is a deviation ΔV between the positive side voltage Vc1 and the negative side voltage Vc2, and the positive side voltage Vc1> the negative side voltage Vc2, the dead time Td of the switching elements Q1 and Q3 is shortened, It can be seen that the deviation ΔV approaches zero by increasing the dead time Td of the switching elements Q2 and Q4.

  Next, the simulation results of the power conversion device according to the first embodiment of the present invention will be described with reference to FIGS. Will be described in comparison with the case where the neutral point potential fluctuation suppression control and the flow balance control according to the first embodiment of the present invention are simultaneously applied.

  FIG. 6 is an explanatory diagram showing a simulation result of dead time in the power conversion device to which the neutral point potential fluctuation suppression control and the flow balance control are applied at the same time. Moreover, FIG. 7 is explanatory drawing which shows the simulation result of the dead time in the power converter device which applied simultaneously the neutral point potential fluctuation | variation suppression control and conduction | electrical_flow balance control which concern on Embodiment 1 of this invention.

  6 and 7, in the power conversion device to which the neutral point potential fluctuation suppression control and the current balance control are applied at the same time, the time of the P-side Td and the time of the N-side Td are almost the same. I understand. On the other hand, in the power conversion device to which neutral point potential fluctuation suppression control and conduction balance control according to Embodiment 1 of the present invention are applied simultaneously, the P-side Td bias value is larger than the N-side Td bias value. It can be seen that the time for the P-side Td is longer than the time for the N-side Td.

  FIG. 8 is an explanatory diagram showing a simulation result of a potential difference in a power conversion device to which conventional neutral point potential fluctuation suppression control and flow balance control are applied simultaneously. FIG. 9 is an explanatory diagram showing a simulation result of a potential difference in the power conversion device to which the neutral point potential fluctuation suppression control and the flow balance control according to the first embodiment of the present invention are simultaneously applied.

  In FIG. 8 and FIG. 9, in the power conversion device to which the neutral point potential fluctuation suppression control and the current balance control at the same time are applied simultaneously, the deviation ΔV between the positive side voltage Vc1 and the negative side voltage Vc2 is not balanced. I understand. This is because the neutral point potential fluctuation suppression control and the flow balance control interfere with each other. On the other hand, in the power conversion device to which the neutral point potential fluctuation suppression control and the current balance control according to the first embodiment of the present invention are simultaneously applied, the electric difference ΔV between the positive side voltage Vc1 and the negative side voltage Vc2. Can be seen to be balanced.

As described above, according to the first embodiment, a voltage command calculation unit that calculates a voltage command value for a three-level inverter based on an external frequency command or speed command, and an external frequency command or speed command. Based on the current balance control unit for adding a bias value while switching between positive and negative polarities in a cycle set in advance to the voltage command value, and a switching element of the three-level inverter based on the voltage command value to which the bias value is added Based on the potential difference between the positive side voltage and the negative side voltage, the PWM generation unit that generates the gate signal for the voltage, the voltage detection unit that detects the voltage of the positive side capacitor and the negative side capacitor as the positive side voltage and the negative side voltage, The dead time of the switching element for the gate signal generated by the PWM generator so that the potential difference is small And a dead time setting unit for setting.
Therefore, it is possible to prevent the neutral point potential fluctuation suppression control and the flow balance control from interfering with each other, thereby suppressing the fluctuation of the neutral point potential and ensuring the flow balance.

  1 DC power supply, 2 motor, 10 3-level inverter, 11 positive-side capacitor, 12 negative-side capacitor, 13 3-level inverter for one phase, 14, 15 voltage sensor (voltage detection unit), 20 V / F control unit (voltage command Arithmetic unit), 21 V / F pattern, 22 integrator, 23 three-phase sin table, 24 adder, 30 current balance control unit, 31 bias pattern, 32 multiplier, 40 trapezoidal wave modulation circuit, 41 limit circuit, 50 Generator, 60 neutral point potential fluctuation suppression control unit (dead time setting unit), 61 subtractor, 62 PI controller, 63 upper / lower limiter, 64 adder, 65 upper / lower limiter, 66 subtractor, 67 inverting circuit, 68 Upper / Lower Limiter, 70 Dead Time Generation Unit (Dead Time Setting Unit), 71 Integrator, 72 NOT Circuit, 73 Comparator, 74 AND circuit.

Claims (2)

Connected in series between the positive electrode side and negative electrode side of the DC power source, and has a positive electrode side capacitor and a negative electrode side capacitor with the connection point as a neutral point, and converts DC power from the DC power source into AC power A three-level inverter that supplies the motor with
A voltage command calculation unit that calculates a voltage command value for the three-level inverter based on an external frequency command or speed command;
Based on the frequency command or speed command from the outside, a current balance control unit that adds a bias value while switching between positive and negative polarity at a preset period to the voltage command value,
A PWM generator that generates a gate signal for the switching element of the three-level inverter based on the voltage command value to which the bias value is added;
A voltage detection unit for detecting voltages of the positive side capacitor and the negative side capacitor as a positive side voltage and a negative side voltage;
A dead time setting unit that sets a dead time of the switching element for the gate signal generated by the PWM generation unit so that the potential difference is reduced based on a potential difference between the positive voltage and the negative voltage. When,
The power converter provided with. The power conversion device according to claim 1, wherein the dead time setting unit sets a dead time of the switching element for each phase of the three-level inverter.

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