JP5852544B2 - 3-level power converter - Google Patents

Description

  The present invention relates to a three-level power converter that performs PWM control.

  Conventionally, a power converter that controls output voltage by so-called PWM (pulse width modulation) control, for example, an inverter device, uses a switching element such as an IGBT in its main circuit, and is a pulse that is turned on for a predetermined period for each modulation period. Is output and the average voltage is controlled. When the inverter device reaches the 3rd level, a mode for outputting a zero voltage is added in addition to the positive voltage and the negative voltage, and PWM control of 4 switching elements per arm which is doubled as compared with the 2 level inverter device is performed. Although it is necessary, the basic concept of control remains the same.

  In a three-level inverter device, when the output frequency is low, and therefore the output voltage is low, when a gate control pulse is generated by comparing the voltage reference and the modulation carrier, the pulse width is unacceptable due to the characteristics of the switching element. (Hereinafter referred to as the minimum on-pulse width).

  In order to solve this problem, a so-called rectangular PWM method has been proposed. In this rectangular PWM method, a predetermined bias value is added to the three-phase voltage reference to avoid PWM modulation near zero voltage, and the polarity of the three-phase voltage reference is controlled as the same polarity, and this polarity is switched at a predetermined cycle. Is. (For example, refer to Patent Document 1).

JP-A-5-268773 (page 4-6, FIG. 1)

  The conventional method disclosed in Patent Document 1 prevents a pulse having a width less than the minimum on-pulse width from being generated, and switches this with a predetermined period to balance the energization currents of the positive and negative switching elements. I try to measure it. However, when switching is performed at a predetermined cycle in this way, there is a problem in that potential fluctuations of each phase occur at the time of switching, which causes fluctuations in the neutral point potential. If the potential at the neutral point fluctuates, a so-called common mode current flows, and noise is generated or voltage control is adversely affected.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a three-level power converter that ensures a flow balance and suppresses potential fluctuations at a neutral point.

  In order to achieve the above object, a three-level power converter according to the present invention converts a DC power supplied from a DC power source into a three-phase AC power and supplies it to a load, and the three-level power converter. The converter comprises control means for PWM control, the control means generating means for generating a three-phase basic voltage reference for the three-level power converter, and a phase that is the largest of the three-phase basic voltage references. A maximum value detecting means for detecting the value of the current, a minimum value detecting means for detecting the minimum phase value of the three-phase basic voltage reference, and outputs of the maximum value detecting means and the minimum value detecting means are predetermined. Switching means for alternately switching at a period of, a correction means for subtracting the output of the switching means from each of the three-phase basic voltage references to obtain a three-phase voltage reference, the three-phase voltage reference, and positive and negative sides The three-level power change PWM control means for generating the gate pulse of the switching element constituting the detector, and generating a triangular wave reference carrier for the PWM control means, and generating a negative carrier in the same phase and a positive carrier in the opposite phase And the switching means operates at the timing of the minimum value of the triangular wave reference carrier generated by the carrier generating means.

  According to the present invention, it is possible to provide a three-level power converter that secures a flow balance and suppresses potential fluctuations at a neutral point.

1 is a circuit configuration diagram of a three-level power converter according to Embodiment 1 of the present invention. FIG. 3 is a circuit configuration diagram for one phase of the three-level power converter of the present invention. The figure which shows the waveform of the three-phase voltage reference and the positive side carrier when the minimum value detection circuit is selected. The figure which shows the waveform of the three-phase voltage reference when the maximum value detection circuit is selected, and a negative side carrier. The circuit block diagram of the 3 level power converter device which concerns on Example 2 of this invention. FIG. 4 is an enlarged view of one carrier period in FIG. 3.

  Embodiments of the present invention will be described below with reference to the drawings.

  A three-level power converter according to Embodiment 1 of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1A is a circuit configuration diagram of the three-level power conversion device according to the first embodiment of the present invention.

  The DC power supply 1 supplies three-level DC voltage, and supplies DC power to the three-level power converter 3 via the positive-side smoothing capacitor 2A and the negative-side smoothing capacitor 2B. The three-level power converter 3 converts this DC power into three-phase AC power and drives the AC motor 4. The AC motor 4 is provided with a rotation angle detector 5 for detecting the rotation phase thereof, and a current detector 6 for detecting an input current. The switching elements constituting the three-level power converter 3 are PWM controlled by a gate signal from the control unit 7.

  FIG. 2 is an internal configuration diagram showing one arm of the three-level power converter 3. As shown in FIG. 2, one arm is formed by connecting switching elements Q1, Q2, Q3 and Q4 in series. Flywheel diodes D1, D2, D3, and D4 are connected in antiparallel to switching elements Q1, Q2, Q3, and Q4, respectively. Further, the potential between the switching elements Q1 and Q2 is clamped to the clamp diode Dp, and the potential between the switching elements Q3 and Q4 is clamped to the zero potential by the clamp diode Dn.

  In the above configuration, when the switching elements Q1 and Q2 are on and the switching elements Q3 and Q4 are off, a DC voltage + Ed is supplied to the output terminal, and conversely, the switching elements Q1 and Q2 are off and the switching elements Q3 and Q4 are on. At this time, a DC voltage -Ed is supplied to the output terminal. When the switching elements Q1 and Q4 are off and the switching elements Q2 and Q3 are on, the output terminal voltage is zero.

  Next, the internal configuration of the control unit 7 will be described.

  The phase angle detected by the rotation angle detector 5 is converted into the rotation speed ωr by the differentiator 71, and compared with the given speed reference ωr * and the motor controller 72, which is the main controller, and amplified and compared with the current reference. Become. This current reference is similarly compared and amplified with the output of the current detector 6 inside the motor controller 72 to obtain d-axis and q-axis voltage references ED_R and EQ_R. The phase reference θ1 based on the phase angle detected by the rotation angle detector 5 is used for these two-axis conversions. The d-axis voltage reference ED_R and the q-axis voltage reference EQ_R are converted into three-phase voltage references VU_REF, VV_REF, and VW_REF in a voltage reference conversion unit 73, the details of which will be described later. Then, these three-phase voltage references VU_REF, VV_REF, and VW_REF are compared with the positive carrier and the negative carrier by the PWM control unit 74, and the gate signal of each switching element according to the PMW pattern is generated.

  The carrier generation circuit 75 generates a so-called triangular wave carrier and supplies the triangular wave carrier directly to the PWM controller 74 as a negative carrier. The triangular wave carrier is inverted in polarity by an inverting circuit 76, and a DC component corresponding to the carrier peak value is added by a positive bias adding circuit 77 to obtain a positive carrier. In addition, the carrier generation circuit 75 supplies a carrier synchronization signal to the voltage reference conversion unit 73 for each period of the triangular wave carrier. Here, inverting the positive / negative with the inverting circuit 76 means that the phase is reversed.

  A detailed circuit configuration of the voltage reference converter 73 is shown in FIG. As shown in FIG. 1B, the d-axis voltage reference ED_R and the q-axis voltage reference EQ_R are converted into three-phase basic voltage references EU_R, EV_R, and EW_R by the coordinate conversion / hold circuit 731 using the phase reference θ1. The Here, holding means that the three-phase basic voltage references EU_R, EV_R, and EW_R are held according to the carrier synchronization signal output from the carrier generation circuit 75, and these held values are updated to new values for each carrier period. It is. Here, it is assumed that the carrier synchronization signal is output at the timing of the minimum value (valley) of the triangular carrier output from the carrier generation circuit 75.

  The three-phase basic voltage references EU_R, EV_R, and EW_R are input to the maximum value detection circuit 732 and the minimum value detection circuit 733, and the maximum value and the minimum value of the three-phase basic voltage references EU_R, EV_R, and EW_R are detected. The The detected maximum value and minimum value are input to the switching control circuit 734. The switching control circuit 734 alternates between the maximum value and the minimum value at predetermined intervals, for example, 10 times the carrier period, with reference to the carrier synchronization signal. Output to the switching / subtraction circuit 735. The subtraction circuit 735 subtracts the maximum value or the minimum value output from the switching control circuit 734 from each of the three-phase basic voltage references EU_R, EV_R, and EW_R to obtain three-phase voltage references VU_REF, VV_REF, and VW_REF, respectively.

  The three-phase voltage references VU_REF, VV_REF, and VW_REF obtained as described above are normally compared with the positive and negative carriers from the carrier generation circuit 75 by the PWM modulator 74, and as a result, three-level power conversion is performed. The gate signal of the switching element constituting the device 3 is obtained. An example in which a gate signal is obtained without carrier comparison will be described in the third embodiment.

  The effects of the first embodiment will be described below with reference to FIGS.

  FIG. 3 is a diagram illustrating waveforms of the three-phase voltage references VU_REF, VV_REF, and VW_REF and the positive carrier when the minimum value detection circuit 733 is selected by the switching control circuit 734.

FIG. 4 is a diagram showing waveforms of the three-phase voltage references VU_REF, VV_REF, and VW_REF and the negative carrier when the maximum value detection circuit 732 is selected by the switching control circuit 734. In both figures, a triangular wave indicated by a solid line is a positive or negative carrier, a voltage waveform indicated by a pattern line is a voltage reference VU_REF, a voltage waveform indicated by a solid line is a voltage reference VV_REF, and a voltage waveform indicated by a broken line is a voltage reference VW_REF. It is.

  As shown in FIG. 3 or 4, by correcting the three-phase basic voltage references EU_R, EV_R, and EW_R by the maximum value detection circuit 732 and the minimum value detection circuit 733, the three-phase voltage references VU_REF, VV_REF, and VW_REF are obtained. A so-called two-phase modulation mode is obtained in which one phase is always zero voltage without switching. By doing so, since the polarity of the three-phase voltage reference is controlled to be the same polarity, switching at a low voltage is reduced, and it becomes easy to ensure the minimum on-pulse width. Further, since the outputs of the maximum value detection circuit 732 and the minimum value detection circuit 733 are alternately switched at a predetermined cycle by the switching control circuit 734, the flow rates of the positive side and negative side switching elements can be equalized.

  Next, an explanation will be given focusing on the voltage fluctuation at the neutral point.

First, consider the first carrier period (time T0 to T1) in FIG. Within this one cycle, VV_REF = 0 and VW_REF> VU_REF are always satisfied. Since each of the three-phase voltage references is set to have a potential of + Ed in a period larger than the positive carrier, the switching pattern transition order in this one cycle is
(U, V, W) = (+ Ed, 0, + Ed) => (0, 0, + Ed) => (0, 0, 0) => (0, 0, + Ed) => (+ Ed, 0, + Ed)
It becomes. Here, (U, V, W) represents the potential of each phase when PWM control is performed with the three-phase voltage references VU_REF, VV_REF, and VW_REF, respectively. 0 represents a neutral point potential.

Similarly, consider the first carrier period (time T0 to T1) in FIG. Since the times T0 and T1 in FIG. 4 coincide with T0 and T1 in FIG. 3, respectively, attention should be paid to the fact that in this case, there is no inverting circuit 76 shown in FIG. . In one cycle in FIG. 4, VW_REF = 0 and VU_REF> VV_REF are always satisfied. Since each of the three-phase voltage references is set to −Ed in a period smaller than the negative carrier, the transition order of the switching pattern in this one cycle is
(U, V, W) = (0, 0, 0) => (0, -Ed, 0) => (-Ed, -Ed, 0) => (0, -Ed, 0) => (0, 0, 0) )
It becomes.

Consider the switching operation by the switching control circuit 734 in this state. In FIG. 4, t = T1 is the timing at which the carrier synchronization signal is given to the switching control circuit 734, and it is assumed that the state of FIG. 3 is switched to the state of FIG. 4 at this timing. Then, the transition of the switching pattern by switching is the transition at the last stage in the above transition order,
(U, V, W) = (+ Ed, 0, + Ed) => (0, 0, 0)
It becomes. In this transition, since the two phases of the U phase and the W phase perform switching operations simultaneously, the potential at the neutral point greatly fluctuates.

As a countermeasure, the inversion circuit 76 in FIG. 1 is provided to invert the positive carrier (180 degree phase shift). In this way, the positive carrier in the period from time T0 to T1 in FIG. 3 becomes the maximum value at times T0 and T1, and becomes zero at time (T1−T0) / 2. Therefore, the transition order of the switching pattern in one cycle from time T0 to T1 is
(U, V, W) = (0, 0, 0) => (0, 0, + Ed) => (+ Ed, 0, + Ed) => (0, 0, + Ed) => (0, 0, 0)
It becomes. Therefore, by providing the inverting circuit 76 shown in FIG. 1, the transition of the switching pattern when switching from the state of FIG. 3 to the state of FIG. 4 at the timing of t = T1 is as follows:
(U, V, W) = (0, 0, 0) => (0, 0, 0)
It becomes. Since this transition does not perform a switching operation, the neutral point potential does not fluctuate.

  The above description is made in the first cycle of FIGS. 3 and 4, that is, the period of VV_REF = 0 in FIG. 3 and VW_REF = 0 in FIG. It is clear that it will be established even if it is performed in other periods, since it is kept changing.

  FIG. 5 is a circuit configuration diagram showing the three-level power conversion device according to the second embodiment of the present invention. In the second embodiment, the same parts as those of the circuit configuration of the three-level power conversion device according to the first embodiment of the present invention shown in FIG. The second embodiment is different from the first embodiment in that the inverting circuit 76 is moved from the positive carrier side to the negative carrier side so that the negative carrier is reversed with respect to the reference carrier.

  As described in the first embodiment, the carrier synchronization signal is output at the timing of the minimum value (valley) of the triangular carrier output from the carrier generation circuit 75, and the switching control circuit 734 is maximum at a predetermined interval with reference to the carrier synchronization signal. When the value and the minimum value are alternately switched, as shown in FIG. 1, if the positive carrier is inverted by the inverting circuit 76, the neutral point fluctuation during the switching operation of the switching control circuit 734 is suppressed. .

  The second embodiment corresponds to the case where the carrier synchronization signal is output at the timing of the maximum value (peak) of the triangular carrier output from the carrier generation circuit 75.

In FIG. 3, if the carrier is inverted during the period from T0 to T1, this corresponds to this case.
The order of transition of the switching pattern in one cycle on the positive side is
(U, V, W) = (0, 0, 0) => (0, 0, + Ed) => (+ Ed, 0, + Ed) => (0, 0, + Ed) => (0, 0, 0)
It becomes.

On the other hand, the transition order of the switching pattern in the negative one cycle with reference to FIG.
(U, V, W) = (-Ed, -Ed, 0) => (0, -Ed, 0) => (0, 0, 0) => (0, -Ed, 0) => (-Ed, -Ed , 0)
It becomes. These are transitions when the inverting circuit 76 is not provided in FIG. 1 or FIG.

At this time, the transition of the switching pattern by switching is
(U, V, W) = (0, 0, 0) => ((− Ed, −Ed, 0)
It becomes. In this transition, since the two phases of the U phase and the W phase perform switching operations simultaneously, the potential at the neutral point greatly fluctuates.

On the other hand, when the negative side carrier is inverted by the inverting circuit 76 as shown in FIG.
(U, V, W) = 0, 0, 0) => (0, -Ed, 0) => (-Ed, -Ed, 0) (0, -Ed, 0) => (0, 0, 0)
It becomes. Therefore, the transition of the switching pattern when the switching control circuit 734 performs the switching operation is
(U, V, W) = (0, 0, 0) => (0, 0, 0)
It becomes. Since this transition does not perform a switching operation, the neutral point potential does not fluctuate.

  Hereinafter, the three-level power converter according to Embodiment 3 of the present invention will be described with reference to FIG.

FIG. 6 is an enlarged view of the first carrier 1 period (from T0 to T1) of the waveform shown in FIG. Although overlapping with the description of the first embodiment, each of the three-phase voltage references is set to have a potential of + Ed in a period larger than the positive carrier, so that the switching pattern transition order in this one cycle is
(U, V, W) = (+ Ed, 0, + Ed) => (0, 0, + Ed) => (0, 0, 0) => (0, 0, + Ed) => (+ Ed, 0, + Ed)
It becomes. FIG. 6 shows points of time t1 to t4 at which these switching patterns transition. That is, the transition pattern corresponds to the sections T0 <t <t1, t1 <t <t2, t2 <t <t3, t3 <t <t4, and t4 <t <T1.

  As can be seen from FIG. 6, the transition points t1 to t4 in the above can be obtained by a simple linear calculation as follows. However, T is one period of the carrier, and Vcp is the peak value of the carrier.

t1 = T0 + T (VU_REF) / Vcp
t2 = T0 + T (VW_REF) / Vcp
t3 = T1-T (VW_REF) / Vcp
t4 = T1-T (VU_REF) / Vcp
The above description is for one period from the interval T0 to T1, but the calculation can be performed in the same way for all other periods and also for the period using the negative voltage corresponding to FIG. If the transition points t1 to t4 can be obtained by calculation in this way, the PMW control circuit 74 in FIG. 1 does not need to obtain the t1 to t4 by comparing each phase voltage reference with the carrier, so that the configuration is simplified. . In this case, the PMW control circuit 74 can generate the gate signal of each switching element according to the PMW pattern even if there is no signal of the carrier itself if the information on the carrier cycle T and the peak voltage Vcp is given.

  Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, in the embodiment, the load of the three-level power converter is the AC motor 4, but the load is not limited to the motor. In the embodiment, the motor controller 72 performs the vector control. However, the present invention is not limited to this, and any device that controls the output voltage of the three-level power converter using a three-phase basic voltage reference may be used. For example, normal three-phase voltage control may be used.

  In the first embodiment, the coordinate conversion / hold circuit holds the three-phase basic voltage reference according to the carrier synchronization signal. However, the corrected three-phase voltage reference may be held on the output side of the subtraction circuit 735.

  Furthermore, even if the hold circuit is omitted, the frequency of occurrence of neutral point voltage fluctuations is basically reduced, so the present application is effective. In particular, when the carrier frequency is extremely higher than the three-phase voltage reference frequency, there is no difference in the effect even if the hold circuit is not provided.

1 DC power supply 2A, 2B DC capacitor 3 3-level power converter 4 AC motor 5 rotational position sensor 6 current detector 7 control circuit 71 differentiation circuit 72 motor control unit 73 voltage reference conversion circuit 74 PWM control unit 75 carrier generation circuit 76 inversion Circuit 77 Positive bias addition circuit 731 Coordinate conversion / hold circuit 732 Maximum value detection circuit 733 Minimum value detection circuit 734 Switching control circuit 735 Subtraction circuit

Claims (5)

A three-level power converter that converts DC power supplied from a DC power source into three-phase AC power and supplies the load to a load;
The three-level power converter is configured with control means for PWM control,
The control means includes
Means for generating a three-phase basic voltage reference of the three-level power converter;
Maximum value detecting means for detecting a maximum phase value of the three-phase basic voltage reference;
Minimum value detecting means for detecting a minimum phase value of the three-phase basic voltage reference;
Switching means for alternately switching outputs of the maximum value detecting means and the minimum value detecting means at a predetermined cycle;
Correction means for subtracting the output of the switching means from each of the three-phase basic voltage references to obtain a three-phase voltage reference;
PWM control means for generating gate pulses of switching elements constituting the three-level power converter from the three-phase voltage reference and positive and negative carriers;
A carrier generating means for generating a triangular wave reference carrier for the PWM control means, generating a negative carrier in the same phase as this, and a positive carrier in the opposite phase;
The three-level power converter according to claim 1, wherein the switching means operates at the timing of the minimum value of the triangular wave reference carrier generated by the carrier generating means. A three-level power converter that converts DC power supplied from a DC power source into three-phase AC power and supplies the load to a load;
The three-level power converter is configured with control means for PWM control,
The control means includes
Means for generating a three-phase basic voltage reference of the three-level power converter;
Maximum value detecting means for detecting a maximum phase value of the three-phase basic voltage reference;
Minimum value detecting means for detecting a minimum phase value of the three-phase basic voltage reference;
Switching means for alternately switching outputs of the maximum value detecting means and the minimum value detecting means at a predetermined cycle;
Correction means for subtracting the output of the switching means from each of the three-phase basic voltage references to obtain a three-phase voltage reference;
PWM control means for generating a gate control pulse of a switching element constituting the three-level power converter from the three-phase voltage reference and positive and negative carriers;
A carrier generating means for generating a triangular wave reference carrier for the PWM control means, and generating a positive carrier in the same phase and a negative carrier in the opposite phase;
3. The three-level power converter according to claim 1, wherein the switching means operates at the timing of the maximum value of the triangular wave reference carrier generated by the carrier generating means. The control means includes
The value of each phase of the three-phase basic voltage reference or the three-phase voltage reference is held at every timing of the minimum value of the triangular wave reference carrier generated by the carrier generating means. The three-level power converter described. The control means includes
The value of each phase of the three-phase basic voltage reference or the three-phase voltage reference is held at every timing of the maximum value of the triangular wave reference carrier generated by the carrier generating means. The three-level power converter described. The PWM control means includes
4. The gate control pulse of the switching element constituting the three-level power converter is generated by linear calculation from the period and peak voltage of the three-phase voltage reference and the triangular wave reference carrier. Or the 3 level power converter device of Claim 4.

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