JP2539146B2 - Inverter control method and device using PWM control - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter control device, and more particularly, to an inverter control method and device using PWM control improved so as to secure a minimum on-pulse width and obtain a linear characteristic.

[0002]

2. Description of the Related Art A self-extinguishing switch element such as a GTO (gate turn-off thyristor) is used as an inverter for controlling an output voltage by PWM control. It outputs a voltage and controls the average voltage. In this case, in order to suppress the surge voltage when the switch element is turned off, the capacitor of the snubber circuit is connected in parallel with the switch element. The surge voltage is suppressed by absorbing the surge current in this capacitor. Further, when the switching element is turned on to initialize the voltage of the capacitor, the charge of the capacitor is discharged by maintaining the on state for a certain time (minimum on pulse width: for example, about 100 microseconds).

In this type of conventional device, as shown in FIG. 20 (a), modulating triangular waves (carriers) V _CP and V _CN and a voltage reference V ^*. When the comparator output V _CMP is a voltage reference of a low voltage such that the minimum on-pulse width T ₀ or less, the gate signal V _G for turning on the switching element is set to the minimum on-pulse width T ₀ or less in FIG. The pulse correction unit 180 shown in b) limits the minimum width to T ₀ and outputs it.

[0004]

However, in the above-mentioned conventional device, the reference voltage ± which becomes the minimum ON pulse width T _0.
There is a problem that voltage control cannot be performed in a low voltage region of Vmin or less, and an uncontrollable region occurs. When such an uncontrollable region occurs, the control system becomes unstable and it becomes difficult to perform highly accurate control.

The present invention has been made to solve the above problems, and an object thereof is to ensure a minimum on-pulse width in an inverter that outputs a three-phase AC voltage by PWM control and to provide a total output voltage range of line voltage. In order to provide a control method and device of an inverter using PWM control which outputs a smooth sinusoidal voltage and has no uncontrollable region.

[0006]

In order to achieve the above object, the present invention provides the following control method and device.

(1) The invention according to claim 1 is a control method of a three-phase inverter for outputting a voltage corresponding to a voltage reference for each phase by using PWM control, and the voltage reference for all three phases is a predetermined voltage. When the voltage reference of two or more of the three phases is less than or equal to the predetermined voltage, or when the voltage reference of two of the three phases is less than or equal to twice the predetermined voltage and has a different sign Determine the mode, 1 of 3 phases
When the voltage reference of the phase is equal to or lower than the predetermined voltage and the voltage reference of the other two phases is equal to or less than twice the predetermined voltage and has the same sign, the zero correction mode is determined, and in the normal mode, the voltage reference is used as it is When the mode is determined, the voltage reference of the phase that becomes the maximum voltage in each predetermined cycle is fixed to the predetermined voltage of the opposite polarity or zero voltage, and the voltage reference of the other phase is set to the line voltage.
Correct the voltage so that it does not change from the original value, and when the zero correction mode is determined, fix the voltage reference of the phase that is less than or equal to the predetermined voltage to the predetermined voltage of the same polarity and set the voltage reference of the other phase to the line voltage. Is a control method for correcting so that does not change from the original value.

(2) The invention according to claim 3 is a neutral point clamp type three-phase inverter control method for outputting a voltage according to a voltage reference for each phase by using PWM control.
The first voltage reference of the phase having the largest positive value among the voltage references of the respective phases is fixed to the negative minimum voltage reference or zero, and the voltage references of the other two phases are converted so that the line voltage does not change. Voltage reference conversion method and fixing the voltage reference of the phase with the maximum negative of the voltage references of each phase to the positive minimum voltage reference or zero, and preventing the line voltage from changing the voltage reference of the other two phases. And a second voltage reference conversion method for converting the above into a control method for alternately switching between these two conversion methods.

(3) In the invention corresponding to claim 5, in a control device of a three-phase inverter for outputting a voltage corresponding to a voltage reference for each phase by using PWM control, all the three-phase voltage references are predetermined voltages. When the voltage reference of two or more of the three phases is less than or equal to the predetermined voltage, or when the voltage reference of two of the three phases is less than or equal to twice the predetermined voltage and has a different sign Determine the mode, 1 of 3 phases
Mode determining means for determining a zero correction mode when the phase voltage reference is less than or equal to the predetermined voltage and the other two phase voltage references are less than or equal to twice the predetermined voltage and have the same sign; and the mode determining means determines the normal mode. When the rectangular mode is determined, the voltage reference is output as it is, and when the rectangular mode is determined, the voltage reference of the phase that becomes the maximum voltage is fixed to the predetermined voltage or zero voltage of the opposite polarity and the voltage of the other phase. Reference line voltage
Outputs a voltage reference corrected so that does not change from the original value
And, when it is determined to zero correction mode as line voltage to the voltage reference for other phase fixes the voltage reference phase equal to or less than the predetermined voltage to the predetermined voltage of the same polarity does not change from the original value The control device is provided with voltage reference conversion means for outputting the corrected voltage reference, to secure the minimum on-pulse width, and to output a smooth sine wave voltage in the entire output voltage region of the three-phase line voltage.

(4) The invention according to claim 7 is a neutral point clamp type three-phase inverter controller for outputting a voltage according to a voltage reference for each phase by using PWM control.
Only one phase of the voltage reference of each phase is the minimum on-pulse of the device
When the voltage falls below the minimum voltage standard corresponding to the width, the voltage of this phase
Fixed reference to minimum positive voltage reference or minimum negative voltage reference
Then, set the other two-phase voltage reference so that the line voltage does not change.
A voltage reference conversion means for conversion is provided, and this voltage reference conversion
The control device is capable of controlling the output line voltage even in the vicinity of the zero cross of the voltage reference by the stages .

(5) The invention according to claim 8 is a neutral point clamp type three-phase inverter controller for outputting a voltage according to a voltage reference for each phase by using PWM control.
The first is to convert the polarities of the voltage reference to positive in all three phases or to zero in only one phase and the other two phases to positive without changing the line voltage.
Voltage reference conversion means, second voltage reference conversion means for converting the polarities of the voltage references to all three phases negative or one phase zero and the other two phases negative, and the first and second voltage reference conversion means. means
Which of the two output signals is used as the voltage reference for each phase
The control device is provided with a switching means for alternately switching the output voltage to control the output voltage even in a low voltage region.

(6) The invention according to claim 9 is a neutral point clamp type three-phase inverter controller for outputting a voltage according to a voltage reference for each phase by using PWM control.
First voltage reference conversion means for fixing the voltage reference of the phase having the largest positive value among the voltage references of each phase to the maximum positive reference voltage and converting the voltage references of the other two phases so that the line voltage does not change. And a second voltage reference for fixing the voltage reference of the phase with the maximum negative of the voltage references of each phase to the maximum negative reference voltage and converting the voltage references of the other two phases so that the line voltage does not change. The conversion means and the output signals of the first and second voltage reference conversion means .
Which signal to use as the voltage reference for each phase.
The control device is provided with switching means for switching between each other , and the output voltage can be controlled even in a low voltage region.

[0013]

(1) In the control method of the invention according to claim 1, the normal mode is determined when all the three-phase voltage references exceed a predetermined voltage, and two or more of the three-phase voltage references are the above-mentioned. When the voltage reference is equal to or lower than a predetermined voltage, or when the voltage reference of two of the three phases is less than or equal to twice the predetermined voltage and has a different sign, the rectangular mode is determined, and the voltage reference of one of the three phases is equal to or less than the predetermined voltage. , The other two-phase voltage references are equal to or less than twice the predetermined voltage and have the same sign, the zero correction mode is determined.

When the rectangular mode is determined, the voltage reference of the phase which becomes the maximum voltage in each predetermined cycle is fixed to the predetermined voltage or the zero voltage having the opposite polarity, and when the zero correction mode is determined, the voltage reference is equal to or less than the predetermined voltage. The voltage is fixed to the predetermined voltage having the same polarity as the voltage reference of the phase.

(2) In the control method of the invention according to claim 3 , the voltage reference is equal to or less than the minimum on-pulse width by alternately switching the first voltage reference conversion method and the second voltage reference conversion method. Since no pulse is output and the line voltage is converted to a continuous sine wave voltage reference,
By selecting the switching timing so as not to output a pulse having a width less than the minimum on-pulse width at the time of switching the voltage reference, it is possible to obtain a pulse train in which the line voltage is a continuous sine wave without including the minimum on-pulse.

(3) In the control device of the invention according to claim 5 , the mode determining means determines the normal mode, the rectangular mode, and the zero correction mode in the same manner as in the above control method, and the rectangular mode and the zero mode. When the correction mode is decided,
The voltage reference conversion means corrects the voltage reference in the same manner as in the control method described above. When the neutral point clamp type inverter that outputs three levels of voltage is used as the inverter, the voltage reference correction means fixes the voltage reference of one phase to zero voltage in the rectangular mode and stops switching for a predetermined period.

(4) In the control device of the invention according to claim 7 , it becomes possible to control a low output voltage without outputting a pulse having a width equal to or smaller than the minimum ON pulse width even in the vicinity of the zero cross of the voltage reference. It is possible to control a high output voltage without outputting a pulse with a width less than the minimum off pulse width even in the vicinity of the maximum value of the reference, so the output line voltage from the low voltage region to the high voltage region can be increased without increasing the number of switching times. Can be controlled linearly.

(5) In the control device of the invention according to claim 8 , all the three phases are switched to positive or negative by alternately switching the first voltage reference conversion means and the second voltage conversion means. Since a new voltage reference can be obtained every time, the heat sharing of the switching element for alternately switching between the positive polarity mode and the negative polarity mode can be maintained in balance even in the low voltage region, and the output line voltage can be linearized. Can be controlled. (6) In the control device of the invention according to claim 9 ,
The operation is similar to that of (5) above, but the configuration can be simplified as compared with (5) above.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a control device for an inverter using PWM control according to the present invention.

In FIG. 1, the controller 1 performs three-phase voltage reference V ^* (V _U ^* , V _V ^* , V) by vector control or the like.
_W ^* ) is output to control the inverter (for example, speed control of the electric motor). The mode determination unit 2 determines any one of the normal mode, the rectangular mode, and the zero correction mode according to the algorithm shown in FIG. 2 every time the three-phase voltage reference V ^* is output. That is, the normal mode is selected when the voltage references of all phases are greater than the minimum voltage reference Vmin. The rectangular mode is selected when the voltage reference of two or more of the three phases is less than or equal to the minimum voltage reference Vmin, or when the voltage reference of two of the three phases is less than or equal to twice the minimum voltage reference Vmin and has a different sign. It Further, the zero correction mode is selected when the voltage reference of one of the three phases is equal to or less than the minimum voltage reference Vmin and the voltage reference of the two phases is equal to or less than twice the minimum voltage reference Vmin and the same sign.

After selecting any one of the above-mentioned three types of modes, the mode decision unit 2 further selects one of the detailed modes (Mode = 0 to ± 6) as shown in FIG. select. In the normal mode, Mode = 0 is uniquely selected as shown in FIG.

In the case of the rectangular mode, as shown in FIG.
Sea urchin three-phase voltage reference V^* From the voltage reference
The signal PNFLG whose sign changes every 60 ° in the phase of
obtain. Next, when the signal PNPLG is positive, that is, V^* Is one phase
Only when positive and the other two phases are negative, the maximum positive value among the three phases
Select a voltage reference that This is V_U ^* Then Mode =-
1 and V_V ^* , V_W ^* Then Mode = -2,
-3. When the signal PNFLG is negative, the most negative of the three phases
Select the criterion that gives the maximum value, and this is V_U ^* , V_V ^* , V_W ^*
Then, Mode = 1, 2, 3, respectively.

In the zero correction mode, since only one phase becomes the minimum reference voltage Vmin or less, the phase (V _U ^* ) which becomes Vmin or less as shown in FIG. 3C. , V _V ^* , V _W ^* ) And its polarity determine Mode = (± 4 to ± 6). The voltage reference conversion unit 3 operates as follows in accordance with the normal mode, the rectangular mode, and the zero correction mode as follows ^. To output a new voltage reference V ^** . (A) In the normal mode The mode determination unit 2 selects Mode = 0 and sets the original voltage reference V ^* as the new voltage reference V ^{** .} Is output as is. V ^** (= _VU ^** , _VV ^** , _VW ^** ) = V ^* (V _U ^* , V _V ^* , V _W ^* ) …… (1) (b) In rectangular mode

The mode determining unit 2 selects Mode = ± 1 to ± 3, and fixes the voltage reference of the phase having the maximum voltage as the new voltage reference V ^{** to} the minimum voltage reference voltage Vmin of reverse polarity or zero voltage. At the same time, the voltage is also shifted and output so that the voltage reference line voltage of the other phase does not change from the original value. For example, the U-phase voltage reference V _U ^* Is the largest and is positive, the voltage reference for each phase is corrected as follows. V _U ^** = -Vmin V _V ^** = -Vmin-(V _U ^* -V _V ^* ) V _W ^** = -V min-(V _U ^* -V _W ^* ) (2) Also, V _U ^* If is the most negative, the voltage reference for each phase is corrected as follows. V _U ^** = Vmin V _V ^** = Vmin- (V _U ^* -V _V ^* ) V _W ^** = V min − (V _U ^* -V _W ^* ) (3) The operation waveform in this rectangular mode is shown in FIG. In FIG. 4, V _U , V _V , V _W are phase voltages, V _UV , V _vw , V _WU
Indicates the line voltage.

As shown in FIG. 4, in this embodiment, Modes are switched at intervals of about 60 °, and the respective Modes are switched.
In this range, the voltage reference of the maximum phase is fixed to the minimum reference voltage Vmin of the opposite polarity, and the voltage reference of the other phase is shifted so that the line voltage does not change from the original value. In this rectangular mode, all three phases switch to positive or negative approximately every 60 °, so this is called a 60 ° switching system. (C) In zero correction mode

The mode decision unit 2 selects Mode = ± 4 to ± 6, fixes the voltage reference of the zero-crossing phase as the new voltage reference V ^** to the minimum voltage reference Vmin, and sets the voltage reference of the other phase. The line voltage is shifted and output so that it does not change from the original value. For example, U phase voltage reference V _U ^* When zero crosses from the positive side to the negative side, the voltage reference of each phase is corrected as follows. V _U ^** = Vmin V _V ^** = Vmin- (V _U ^* -V _V ^* ) V _W ^** = V min − (V _U ^* -V _W ^* ) (4) Also, V _U ^* When zero crosses from the negative side to the positive side, the voltage reference of each phase is corrected as follows. V _U ^** = -Vmin V _V ^** = -Vmin-(V _U ^* -V _V ^* ) V _W ^** = -V min-(V _U ^* -V _W ^* ) (5) The operation waveform in this zero correction mode is shown in FIG.

The data latch 7 stores and holds the output V ^** of the voltage reference converter 3, and the switching timing selector 4 receives V ^** obtained from the voltage reference converter 3 and the data clutch 7.
One of the four kinds of switching timings 0X, 1X, 2X, and 3X shown in FIG. 6 is selected from the previous V ^** held at. The timing / carrier comparison unit 5 determines whether or not to update the contents of the data register 7.

The switching timing circuit 6 rewrites the output of the data latch 8 at the timing selected by the switching timing selection section 4, and the comparator 9 outputs V ^** from the data latch 8.
And a carrier are compared and a gate signal is output.

In the above structure, the controller 1, the mode decision unit 2, the voltage reference conversion unit 3, the switching timing selection unit 4, the timing / carrier comparison unit 5, and the data latch 7 are constituted by software, and these are collectively referred to as the CPU 10.
And

Data loading of the CPU 10, that is,
The data input of the track 1 is the valley of the positive carrier shown in FIG.
(0X) and mountain (2X) time, 3 phase voltage reference
V^* Is output.

The switching timing selector 4 switches from the voltage reference V ^** (k) output this time and the previous voltage reference V ^** (k-1) held in the data latch 7 according to the flow chart shown in FIG. Select timing TChgx = 0X to 3X, 2bi
Output as t data (00 to 11).

As shown in FIG. 8, the switching timing circuit 6 compares the switching timing signal TChgx of 2 bits with the carrier phase signal of 2 bits and outputs a signal for rewriting the contents of the data latch 8 when they are equal. It should be noted that the 2-bit carrier phase signal is 0X to 3 by dividing the carrier signal into four equal parts.
It is obtained by distinguishing the phase range of X. Further, L and H in the figure mean a lower digit and an upper digit.

As a result, as shown in FIGS. 9A and 9B, when the sign of the voltage reference V ^** does not change, the voltage reference V ^** is switched at a timing of 0X or 2X, and when the sign changes, 1X or 3X.
It switches at the timing of X. In this case, 0 is given to the 0, 2 identification signal 90 so that 0X and 2X are not distinguished. Further, it is determined that the voltage reference V ^** and the carriers V _CP and V _CN cross each other before and after the switching time point so that switching is not performed.

If the switching timing is fixed to 0X and 2X or 1X and 3X without the above configuration, FIG.
Alternatively, as shown in (d), when the voltage reference V ^** is rewritten (near zero voltage or in the high voltage region), the voltage reference V ^** and the carriers V _CP and V _CN cross each other and the width is less than the minimum on-pulse width. There is a risk of pulsing.

The timing / carrier comparison unit 5 compares the above-mentioned 2-bit switching timing signal Tchgx with the 2-bit carrier phase signal to update the contents of the data latch 7 and always operates to select the correct switching timing.

For example, when the data is loaded at the timing 0a and the switching timing becomes 1a, the output of this signal is performed before the timing 2a. Therefore, the output of the data latch 8 is rewritten between the timings 2a and 0b. I will not be able to. If the next switching timing is selected in this state, a correct result will not be obtained, so the contents of the data clutch are not updated in such a state.

In the case of performing PWM control using the GTO, gives an incomplete OFF gate pulse when the current concentration occurs in a portion of the GTO inside, there is a possibility that the element is damaged, the minimum on
So that does not fall below full pulse width. That is, FIG.
Domain voltage reference V ^** as shown in (e) exceeds the maximum voltage reference ± Vmax close to the maximum value of the carrier T _MP, since if less than or equal to the minimum off pulse width in T _MN occurs, switching
The conversion timing circuit 6 is provided with a function of switching all the regions T _MP and T _MN to the ON state.

That is, in this switching timing circuit 6,
It is a positive start and end points of the maximum voltage output section T _MP as pulse 1/2 of the width of the minimum off pulse width is not outputted at the time of switching the switching in both timing 0X (valley), the maximum negative voltage output section start and end points of T _MN timing 2
I am trying to switch by X (mountain). In this case, 0, 2
The identification signal 90 is set to 1 to distinguish between 0X and 2X, and it is determined whether it is the positive maximum voltage output section or the negative maximum voltage output section.

Rectangular mode of this embodiment (60 ° switching system)
Then, since the phase whose sign changes by converting the voltage reference is the one phase having the maximum positive or negative value, the three-phase voltage reference having the maximum positive or negative in the rectangular mode of the voltage reference conversion unit 3 is negative. Alternatively, instead of the correction of fixing the positive minimum voltage reference Vmin, the voltage reference of the phase having the maximum positive or negative may be fixed to zero.

FIG. 10 shows a waveform example of the voltage reference and the PWM-controlled output voltage (phase voltage and line voltage) in this case. The U-phase voltage reference V _u ^* Voltage reference V _U in which the positive or negative maximum period T _UP or T _UN is corrected
^It is zero in ^** .

The main circuit of the neutral point clamp type inverter is
As shown in FIG. 11, the neutral point voltage is provided by the two capacitors 103 provided between P and N of the DC voltage source 104, and the inverter outputs V _{U to} V _W are clamped to the neutral point voltage. Zero voltage can be output, and P and N potentials of the DC voltage source and three-level output can be obtained. If the neutral point clamp type inverter is used and fixed to zero voltage as described above, the number of times of switching can be greatly reduced and the switching loss is reduced, so that the inverter having improved operation efficiency can be obtained. Further, since the currents flowing through the switch elements alternately balance and flow in the positive direction and the negative direction, the heat generation of the switch elements is balanced and the utilization rate is improved. In addition, the zero-phase correction mode enables the output voltage to be controlled without outputting a pulse with a minimum on-pulse width or less even near the voltage reference zero crossing. It is possible to control high output voltage without outputting,
The line voltage can be linearly controlled over the entire output voltage range from the low voltage range to the high voltage range, and an inverter capable of highly accurate control can be obtained. Next, another embodiment of the present invention will be described.

As a second embodiment, in the mode decision unit 2 shown in FIG. 1, the three-phase voltage reference V ^{* is used.} (V _U ^* ,
V _V ^* , V _W ^* If there is a voltage reference equal to or less than the minimum voltage reference Vmin in (), the zero correction mode is selected. If not, the normal mode is selected.
As shown in (c), Mode (± 4 to ± 6) is determined by the phase of the U, V, and W phases that is Vmin or less and the polarity thereof.

Further, in the voltage reference conversion unit 3, the voltage reference V ^{* is} calculated according to the following equation from the Mode obtained by the mode determination unit ^. Is converted to a new voltage reference V as shown in FIG.
It is designed to output ^** . V _U ^* out of 3 phases If only 0 or more and Vmin or less (Mode = 4) V _U ^** = Vmin V _V ^** = Vmin − (V _U ^* -V _V ^* ) V _W ^** = V min − (V _U ^* -V _W ^* ) (6) Of the three phases, V _U ^* If only the 0 inclusive _{-Vmin (Mode = -4) V U} ** = -Vmin V V ** = -Vmin - (V U * -V _V ^* ) V _W ^** = -V min-(V _U ^* -V _W ^* ) (7) By doing this, although the phase voltage is discontinuous, a continuous sinusoidal voltage reference is obtained for the line voltage, which is the difference in phase voltage.

According to the second embodiment, it is possible to control a low output voltage without outputting a pulse having a width less than the minimum on-pulse width even in the vicinity of the zero cross of the voltage reference, and further, in the vicinity of the maximum value of the voltage reference, the minimum off-pulse. Since it is possible to control high output voltage without outputting pulses less than the width, when applied to a neutral point clamp type inverter, the output line from the stop voltage region to the high voltage region can be increased without increasing the number of switching times. The voltage can be controlled linearly.

As a third embodiment, in the mode decision unit 2 shown in FIG. 1, the three-phase voltage reference V ^{* is used.} (V _U ^* ,
V _V ^* , V _W ^* ), The method of selecting the positive maximum value and the method of selecting the negative maximum value are approximately 60 at the phase of the U-phase voltage reference.
In the method of switching every ° and selecting the positive maximum value, for example, U
If the phase is the positive maximum, Mode = -1. In the method of selecting the negative maximum value, for example, if the U phase is the negative maximum, Mode = 1.
Therefore, the output is divided into six modes.

Further, in the voltage reference conversion unit 3, V _U ^* is obtained from the Mode obtained by the mode determination unit ^. Is the maximum positive value among the three phases, the above (7) is set as Mode = -1.
According to the formula, new voltage references V _U ^** , V _V ^** , V _W ^** are obtained and V _U ^* Is the maximum negative value among the three phases, Mode = 1
As a new voltage reference V _U ^** , V according to the above equation (6)
By obtaining _V ^** and _VW ^** , it is possible to obtain a continuous sinusoidal reference voltage with a line voltage, which is the difference between the phase voltages, although the phase voltage is discontinuous. Even in the third embodiment, the same effect as described above can be obtained. FIG. 12 is a block diagram showing the fourth and fifth embodiments of the present invention.

In FIG. 12, as a fourth embodiment,
The switching timing selection unit 4, the timing / carrier comparison unit 5, and the data clutch 7 in FIG. 1 are omitted, and a timing circuit 6A is provided in place of the switching timing circuit 6, and this timing circuit 6A is defined as the valley (0X) of the positive side carrier. Mountain (2X)
The voltage reference is switched at a fixed timing.

In this case, as described above, at the time of switching the voltage reference, the minimum on-pulse width or 1 / of the minimum off-pulse width is obtained.
Since a pulse having a width of 2 may be generated, when using this embodiment, the minimum voltage reference Vmin is set in advance so that the pulse width is twice the minimum on pulse width and the minimum off pulse width.
And the maximum voltage reference Vmax. According to the fourth embodiment, the line voltage can be linearly controlled in the entire output voltage region in the same manner as described above with a simple structure.

Further, in FIG. 12, as a fifth embodiment, a level detector 11 for discriminating whether the voltage reference V ^** is in the vicinity of zero cross or in the vicinity of the maximum voltage, and the comparator 9 based on the result of the judgment. The same effect can be obtained by providing the pulse correction unit 12 that converts the gate signal output from the device into a gate signal having a fixed minimum on-pulse width or fixed minimum off-pulse width and outputs the converted gate signal.

The algorithm in the rectangular mode of the mode determining section 2 can be implemented by the method shown in FIG. 13, and FIG. 13 (a) is the sixth embodiment and FIG. 13 (b) is the seventh embodiment.
Will be described as an example.

The sixth embodiment is provided with a counter for counting the clock pulses given at every constant period when the rectangular mode is switched, and clears the contents of the counter to zero each time the constant number of clocks (Count) is reached. Flag (PNFLG)
The function of inverting the sign of is provided, and the judgment of Mode = ± 1 to ± 3 is performed in the same manner as described above according to the sign of the PNFLG. This method uses a voltage reference V ^* This is called a rectangular mode time switching method because it changes the sign of PNFLG at regular intervals regardless of the frequency. 20ms using this method
FIG. 14 shows a waveform example when PNFLG is inverted every ec.

According to this sixth embodiment, the voltage reference V ^*
Since the switching elements on the positive side and the negative side conduct at regular intervals regardless of the frequency of, the fluctuation range of the temperature rise of the switching element can be reduced in the low frequency region and the DC output, and the utilization rate can be reduced accordingly. An improved inverter is obtained.

In the seventh embodiment, when the rectangular mode is switched as shown in FIG. 13B, the voltage reference V ^* Is provided with determination means for detecting whether or not the frequency is equal to or higher than a predetermined frequency, and if the frequency is equal to or higher than the predetermined frequency, Mode determination is performed as in FIG.
If not, the Mode determination is performed as in FIG.

Using this method, the voltage reference V ^* FIG. 15 shows an example of a waveform when the frequency is changed from 5 Hz to 10 Hz and the time switching method is switched to the 60 ° switching method in the vicinity of 8.3 Hz.

According to the seventh embodiment, the fluctuation of the temperature rise of the switch element can be suppressed by the time switching method in the low frequency region or the direct current output, and the utilization factor can be improved accordingly. With respect to frequency, the 60 ° switching system can significantly reduce the number of times of switching and enable efficient operation. FIG. 16 shows an eighth aspect of the present invention.
9 is a block diagram showing a case where PWM control is applied to a neutral point clamp type inverter as an embodiment of FIG.

In FIG. 16, the controller 11 performs three-phase voltage reference V ^* by vector control or the like ^. (V _U ^* , V _V
^* , V _W ^* ) Is output to control the inverter (speed control of the electric motor, etc.).

The mode decision unit 12 uses the three-phase voltage reference V ^*. 17 is output, a positive / negative switching signal PNFLG is set to 1 or -1 every P, N switching cycle (T) as shown in FIG. Next, when PNPLG is 1, select the voltage reference with the maximum positive value among the three phases. This is V _U ^* Then, set to mode 1 and V _V ^* , V _W ^* If so, set to modes 2 and 3, respectively. When PNPLG is -1, the negative maximum value is selected from the three phases, which is V _U ^*. ,
V _V ^* , V _W ^* Then, the modes are set to -1, -2 and -3, respectively. In this way, the mode determining unit 12 outputs six types of modes. The voltage reference conversion unit 13 responds to these modes by the following voltage reference V ^*. To output a new voltage reference V ^** . V _U ^* Is the maximum positive value among the three phases (Mode = 1) V _U ^** = Vmax V _V ^** = Vmax − (V _U ^* -V _V ^* ) V _W ^** = V max − (V _U ^* -V _W ^* ) …… (8) V _U ^* Is the maximum negative value among the three phases (Mode =-
1) V _U ^** = -Vmax V _V ^** = -Vmax-(V _U ^* -V _V ^{* _{) V W ** = -Vmax - (}} V U * -V _W ^* ) (9) However, Vmax is the maximum voltage reference. FIG. 18 shows waveform diagrams of the voltage reference, the phase voltage, and the line voltage in the eighth embodiment. In the above configuration, the controller 11, the mode determination unit 12, and the voltage reference conversion unit 13 are configured by software, and these are collectively referred to as the CPU 15. According to the above conversion method, the phase voltage is discontinuous, but a continuous sine wave voltage reference V ^** is output at the line voltage which is the difference between the phase voltages. The comparator 14 compares this voltage reference V ^** with the carrier and outputs an inverter gate signal.

Therefore, in the above configuration, the voltage reference V _U
^* Does not output a pulse having a width equal to or smaller than the minimum on-pulse width in the voltage reference converter 13, and since the line voltage is converted into a voltage-based V ^** that is a continuous sine wave, switching is performed even when the output frequency of the inverter is low. It is possible to control the output line voltage linearly without causing variations in the temperature rise of the element.

As a ninth embodiment, in the configuration shown in FIG. 16, the mode determining unit 12 sets the positive / negative switching signal PNFLG to 1 or -1 for each PN switching period (T) by the timer, and the voltage reference converting unit 13 is set. The voltage reference V ^{* of} each phase of U, V, W shown in the following equation according to PNFLG (V _U ^* , V _V ^* , V
_W ^* 19) by superimposing a constant voltage reference on
As shown in (3), a new voltage reference V ^{** in} which all three phases are switched to positive or negative is obtained every PN switching period (T). When PNFLG = 1 V _U ^** = V _U ^* +1/2 ・ Vmax V _V ^** = V _V ^* +1/2 ・ Vmax V _W ^** = V _W ^* + 1/2 · Vmax ……… (10) When PNFLG = -1 V _U ^** = V _U ^* -1/2 ・ Vmax V _V ^** = V _V ^* -1/2 ・ Vmax V _W ^** = V _W ^* -1 / 2 · Vmax (11) where Vmax is the maximum voltage reference; V _U ^* ≦ 1/2 ・ Vma
x.

According to the ninth embodiment, the structure can be simplified, and even when the output frequency of the inverter is low, the temperature rise of the switching element does not vary even when the output frequency of the inverter is low, and the output line spacing is kept constant. The voltage can be controlled linearly.

[0061]

As described above, according to the present invention, the PW
In an inverter that outputs a three-phase AC voltage by M control, the minimum on-pulse width is ensured, and a smooth sinusoidal voltage is output in the entire output voltage region of the line voltage, and an inverter using PWM control that does not have an uncontrollable region It is possible to provide a control method and device.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining first to third embodiments illustrating a main configuration of an inverter control device using PWM control according to the present invention.

FIG. 2 is a flow chart showing an algorithm for determining a normal mode, a rectangular mode, and a zero correction mode in a mode determining unit of the first embodiment.

FIG. 3 is a flowchart for dividing each of the normal mode, the rectangular mode, and the zero correction mode into subdivided modes.

FIG. 4 is an operation waveform diagram in the rectangular mode of the first embodiment.

FIG. 5 is an operation waveform diagram in the zero correction mode of the first embodiment.

FIG. 6 is a timing chart for explaining the operation of the first embodiment.

FIG. 7 is a flowchart showing the timing determination of the switching timing selection unit in the first embodiment.

FIG. 8 is a specific circuit diagram of a switching timing circuit in the first embodiment.

FIG. 9 is a diagram for explaining the switching timing of the voltage reference V ^** in the first embodiment, where (a) and (b) are the configurations of the first embodiment, and (c) is Switching timing is 0X, 2X, (d) switching timing is 1X, 3X
(E) is the maximum voltage reference ± Vmax
FIG. 5 is a waveform chart showing the timing of switching to the all-on state when the value exceeds the limit.

FIG. 10 is an operation waveform diagram when the voltage reference of the phase having the maximum positive or negative polarity is corrected to zero in the rectangular mode of the first embodiment.

FIG. 11 is a configuration diagram of a main part of a main circuit of a neutral point clamp type inverter.

FIG. 12 is a configuration diagram for explaining fourth and fifth embodiments of the present invention.

FIG. 13 is a diagram showing sixth and seventh embodiments according to the present invention, in which the subdivision mode decision algorithm in the rectangular mode of the mode decision unit of FIGS. 1 and 12 is changed,
Is a flow chart of the sixth embodiment, and (b) is a flow chart of the seventh embodiment.

FIG. 14 is an operation waveform diagram in the rectangular mode of the sixth embodiment.

FIG. 15 is an operation waveform diagram in the rectangular mode of the seventh embodiment.

FIG. 16 is a configuration diagram showing eighth and ninth embodiments of the present invention.

FIG. 17 is a flowchart of a mode determining unit in the eighth and ninth embodiments.

FIG. 18 is a waveform diagram of a voltage reference, a phase voltage reference, and a line voltage reference in the eighth embodiment.

FIG. 19 is a waveform diagram of a voltage reference, a phase voltage reference, and a line voltage reference in the ninth embodiment.

FIG. 20 is a diagram for explaining a conventional inverter control device using PWM control, in which (a) is a main part configuration diagram;
FIG. 6B is a diagram showing an uncontrollable area.

[Explanation of symbols]

1 ... Controller, 2 ... Mead decision unit, 3 ... Voltage reference conversion unit, 4 ... Switching timing selection unit, 5 ... Timing / carrier comparison unit, 6 ... Switching timing circuit,
Data latch, 9 ... Comparator.

Claims (9)

(57) [Claims] 1. A voltage according to a voltage reference is PWM for each phase
In a control method of a three-phase inverter that outputs using control, when all the three-phase voltage references exceed a predetermined voltage, the normal mode is determined, and when two or more of the three-phase voltage references are below the predetermined voltage, or When the voltage reference of two of the three phases is less than or equal to twice the predetermined voltage and has a different sign, a rectangular mode is determined, and the voltage reference of one of the three phases is less than or equal to the predetermined voltage and the voltage reference of the other two phases. Is less than or equal to twice the predetermined voltage and has the same sign, the zero correction mode is determined, when the normal mode is used, the voltage reference is used as it is, and when the rectangular mode is determined, the maximum voltage is determined every predetermined period. The voltage reference is fixed to the specified voltage of reverse polarity or zero voltage, and
Correct the voltage reference so that the line voltage does not change from the original value.
And, when it is determined to zero correction mode as line voltage to the voltage reference for other phase fixes the voltage reference phase equal to or less than the predetermined voltage to the predetermined voltage of the same polarity does not change from the original value A method for controlling an inverter using PWM control, which is characterized in that correction is performed. 2. When the rectangular mode is determined,
The predetermined cycle is a cycle of a constant time when the frequency of the voltage reference is equal to or lower than a predetermined frequency, and the predetermined cycle is a cycle of a constant phase when the frequency of the voltage reference exceeds the predetermined frequency. Inverter control method using the above PWM control. 3. A voltage according to a voltage reference is PWM for each phase
In a control method of a neutral-point clamp type three-phase inverter that outputs using control, the voltage reference of the phase having the largest positive value among the voltage references of each phase is fixed to the negative minimum voltage reference or zero, and another A first voltage reference conversion method for converting the voltage reference of two phases so that the line voltage does not change, and the voltage reference of the phase with the largest negative of the voltage references of each phase is set to the positive minimum voltage reference or zero. A PWM which is fixed and uses a second voltage reference conversion method for converting other two-phase voltage references so that the line voltage does not change, and these two conversion methods are alternately switched. Inverter control method using control. 4. A carry is provided for the timing of switching the voltage reference.
The period of the A signal and phase range obtained by several equal parts, switching
The sign of the voltage reference before switching is different from the sign of the voltage reference after switching.
Switching timing when the same
To select from the different phase ranges
Prevents the voltage reference and carrier from crossing when switching.
The method of controlling an inverter using PWM control according to claim 3, wherein the method is stopped . 5. A voltage according to a voltage reference is PWM for each phase
In a control device for a three-phase inverter that outputs by using control, when all the three-phase voltage references exceed a predetermined voltage, the normal mode is determined, and when two or more of the three-phase voltage references are below the predetermined voltage, or When the voltage reference of two of the three phases is less than or equal to twice the predetermined voltage and has a different sign, a rectangular mode is determined, and the voltage reference of one of the three phases is less than or equal to the predetermined voltage and the voltage reference of the other two phases. Is a voltage equal to or less than twice the predetermined voltage and has the same sign, the mode determining means determines the zero correction mode, and when the mode determining means determines the normal mode, the voltage reference is output as it is, and the rectangular mode is determined. In this case, the voltage reference of the phase that becomes the maximum voltage in every predetermined cycle is fixed to the predetermined voltage or zero voltage of opposite polarity, and
The voltage reference of is corrected so that the line voltage does not change from the original value.
The corrected voltage reference is output, and when the zero correction mode is determined, the voltage reference of the phase that is equal to or lower than the predetermined voltage is fixed to the predetermined voltage of the same polarity, and the voltage reference of the other phase is the original line voltage. A voltage reference conversion unit that outputs a voltage reference corrected so as not to change from the value is provided, a minimum on-pulse width is secured, and a smooth sine wave voltage is output in the entire output voltage region of the three-phase line voltage. An inverter control device using PWM control. 6. The voltage reference conversion means fixes a one-phase voltage reference to zero voltage in a rectangular mode when a neutral point clamp type inverter that outputs three levels of voltage is used as the inverter, for a predetermined period. The inverter control device using PWM control according to claim 5, wherein the switching is stopped only. 7. A voltage according to a voltage reference is PWM for each phase
In a control device for a neutral-point clamp type three-phase inverter that outputs by using control, when only one phase of the voltage references of each phase is less than or equal to the minimum voltage reference corresponding to the minimum on-pulse width of the element, the voltage reference of this phase Is fixed to a positive minimum voltage reference or a negative minimum voltage reference, and voltage reference conversion means for converting other two-phase voltage references so that the line voltage does not change is provided. An inverter control device using PWM control characterized in that the voltage between output lines can be controlled even near zero cross. 8. A voltage according to a voltage reference is PWM for each phase
In the control device of the neutral point clamp type three-phase inverter which outputs by using the control, without changing the line voltage,
Voltage reference polarity is positive in all three phases or zero in only one phase and the other two
First voltage reference conversion means for converting a phase into positive; second voltage reference conversion means for converting all three phases of the voltage reference into negative or only one phase into zero and the other two phases into negative; The present invention is characterized in that the output voltage can be controlled even in a low voltage region by providing switching means for alternately switching which of the output signals of the first and second voltage reference conversion means is adopted as the voltage reference of each phase. An inverter control device using PWM control. 9. A voltage according to a voltage reference is PWM for each phase
In a control device for a neutral-point clamp type three-phase inverter that outputs by using control, the voltage reference of the phase with the largest positive value among the voltage references of each phase is fixed to the maximum positive reference voltage, and the voltage of the other two phases is fixed. First to convert the reference so that the line voltage does not change
Of the voltage reference converting means of each phase, and the voltage reference of the phase having the largest negative value among the voltage references of the respective phases is fixed to the maximum negative reference voltage, and the other 2
Which of the second voltage reference conversion means for converting the phase voltage reference so that the line voltage does not change and the output signal of the first and second voltage reference conversion means is adopted as the voltage reference for each phase. A control device for an inverter using PWM control, characterized in that a switching means for alternately switching between the two is provided, and the output voltage can be controlled even in a low voltage region.