JPH05211776A - Inverter - Google Patents

Abstract

PURPOSE:To make an inexpensive low-speed switching element which is less in steady-state loss usable by switching two of three up-down arm circuits by using the basic frequency of the output of an inverter and controlling the remaining up-down arm circuit by using a frequency higher than the basic frequency of the inverter output. CONSTITUTION:Transistors 1, 3, 8, and 10 are turned on and transistors 2, 4, 7, and 9 are turned off when the output voltage of an inverter is in a positive half-period. On the contrary, the transistors 1, 3, 8, and 10 are turned off and transistors 2, 4, 7, and 9 are turned on when the output voltage of the inverter is in a negative half-period. When transistors 5, 6, 11, and 12 are modulated in pulse width in such a state, an AC output is obtained. Therefore, even when pulse width modulation is performed at a high frequency, no expensive high- speed switching element having a large steady-state conducting loss is required for the semiconductor switching elements of this inverter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention uses a direct current power source having positive and negative electrodes and a midpoint potential electrode of both electrodes for the purpose of reducing harmonic components and increasing output capacity. The present invention relates to a so-called three-level inverter capable of outputting three levels of positive electrode level, negative electrode level, and midpoint electrode level on the side. In the following figures, the same reference numerals indicate the same or corresponding parts.

[0002]

2. Description of the Related Art FIG. 4 shows a main circuit configuration of a conventional single-phase three-level inverter. In the figure, the same output voltage Ed
Are connected in series, where the positive side of one DC power source 25 is at the P point, the negative side of the other DC power source 26 is at the N point, and these two DC power sources 2 are connected.
The connection point (middle point) between 5 and 26 is set as M point. Transistors 1, 5, 6, and 4 are sequentially connected in series between the P point and the N point, and diodes 13, 17, 18, and 16 are sequentially connected in antiparallel to the respective transistors. Similarly, transistors 7, 11, 12, and 10 are sequentially connected in series between points P and N, and diodes 19, 23, 24, and 22 are sequentially connected in antiparallel to the respective transistors.
Furthermore, a diode 14 is provided between the mutual connection point of the transistors 1 and 5 and the M point, a diode 20 is provided between the mutual connection point of the transistors 7 and 11 and the M point, and a mutual connection between the M point and the transistors 6 and 4. Diode 15 between the connection point
However, the diode 21 is connected between the point M and the connection point of the transistors 12 and 10 to form a main circuit. And the mutual connection point of the transistors 5 and 6,
The connection point between the transistors 11 and 12 serves as the output terminal of this inverter, and is connected to the load 28 via the LC filter 27.

Next, the operation of FIG. 4 will be described. FIG. 5 shows the operation waveforms of FIG. Here, FIG. 5A shows the carrier wave 3.
3, 34 and the output waveform signals 35, 36 are shown in relation to each other, and FIG. 5B shows the transistors 1, 4, 5, 6, 7, 10, 11, 12 in order from the top. on/
Off signals 44, 45, 46, 47, 48, 49, 50,
51 and each waveform of the inverter output voltage Vo are shown.

That is, when the inverter output voltage Vo is positive, that is, the output waveform signal 35 is positive and the same signal 36 is negative, the transistor 1 is turned on in the section of (output waveform signal 35)> (carrier wave 33), The transistor 6 is turned on in the excluding section, and (output waveform signal 36) <(carrier wave 34)
The transistor 10 is turned on in the section of 1, and the transistor 11 is turned on in the section other than the section. In this case, the transistors 5 and 12 remain on, and the transistor 4 and
7 is off.

Next, if the inverter output voltage Vo is negative, that is, the output waveform signal 35 is negative and the same signal 36 is positive, the transistor 4 is turned on in the section of (output waveform signal 35) <(carrier wave 34), and the section is in the section. The transistor 5 is turned on in the section other than, and (output waveform signal 36)> (carrier wave 33)
The transistor 7 is turned on in the section of, and the transistor 12 is turned on in the section other than the section. Also in this case, the transistors 6 and 11 remain on, and the transistors 1 and 1
0 remains off.

In other words, when the inverter output Vo is positive, the transistors 5 and 12 are turned on, and the transistors 1 and 6, 11 and 10 are on / off controlled by pulse width modulation, so that the inverter output Vo becomes 0. , + Ed, +
It becomes possible to adjust to 3 levels of 2 Ed. When the inverter output Vo is negative, the transistors 6 and 11 are turned on, and the transistors 5 and 4, 7 and 12 are on / off controlled by pulse width modulation, so that the inverter output Vo is O, -Ed,-. It becomes possible to adjust to 3 levels of 2 Ed. In this way, the single-phase three-level inverter can obtain 5 levels of output of + 2Ed, + EO, -Ed, -2Ed as the output, and output at a lower switching frequency than the normal full bridge inverter. It is possible to reduce harmonics.

[0007]

The conventional three-level inverter shown in FIG. 4 is used as a sine wave output inverter,
If an attempt is made to increase the switching frequency of the semiconductor elements in order to reduce the low-order harmonic components included in the output voltage Vo, in this method of the main circuit configuration, as shown in FIG. 1, 4, 5, 6,
The switching frequency of 7, 10, 11, 12 and the diodes 13 to 24) becomes high, and a high-speed switching device capable of switching at a high frequency is required for all semiconductor elements. However, since a high-speed switching device is generally expensive and has a large steady conduction loss, there are problems that the cost of the whole inverter increases and the efficiency decreases.

Further, the semiconductor device generally requires a subvane circuit in order to protect the device from a jumping voltage generated at the time of its switching, but in the main circuit system of FIG. 4, in particular, it is directly connected to the AC output line of the inverter. The voltage applied to the connected upper and lower arm pairs (transistors 5 and 6, 11 and 12) is not a constant value but changes to O or Ed, and the potential at both ends of each arm also fluctuates. A conventional discharge blocking RCD snubber circuit cannot be used. Therefore, when the charge / discharge type RC snubber circuit is used, there is a problem that a large loss occurs particularly when high frequency switching is performed. Therefore, an object of the present invention is to provide an inverter which is a so-called three-level inverter and which can solve the above problems.

[0009]

In order to solve the above-mentioned problems, an inverter according to claim 1 has a positive electrode (point P) and a negative electrode (N).
Point) and a DC power supply (25, 26, etc.) having a midpoint potential pole (M point) between these two poles, and two upper and lower arms in which switching elements and diodes are connected in antiparallel are connected in series. A circuit is provided, and three upper and lower arm circuits are provided, and a first upper and lower arm circuit (comprising transistors 1 and 2 and diodes 13 and 14) of the three upper and lower arm circuits serves as the positive electrode of the DC power source. Similarly, the second upper and lower arm circuits (comprising transistors 3, 4, diodes 15, 16 etc.) are connected between the midpoint potential pole and the negative pole of the DC power source, and A third upper and lower arm circuit (comprising transistors 5 and 6, diodes 17 and 18) is connected in series between the serial connection point of the arms in the first upper and lower arm circuits and the arm in the second upper and lower arm circuits. Connected between points, the third upper and lower arm circuits N to the series connection point and the AC output terminal of the arms of the upper and lower arm circuits (N is an integer of 2 or more)
In the N-phase output inverter provided individually, the first and second upper and lower arm circuits of each upper and lower arm circuit group perform switching at the fundamental frequency of the inverter output, and the third upper and lower arm circuits Pulse width controlled switching is performed at a frequency higher than the fundamental frequency.

According to a second aspect of the present invention, there is provided an inverter according to the first aspect, wherein the switching elements constituting the third upper and lower arm circuits of the N upper and lower arm circuit groups are the same as the N upper and lower arm circuits. A high-speed switching element (MOSFE) with less switching loss than the switching elements forming the first and second upper and lower arm circuits of the group.
T29-32).

[0011]

The semiconductor (transistor or the like) capable of self-excited switching is added in antiparallel to the arm composed of only the diode connected to the point M in FIG. 4, like the other arms. As the operation of the inverter, the semiconductor (transistor) of the arm directly connected to the points P, M and N of the DC power supply performs on / off control at the same frequency as the fundamental wave of the inverter output, and also the AC output. The arm semiconductor (transistor) directly connected to the line performs on / off control by pulse width modulation of a frequency higher than the fundamental wave. Therefore, it is not necessary to switch all the semiconductor elements at a high frequency even though a 5-level voltage pulse-modulated at a high frequency is obtained at the output of the inverter for reducing the harmonics, and the P point of the DC power supply, The semiconductor element of the arm directly connected to the points M and N can be switched at the same frequency as the fundamental wave of the AC output. Furthermore, the voltage value applied to the arm pair directly connected to the AC output line of the inverter is always Ed, and the switching element of this arm is a general PN collective discharge prevention type with less generated loss than the charge / discharge snubber circuit. The snubber circuit of can be used. As a result, low loss and high efficiency of the inverter can be achieved.

[0012]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a configuration diagram of a single-phase three-level inverter as an embodiment of the invention according to claim 1, and corresponds to FIG. 1 differs from FIG. 4 in that transistors 2, 3, 8 and 9 are respectively connected in antiparallel with diodes 14, 15, 20, and 21 connected to point M.

Next, the operation of FIG. 1 will be described. FIG. 2 shows the operation waveforms of FIG. Here, FIG. 2A is shown in FIG.
Similarly, the relationship between the carrier waves 33, 34 and the output waveform signals 35, 36 is shown in FIG. 2B. Transistors (1, 3, 8, 10), (2, 4, 7,
9), 5, 6, 11, 12 on / off signals 3 respectively
7, 38, 39, 40, 41, 42 and the waveforms of the inverter output voltage Vo are shown.

That is, when the inverter output voltage Vo is positive, that is, when the output waveform signal 35 is positive and the same signal 36 is negative, the transistors 1, 3, 8 and 10 are kept on, 2, 4, 7 ,.
9 remains off. And (output waveform signal 35)>
The transistor 5 is turned on in the section of (carrier wave 33), the transistor 6 is turned on in the section other than the section, and the transistor 11 is turned on in the section of (output waveform signal 36)> (carrier wave 34) and in the section other than the section. The transistor 12 is turned on.

When the inverter output voltage Vo is negative, that is, when the output waveform signal 35 is negative and the signal 36 is positive, the transistors 1, 3, 8, 10 remain off, 2, 4, 7 ,.
9 remains on. And (output waveform signal 35)>
The transistor 5 is turned on in the section of (carrier wave 34), the transistor 6 is turned on in the section other than the section, and the transistor 11 is turned on in the section of (output waveform signal 36)> (carrier wave 33) and in the section other than the section. The transistor 12 is turned on.

In other words, when the inverter is operated as a sine output inverter, the transistors 1, 3, 8 and 10 have the waveform 3 during the positive half cycle of the inverter output voltage Vo.
The transistors 2, 4, 7, 9 are turned on as shown in FIG.
Turns off as shown in waveform 38. At this time, a voltage between points P and M of the DC power supply is applied to the pair of upper and lower arms composed of the transistors 5 and 6. Also, the transistor 1
A voltage between points M and N is applied to the pair of upper and lower arms composed of 1 and 12. In the negative half cycle of the inverter output voltage Vo, on the contrary, the transistors 1, 3, 8 and 10 are turned off,
The transistors 2, 4, 7, 9 are turned on. At this time, a voltage between points M and N of the DC power supply is applied to the upper and lower arm pairs composed of the transistors 5 and 6, and the transistors 11 and
A voltage between points P and M of the DC power supply is applied to the pair of upper and lower arms composed of 12. In this state, the transistors 5, 6, 11 and 12 are connected to the waveforms 39, 40, 41 and 4 respectively.
By performing on / off control by pulse width modulation as shown in Fig. 2, an AC output voltage waveform similar to that in Fig. 5B is obtained as shown in the waveform of the inverter output voltage Vo in Fig. 2B.

FIG. 3 shows an embodiment of the invention according to claim 2. The difference between FIG. 3 and FIG. 1 is that instead of the transistors 5, 6, 11, 12 in FIG. 1, MOSFETs 29, 30,
31 and 32 are used. The operation of the inverter shown in FIG. 3 is the same as that of the inverter shown in FIG.

[0018]

According to the invention of claim 1, all the arms of the three-level inverter using the DC power source having the middle point electrode are constituted by the anti-parallel circuit of the semiconductor switching element and the diode, and the semiconductor of each arm is formed. Among the switching elements, the semiconductor switching element connected to the electrode of the DC power supply is opened and closed at the frequency of the fundamental wave of the AC output voltage, and the semiconductor switching element connected to the AC output terminal is opened at the frequency of PWM modulation higher than the fundamental wave. Since it is configured to be opened and closed, a PN collective discharge prevention snubber circuit with less generated loss can be used even for a semiconductor switching element connected to an AC output line, and further high performance of the device (high speed response, Even when performing pulse width modulation at high frequencies to reduce low-order harmonics, etc. It does not require a large high-speed switching element in constant current loss.

Therefore, in the invention according to claim 2, since only the semiconductor switching element connected to the AC output line is used as the high-speed switching element, it is possible to realize an inexpensive, high-performance and highly efficient three-level inverter.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main circuit as an embodiment of the invention according to claim 1.

FIG. 2 is a waveform diagram for explaining the operation of FIG.

FIG. 3 is a configuration diagram of a main circuit as an embodiment of the invention according to claim 2;

FIG. 4 is a conventional main circuit configuration diagram corresponding to FIG.

5 is a waveform diagram for explaining the operation of FIG.

[Explanation of symbols]

 1 transistor 2 transistor 3 transistor 4 transistor 5 transistor 6 transistor 7 transistor 8 transistor 9 transistor 10 transistor 11 transistor 12 transistor 13 diode 14 diode 15 diode 16 diode 17 diode 18 diode 19 diode 20 diode 21 diode 22 diode 23 diode 25 diode 24 diode Power supply 26 DC power supply 27 LC filter 28 Load 29 MOSFET 30 MOSFET 31 MOSFET 32 MOSFET

Claims (2)

[Claims] 1. An upper and lower arm circuit comprising a positive and negative electrodes and a direct current power source having a midpoint potential pole between the two electrodes, and connecting two arms in which switching elements and diodes are connected in anti-parallel in series. , Three upper and lower arm circuits are provided,
Of the three upper and lower arm circuits, the first upper and lower arm circuits are connected between the positive electrode of the DC power supply and the midpoint potential electrode,
Similarly, a second upper and lower arm circuit is connected between the midpoint potential pole and the negative electrode of the DC power source, and a third upper and lower arm circuit is similarly connected to the series connection point of the arms in the first upper and lower arm circuits and the first and second arm circuits. An upper and lower arm circuit group connected to the series connection point of the arms in the second upper and lower arm circuit, and having the series connection point of the arms in the third upper and lower arm circuit as an AC output terminal.
(N is an integer of 2 or more) N-phase output inverters are provided, and the first and second upper and lower arm circuits in each of the upper and lower arm circuit groups perform switching at the fundamental frequency of the inverter output. An inverter characterized in that the third upper and lower arm circuits perform pulse width controlled switching at a frequency higher than the fundamental frequency. 2. The inverter according to claim 1, wherein N
The switching elements that form the third upper and lower arm circuits of the upper and lower arm circuit groups are smaller in switching loss than the switching elements that are also the first and second upper and lower arm circuits of the N upper and lower arm circuit groups. An inverter characterized by a small number of high-speed switching elements.