JP3179692B2 - PWM control method and apparatus for three-level inverter with reduced switching loss - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a voltage-type three-level inverter used as a control power supply for driving a motor in the fields of general industry and railways, and more particularly to a control device for reducing switching loss. The present invention relates to a PWM control method and apparatus for a three-level inverter that can perform the PWM control.

[0002]

2. Description of the Related Art Three-level inverters are becoming popular mainly as large-capacity, high-voltage inverters, including electric railways. FIG. 2 is a diagram showing a main circuit configuration of the three-level inverter. In the figure, 11 is a DC voltage power supply, 12 is a DC reactor, 12C1 and 12C2 are capacitors of the same capacity, and both ends P and N are DC power supply 11
Are connected to the respective positive and negative terminals. Further, a neutral point terminal O is led out from a connection point between the capacitors 12C1 and 12C2.

[0003] 13u1 to 13u4, 14v1 to 14v4
And 15w1 to 15w4 are U, V, and W phase main switching element groups connected in series between the positive terminal P and the negative terminal N, and are respectively 13D1 to 13D4, 14D in this order.
It has antiparallel diodes D1 to 14D4 and 15D1 to 15D4. Also, 13D5-13D
6, 14D5 to 14D6 and 15D5 to 15D6 have the polarities shown in FIG.
Connection points between 4u1, 15u1 and 13u2, 14u2, 15u2, and main switching elements 13u3, 14u
This is a neutral point clamp diode connected between the neutral point terminal O and the connection point between 3, 15u3 and 13u4, 14u4, 15u4.

The U, V, and W phase potentials shown in FIG. 2 output three types of levels + E, 0, and -E. For example, in the U-phase main switching element group, switching elements 13u1, 1
When 3u2 conducts, + E level is output, and 13u3,
When 13u4 conducts, it goes to the -E level.
When u2 and 13u3 conduct, the level becomes 0. Similarly, the switching elements of each phase conduct two pairs at a time, and U,
Voltages of + E, 0, and -E are generated in the V and W phases.

FIG. 3 is a diagram showing a space voltage vector that can be output by the three-level inverter. FIG. 4 is a diagram showing one section (eg, section S1 in FIG. 3) of FIG. 3 divided into four ranges A1 to A4. It is. In the figure, for example, (0, 1, -1) indicates that the voltages of the U, V, and W phases are (0, + E, -E), respectively. Also, (1,
(1, 1), (0, 0, 0) and (-1, -1, -1) are zero voltage vectors V0 that do not generate an output. As shown in the figure, the three-level inverter can take 3 ³ = 27 kinds of switching states, and can output 19 types of discrete voltage vectors. In the instantaneous space voltage vector control of the three-level inverter, several vectors including the zero voltage vector among the voltage vectors adjacent to the command voltage vector V are selected so that the combined vector matches the command vector V. To control.

[0006]

In the conventional three-phase three-level inverter device, since the range of the command vector V that can be generated by the output voltage vector of the inverter has not been clarified, some of the voltage vectors shown in FIG. 3 are selected. However, when synthesizing a vector that matches the command vector V, the zero voltage vector V0 is frequently used. That is, in FIG.
Regardless of the range of A3 or A4, the zero voltage vector V0 may be used in some cases, causing a problem that the load current ripple increases.

In the conventional three-phase three-level inverter device, the harmonic component is reduced by increasing the switching frequency using the IGBT element.
The switching loss increases as the switching frequency increases, causing a problem that the efficiency of the entire system decreases.

The present invention has been made in consideration of the above-mentioned problems of the prior art, and it is an object of the present invention to reduce switching loss by performing relatively simple calculations and logical decisions. To provide a PWM control method and apparatus for a three-level inverter that can improve the efficiency of the system.

[0009]

First, the principle of the present invention will be described. In FIG. 3 described above, a region of 60 ° sandwiched between two long vectors is defined as one section, and 36
The entire 0 ° space is divided into six sections from section S1 to section S6. From the definition of the vector, the section number n where the command vector V exists can be calculated by the following equation (1). Here, ω is the output frequency of the inverter. n = (ωt mod 60 °) +1 (1)

FIG. 4 shows a state in which one section (for example, section S1) in FIG. 3 is divided into four ranges A1 to A4. In FIG.
With zero voltage vector V0 and two short vectors Vs1, Vs
Short vector (Vs1, Vs2) when generated by s2
Is calculated by the following equation (2). When the command vector V in the range A2 is generated by the intermediate vector Vm and the two short vectors Vs1 and Vs2, the maximum times Tsmax2 and Tsmax3 in which the two short vectors Vs1 and Vs2 can be output are expressed by the following (3)
It is calculated by equation (4).

[0011]

(Equation 1)

When the magnitude of the vector is represented as | V |, the output time Ts of the short vector Vs required to generate the command vector V is calculated by the above equation (5). In the above equations (1) to (5), Tc is a control cycle,
| Vm | is the magnitude of the intermediate vector, and θ is the rotation angle of the vector V shown in FIG. Ts and Tsm in the above equation (5)
By comparing ax1, Tsmax2, and Tsmax3, it is possible to determine in which range the command vector V is. This determination is made as follows.

(A) Command vector V when Ts <Tsmax1
Exists in the range A1 (m = 1: m is a range number in which the command vector V in one section exists). (b) When θ ≦ 30 °, Tsmax1 ≦ Ts <Tsmax2, or when θ> 30 ° and Tsmax1 ≦ Ts <Tsmax3, the command vector V exists in the range A2 (m = 2). (c) Command vector V when θ ≦ 30 ° and Ts ≧ Tsmax2
Exists in the range A3 (m = 3). (d) Command vector V when θ> 30 ° and Ts ≧ Tsmax3
Exists in the range A4 (m = 4).

By the way, when the command vector V is within the above ranges, the following transmission order exists as the transmission order of the space voltage vector shown in FIG. For the sake of simplicity, a case where the voltage vector V is in the section S1 will be described below. When the vector V is in the range A1, there are the following two transmission orders. In the transmission order 1, the U-phase of the inverter is not modulated (the U-phase switching element is not switched) Vu = + 1
The transmission order 2 is a transmission order of Vw = −1 in which the W phase of the inverter is not modulated. T0 is the zero voltage vector V0 (111), (-1-1-1) in each control cycle.
Is the output time of the short vector Vs1 (100), (0-1-1), and Ts2 is the output time of the short vector Vs2 (110), (00-1).

When the vector V is in the range A2, there are the following two transmission orders. The transmission order 3 is such that the U phase of the inverter is not modulated Vu =
The transmission order is +1, and the transmission order 4 is the transmission order of Vw = −1 in which the W phase of the inverter is not modulated. Note that Tm
Is the output time of the intermediate vector Vm (10-1), and Ts1 and Ts2 are the output times of the short vectors Vs1, Vs2 (110) and (00-1).

When the vector V is long and in the range A3, there are the following two transmission orders. The transmission order 5 is such that Vu =
The transmission order is +1, and the transmission order 6 is the transmission order of Vw = −1 in which the W phase of the inverter is not modulated. Note that Tm
Is the output time of the intermediate vector Vm, and Ts1 is the short vector V
The output time of s1, TL1 is the output time of the long vector VL1 (1-1-1).

When the vector V is long and in the range A4, there are the following two transmission orders. The transmission order 7 is such that Vu = the U phase of the inverter is not modulated.
The transmission order is +1, and the transmission order 8 is the transmission order of Vw = −1 in which the W phase of the inverter is not modulated. Note that Tm
Is the output time of the intermediate vector Vm, and TL2 is the long vector V
This is the output time of L2 (11-1).

As described above, when the vector V is in each range A1 to A4 of the section S1, there are two transmission orders each having a non-switching phase. Therefore, by selecting the transmission order having the above-mentioned non-switching phase as the transmission order of the vector output near the peak of a certain phase current, the switching loss can be reduced. The present invention reduces the switching loss based on the above principle.

FIG. 5 is a diagram showing the correspondence between the U-phase current, the voltage fundamental wave, and the space vector shown in FIG. In the figure, S1 to S6 are sections S1 to S shown in FIG.
6, Vu is a U-phase voltage, iu is a U-phase current, and Tc is a control cycle. Further, a to f (range of 120 °) indicate a range in which no switching can be performed. For example, for the U phase, Vu = + 1 can be maintained without switching the U phase in the sections S6 and S1. , Section S3
In S4, Vu = -1 can be maintained without switching.

Therefore, for example, in FIGS.
Switching loss can be reduced by selecting a range of 60 ° near the current peak value in a range in which switching is not actually performed (the black portion in the figure). Where the power factor angle β
When β ≦ 30 °, the above-mentioned non-switching portion (black portion in FIG. 5) can be placed near the peak of the current according to the power factor angle of the load. FIG. 6 shows sections S6 and S1.
FIG. 6 is a diagram showing a relationship between a range where the U-phase of the inverter is not switched and a power factor angle of the load in FIG. If the non-switching range can be selected as shown in the figure, the switching loss can be minimized.

The transmission order in each section in this case is as follows. Section S1: When θ ≦ 30 ° + β, the u phase is not modulated (held at Vu = + 1). When θ> 30 ° + β, the w-phase is not modulated (maintained at Vw = −1). Section S2: The phase w is not modulated when θ ≦ 30 ° + β (Vw = −1 is maintained). The phase v is not modulated when θ> 30 ° + β (Vv = + 1 is maintained). Section S3: The phase v is not modulated when θ ≦ 30 ° + β (Vv = + 1 is maintained). When θ> 30 ° + β, the u phase is not modulated (Vu = −1 is maintained). Section S4: The u phase is not modulated when θ ≦ 30 ° + β (Vu = −1 is maintained). When θ> 30 ° + β, the w-phase is not modulated (maintained at Vw = + 1). Section S5: When θ ≦ 30 ° + β, the w phase is not modulated (Vw = + 1 is maintained). When θ> 30 ° + β, the v phase is not modulated (maintained at Vv = −1). Section S6: The phase v is not modulated when θ ≦ 30 ° + β (Vv = −1 is maintained). When θ> 30 ° + β, the u phase is not modulated (maintained at Vu = + 1).

FIG. 7 is a diagram showing a range where the inverter u-phase is not switched in the sections S6 and S1 when the load power factor angle β> 30 °. When the load power factor angle β> 30 °, the transmission order is distributed as follows. Section S1: The u phase is not modulated (held at Vu = + 1). Section S2: The w-phase is not modulated (held at Vw = −1). Section S3: The v phase is not modulated (held at Vv = + 1). Section S4: The u phase is not modulated (Vu = −1 is maintained). Section S5: The w-phase is not modulated (held at Vw = + 1). Section S6: The v phase is not modulated (Vv = −1 is maintained). In this case, the non-switching range of 60 ° cannot be located at the center (near the peak value) of the corresponding phase current phase.

In order to select the transmission order as described above, it is necessary to make a determination based on the power factor angle β of the load.
The power factor angle β of the load is estimated as follows. FIG. 8 is a diagram showing the principle of estimating the power factor angle β of the load in the present invention.
As shown in the figure, first, the rising and falling timings tA and tB of each output voltage pulse are obtained by the PWM control unit of the control device, and the polarity of the line voltage pulse is calculated and stored.

Next, the polarity of the line voltage pulse calculated this time is compared with the polarity of the line voltage pulse calculated last time. When the polarity is reversed, the rising and falling timings tC and tD of the pulse are stored. And
The time t1 is obtained by the following equation (6) and stored. t1 = (tC-tB) / 2 (6) Also, the time t1 at which the line voltage fundamental wave switches from negative to positive.
Is obtained by the following equation (7) using the above tA and tB. t1 = (tD-tA) / 2 (7) The time t1 obtained as described above is a time at which the line voltage fundamental wave switches between positive and negative. Next, the measured current value is processed, and the time at which the current switches between positive and negative is stored as t2. Then, the power factor angle β is calculated from the following equation (8) from t1 and t2.
Estimate by β = ωt × (t2−t1) −30 ° (8)

As described above, the range in which the vector V exists is determined, and the output time of the vector is calculated. For example, the calculation of the output time of the vector in each transmission order in the section S1 is as follows. In order to generate the command vector V existing in the range A1 of the section S1, the output time of each vector is calculated by the following equations (9) to (11). In order to generate the command vector V existing in the range A2 of the section S1, the output time of each vector is calculated by the following equations (12) to (14).

[0026]

(Equation 2)

In order to generate a command vector V existing in the range A3 of the section S1, the output time of each vector is calculated by the following equation (1).
5) to (17). In order to generate the command vector V existing in the A4 range of the section S1, the output time of each vector is calculated by the following equations (18) to (20).

[0028]

(Equation 3)

The present invention reduces the switching loss of a three-level inverter based on the above principle.
FIG. 1 shows a principle block diagram of the present invention. In FIG. 1, 1 is based on the magnitude | V | of the command vector V and the rotation angle θ.
First means for determining the sections S1 to S6 where the command vector V exists, and the ranges A1 to A4, 2 means for detecting the load current, 3 means for estimating the power factor angle β of the load, Reference numeral 4 denotes fourth means for determining the transmission order and calculating the output time of each vector. 5 is a vector control device, 6 is a voltage type inverter, and 7 is a load such as an induction motor.

Referring to FIG. 1, the present invention solves the above-mentioned problem as follows. (1) A region of 60 ° sandwiched between two long vectors VL in the output space voltage vector of the three-level inverter is defined as one section, and the entire 360 ° space of the vector is divided into six sections from section S1 to section S6. Each section S
For 1 to S6, zero vector V0 and short vector Vs
1, Vs2, short vectors Vs1, Vs2 and intermediate vector Vm
Alternatively, each of the above sections is divided into four ranges A1 to A4 according to the range in which the command vector V that can be generated by the short vectors Vs1, Vs2, the intermediate vector Vm, and the long vectors VL1, VL2 exists. Then, when the command vector is given from the vector control device 5, the first means 1 determines the section S in which the command vector V exists, based on the magnitude | V |
1 to S6 and ranges A1 to A4 are obtained. On the other hand, the load current is detected by the second means, and the power factor angle β of the load is estimated based on the detected load current and the line voltage pulse applied to the load by the third means. Next, the fourth means determines the vicinity of the positive and negative peak values of the load current of each phase according to the section and range where the power factor angle β and the command vector V exist.
In the range of 60 °, the corresponding phase does not switch
The transmission order is determined, the output time of each vector in the transmission order is calculated, and each switching element of the voltage source inverter 6 is switched based on the transmission order and the output time.

(2) In the above (1), the fourth means calculates the transmission order and output time of each vector according to the following (a) to (d). That is, when the command vector V is short, the long vector VL is not used, and when the command vector V is long, the zero vector is not used. (a) The command vector V is in the range A in each section S1 to S6.
If it is 1, the zero vector V0 and the short vector V0
s1 and Vs2 are used. (b) When the command vector V exists in the range A2, the short vectors Vs1 and Vs2 and the intermediate vector Vm are used. (c) When the command vector V exists in the range A3, the short vector Vs1, the intermediate vector Vm, and the long vector VL1 are used. (d) When the command vector V exists in the range A4, the short vector Vs2, the intermediate vector Vm, and the long vector VL2 are used.

(3) In the above (1) and (2), the third means stores the positive / negative switching point of the line voltage pulse as the first time t1, and is detected by the second means. The time when the load current becomes zero is stored as a second time t2,
The power factor angle β of the load is estimated based on the first and second times t1 and t2 and the output frequency of the inverter. According to the first and second aspects of the present invention, the configuration as described in (1) above can reduce the switching loss of the three-level inverter.

According to the third aspect of the present invention, since the configuration is made as in the above (2), the use of the zero vector can be reduced, and the increase in the load current ripple can be avoided. In the invention of claim 4 of the present invention, since the configuration is made as in the above (3), the power factor angle of the load can be accurately estimated.

[0034]

FIG. 9 is a diagram showing a configuration of a control device according to an embodiment of the present invention. In the figure, reference numerals 11 and 12 denote a DC power supply and a DC reactor, and 12C1 and 12C2.
Is an input voltage dividing capacitor, 13, 14, and 15 are three-phase three-level inverter bridges, 10 is a motor as a load, 16
Is a load current detector, 17 is a digital signal processor (hereinafter abbreviated as DSP), and 18, 19, and 20 are microcomputers (MC18, M18, respectively).
Abbreviated as C19, MC20.

The DSP 17 generates a voltage vector command V according to the motor operation command, processes the output of the load current detector 16 in the above-described manner, obtains a time t2 when the load current becomes zero, and outputs the result to the MC 18 Output to
The MC 18 selects the output order of the vectors according to the processing result of the DSP 17, and calculates the output time. MC1
9, MC20 generates a PWM waveform based on the output time calculated by MC18, and outputs a three-phase three-level inverter bridge 13, 14, 1 via a gate drive circuit (not shown).
5 are driven.

FIG. 10 is a flowchart showing the processing in the DSP 17 and the MC 18, and the processing in this embodiment will be described with reference to FIG. In advance, the section of the vector is S
The sections are divided into sections 1 to S6 (section number is n) (step S1), and each section S1 to S6 is divided into ranges A1 to A4 (range number is m) (step S2). First, DS
In P17, a voltage command vector V is generated from the operation result for controlling the motor, and the instantaneous current value detected by the current detector 16 is processed to control the motor, and a time t2 at which the current becomes zero is obtained. It is stored (step S3).
The voltage command vector V and time t2 are set to MC
Transfer to 18.

The MC 18 first calculates the section number n in which the voltage command vector V exists and the corresponding range number m, and determines that the voltage fundamental wave obtained from the output line voltage pulse timing during the previous processing is positive. The power factor angle β of the load is estimated from the time t1 at which the current is switched to the negative and the time t2 at which the current transferred from the DSP 17 becomes zero (step S).
4). Next, the vector transmission order is selected based on the section number n, the range number m, and the power factor angle β (step S5).

Further, in step S6, the output time of each vector is calculated, and at the same time, the output line voltage pulse timing is calculated to determine the positive and negative switching time t1 of the line voltage fundamental wave (this time t1 is Used when processing). The output time is output to MC19 and MC20. MC19 and MC20 generate PWM waveforms,
The switching elements of the level inverter bridges 13, 14, 15 are driven.

[0039]

As described above, according to the present invention, switching is performed within a range of 60 ° at each of the positive and negative central phases of the current for a total of 120 ° for each phase of the inverter during one cycle. Since the non-switching region is provided, when the power factor angle of the load is 30 ° or less, the non-switching region can be located near the center of the load current phase (near the peak value). For this reason, the switching loss can be reduced by 30% or more as compared with the conventional one. Further, since the calculation and the logical judgment are simple, the processing time can be shortened and the time response characteristics of the entire system are not affected.

[Brief description of the drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a three-level inverter.

FIG. 3 is a diagram showing a space vector in a three-level inverter.

FIG. 4 is a diagram showing division of four areas in one section.

FIG. 5 is a diagram showing a range in which inverter switching is not performed.

FIG. 6 is a diagram showing a relationship between a non-switching range and a load power factor angle β.

FIG. 7 is a diagram showing a non-switching range when β> 30 °.

FIG. 8 is a diagram illustrating a principle of estimating a load power factor angle β.

FIG. 9 is a diagram illustrating a configuration of a control device according to an embodiment of the present invention.

FIG. 10 is a flowchart illustrating a process according to the embodiment of the present invention.

[Explanation of symbols]

1 First means for determining the section and range in which the command vector V exists 2 Second means for detecting the load current 3 Third means for estimating the power factor angle β of the load 4 Fourth means for calculating output time 5 Vector control device 6 Voltage source inverter 7 Load such as induction motor 11 DC power supply 12 DC reactor 12C1, 12C2 Input voltage dividing capacitor 13, 14, 15 3 level inverter bridge 10 Motor 16 Load current Detector 17 Digital signal processor (DSP) 18, 19, 20 Microcomputer

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M ⁷ /42-7/98

Claims (4)

(57) [Claims] 1. A 60 ° region sandwiched between two long vectors VL in an output space voltage vector of a three-level inverter is defined as one section, and the entire 360 ° space of the vector is divided into six sections from section S1 to section S6. Further, for each of the sections S1 to S6, the zero vector V0
And the short vector Vs1, Vs2 or the short vector V
s1, Vs2 and intermediate vector Vm, or short vectors Vs1, Vs2 and intermediate vector Vm and long vector VL
Each of the above sections is divided into four ranges A1 to A4 according to the range in which the command vector V that can be generated by 1,
The sections S1 to S6 where the command vector V exists are determined by the magnitude | V | of the command vector V and the rotation angle θ of the command vector.
And the ranges A1 to A4 are determined, the load current is detected, and the load current and the calculated load are calculated.
The power factor angle β of the load by the line voltage pulse applied to
And the positive and negative peaks of the load current of each phase based on the section and range in which the command vector V exists and the power factor angle of the load.
The corresponding phase switches within a 60 ° range
PWM control of a three-level inverter, wherein a transmission order is determined so as not to be performed, an output time of each vector in the determined transmission order is calculated, and each vector is output at the determined transmission time and output time. Method. 2. A 60 ° region sandwiched between two long vectors VL in an output space voltage vector of a three-level inverter is defined as one section, and the entire 360 ° space of the vector is divided into six sections from section S1 to section S6. There is a command vector V that can be generated by the zero vector V0 and the short vectors Vs1, Vs2, or the short vectors Vs1, Vs2 and the intermediate vector Vm, or the short vectors Vs1, Vs2 and the intermediate vector Vm, and the long vectors VL1, VL2. Each of the sections S1 to S6 is divided into four ranges A1 to A4 according to the range, and when a command vector is given from the vector control device, based on the magnitude | V | of the command vector V and the rotation angle θ. , The first means for determining the sections S1 to S6 in which the command vector V exists, and the ranges A1 to A4, Second means for detecting the flow, the the load current detected by the second means, the power factor angle of the load by the line voltage pulses applied to the calculated load β
And positive and negative peak values of the load current of each phase according to a section and a range in which the power factor angle β and the command vector V exist.
In the nearby 60 ° range, the corresponding phase does not switch.
A fourth means for determining the transmission order and calculating the output time of each vector in the transmission order, and outputting each vector in the transmission order and the output time obtained by the fourth means. 3 level inverter PWM control device. 3. The fourth means uses a zero vector V0 and short vectors Vs1 and Vs2 when the command vector V exists in the range A1 in each of the sections S1 to S6, and uses the command vector V in the range A2. If so, the short vector Vs
1, Vs2 and the intermediate vector Vm, and the command vector V
Is used in the range A3, the short vector Vs1, the intermediate vector Vm and the long vector VL1 are used. When the command vector V is in the range A4, the short vector Vs2, the intermediate vector Vm and the long vector are used. 3. The PWM control device for a three-level inverter according to claim 2, wherein the transmission order and output time of each vector are calculated using VL2. The third means stores a positive / negative switching point of the line voltage pulse as a first time t1 and a time at which the load current detected by the second means becomes zero. stored as a second time t2, the basis of the first and second times t1, t2 and the inverter output frequency, according to claim 2 or claim 3, characterized in that estimating the β power factor angle of the load PWM controller for three-level inverter.