JP6575865B2 - 3-level inverter control method and control apparatus - Google Patents

Description

  The present invention relates to a control method and a control device for a three-level inverter that outputs a three-level AC voltage from a DC voltage using a semiconductor switching element.

FIG. 2 shows a main circuit of a general three-level inverter. Here, in order to facilitate understanding, the configuration and operation of one phase (for example, U phase) of the three phases will be described.
In FIG. 2, B ₁ and B ₂ are DC power supplies connected in series, and O is a midpoint. Semiconductor switching elements (hereinafter also simply referred to as switching elements) S _{1 to} S ₄ are connected in series to both ends of the series circuit of the DC power supplies B ₁ and B ₂ , and a connection point between the switching elements S ₁ and S ₂ is connected to each other. A series circuit of diodes D ₁ and D ₂ is connected between the connection points of the switching elements S ₃ and S ₄ .

The midpoint O and the connection point between the diodes D ₁ and D ₂ are connected to maintain the same potential, and the connection point between the switching elements S ₂ and S ₃ serves as a U-phase output terminal. Yes.
Note that the positive potential of the DC power supply B ₁ is E _d , the negative potential of the DC power supply B ₂ is −E _d, and the potential at the midpoint O is 0 [V].

In the three-level inverter configured as described above, the potential of the output terminal U (hereinafter, synonymous with voltage) is 3 of the DC circuit by the operation of the switching elements S _{1 to} S ₄ and the diodes D ₁ and D _2. Two potentials E _d , 0, and −E _d are obtained.
For example, in a state where the switching element _S 1, _{S 2} is turned to the _S 3, _{S 4} are turned off, the output voltage _{E d} becomes (however, the voltage drop of the switching element is ignored), the _S 2, When S ₃ is on and S ₁ and S ₄ are off, the output voltage is 0, and when S ₃ and S ₄ are on and S ₁ and S ₂ are off, The output voltage is −E _d .

Next, FIG. 3 is a circuit diagram showing one phase of a three-level inverter having another configuration. In this circuit, a diode _D 1, _{D 2} are omitted in FIG. 2, between the switching element _S 1, _{S 4} connecting point between the midpoint O, bidirectional switch S consisting of the switching elements _S 2, _{S 3 0} is connected.
The type of output voltage in this prior art is the same as in FIG. 2. For example, if the switching element S ₁ is turned on and S _{2 to} S ₄ are turned off, the output voltage becomes E _d , and S ₂ , S ₂ , if the S ₃ is turned on the _S 1, _{S 4} is turned off, the output voltage is 0, the _{S 4} is turned on the _S 1 to S ₃ are if off, the output voltage -E _d .

  In this way, the three-level inverter can output three levels of voltage (DC high voltage, DC medium voltage, and DC low voltage), so that compared to the two-level inverter, the steep voltage change applied to the load is alleviated. For example, it is known and effective for suppressing a surge voltage when the load is an electric motor.

In addition, there exist some which were described in patent document 1, 2 as a prior art of the control method of a three level inverter.
Patent Document 1 discloses a method of switching a plurality of modulation methods based on a frequency command or an amplitude command of an output voltage command, such as dipolar modulation in a low output voltage region, unipolar modulation in a medium output voltage region, and overmodulation thereafter. Is described.
Patent Document 2 discloses a control method for selecting a plurality of output voltage vectors suitable for an output voltage command using an instantaneous space vector and sequentially outputting them in order to suppress common mode voltage, It has also been suggested that the voltage vector transition so that the number of switching times does not increase more than necessary.

The conventional technique described in Patent Document 1 switches various modulation schemes. In unipolar modulation, when the output voltage command is positive, it is between E _d and 0 of the DC circuit per switching period. switching occurs, when the output voltage command is negative, switching occurs between 0 and -E _d per switching cycle. That is, since switching occurs twice for each phase (one switching element changes from off to on and then returns from on to off twice), the total switching for the three phases is a total of six times. Number of times.
On the other hand, in the case of dipolar modulation, the number of times of switching further increases in a low output region, and there is a problem that the efficiency of the apparatus is reduced due to switching loss.

  Further, according to the conventional technique described in Patent Document 2, the number of times of switching can be reduced depending on the order of transition of a plurality of selected output voltage vectors. However, since it is difficult to accurately manage the time ratio of each voltage vector using an inexpensive counter such as a microcomputer, a high-performance and expensive arithmetic device is required, which may increase the cost. is there.

  In view of these points, the applicant reduced the number of switching by reducing the number of switching for Patent Document 1, and reduced the number of patents by using a counter such as an inexpensive microcomputer. An application has already been filed for a control method and a control apparatus for a three-level inverter that enables cost reduction (Japanese Patent Application No. 2014-166375).

The outline of the invention related to Japanese Patent Application No. 2014-166375 (referred to as the prior application) will be described below with reference to FIGS.
FIG. 4 is a functional block diagram showing a control device according to the prior application, and is configured by hardware and software of a microcomputer system.

In FIG. 4, for example, three-phase output voltage commands v _u ^* , v _v ^* , v _w ^* (see FIG. 5) calculated from a frequency command or the like are input to the maximum / intermediate / minimum voltage command calculation means 10. Has been. The intermediate phase selecting means 20 selects a voltage command having an intermediate value among the voltage commands v _u ^* , v _v ^* , v _w ^* as the intermediate voltage command v _mid ^* .
In addition, the maximum / intermediate / minimum voltage command calculation means 10 has the voltage commands v _u ^* , v _v ^* , v _w ^* according to Table 1 when one period of the voltage command is set to the intervals 1 to 6 as shown in FIG. _{Are assigned} to the maximum, intermediate, and minimum voltage commands v _max , v _mid , and v _min . Here, the maximum, intermediate, and minimum voltages are synonymous with DC high voltage, DC medium voltage, and DC low voltage.

When the section is set as shown in FIG. 5, the intermediate voltage command v _mid is repeated in the order of v _v ^* → v _u ^* → v _w ^* as apparent from Table 1. Here, when each voltage command is corrected so that the intermediate voltage command is always 0, the corrected voltage commands v _max ^* , v _mid ^* , and v _min ^* are expressed by Equation 1.
The maximum / intermediate / minimum voltage command calculation means 10 in FIG. 4 corrects the above-described maximum / intermediate / minimum voltage commands v _max , v _mid , and v _{min according} to Equation 1 respectively, and v _max ^* , v _mid ^* , and v _min Output as ^* .

FIG. 6 shows the voltage commands v _max ^* , v _mid ^* , and v _min ^* corrected by Equation 1 as v _u0 , v _v0 , and v _w0 .
For example, in section 1, v _u0 is output as v _max ^* , v _v0 is output as v _mid ^* (= 0), and v _w0 is output as v _min ^* . Since v _max ^* = v _max −v _{mid according} to Equation 1, v _u0 is the difference between the maximum voltage v _u ^* and the intermediate voltage v _v ^* in section 1 in FIG. Since v _min ^* = v _min −v _{mid according} to Equation 1, v _w0 is the difference between the minimum voltage v _w ^* and the intermediate voltage v _v ^* in section 1.
In section _{2, v max} ^* _{v v0} is output ^{_{as, v mid * (= 0)}} v u0 is output _{as, v min} ^* as _{v w0} is output. Similarly, for the sections 3 to 6, any one of v _u0 , v _v0 , and v _w0 is output as the corrected voltage commands v _max ^* , v _mid ^* , and v _min ^* , respectively.

FIG. 6 shows a zero-phase voltage command 3w in addition to the phase voltage commands v _u0 , v _v0 , and v _w0 . However, since the zero-phase voltage command 3w is canceled when considering the line voltage, if the control is performed according to the line voltage command synthesized from the voltage command of each phase, the control of the output voltage is not affected.

但し、λ_ｍａｘ ^＊，λ_ｍｉｎ ^＊は０から１までの値である。 Returning to FIG. 4, the on-time ratio calculation means 30 to which the corrected voltage commands v _max ^* , v _mid ^* , v _min ^* are inputted is the magnitude of the positive and negative DC voltages E _d , −E _d of the DC circuit. Thus, the time ratios λ _max ^* and λ _min ^{* at} which the switching element is turned on per switching cycle are obtained by Equation 2.

However, λ _max ^* and λ _min ^* are values from 0 to 1.

Here, the on-time ratio in one switching period of each phase switching element is considered.
In section 1, since the U-phase voltage command v _u ^* is the maximum value, the on-time ratio of the switching element S _{1 in} FIG. 3 is λ _max ^* . Furthermore, since during the outputs 0 to the switching element _{S 1} is turned off, the on time ratio of the _{S 3} becomes (1-λ _max ^*). Further, since the S ₂ is not shorting the DC power supply B ₂ also be turned on, turned on as the reflux mode, the S ₄ is turned off does not output the voltage (-E _d).
Therefore, the ON time of each switching element _S 1 to S ₄ for the maximum voltage command ratio _λ maxS1 ~λ maxS4 becomes Equation 3.

数式４から明らかように、中間電圧指令に応じた電圧を出力するために、スイッチング素子Ｓ_１〜Ｓ_４はオン状態またはオフ状態で固定され、１スイッチング周期ではスイッチングを行わない。 Next, in section 1, the on-time ratios λ _{midS1 to} λ _midS4 of the switching elements S _{1 to} S ₄ of the intermediate voltage command (V-phase voltage command v _v ^* ) are _{expressed as} S ₂ , S ₃ is turned on, and S ₁ and S ₄ are turned off.

As can be seen from Equation 4, in order to output a voltage corresponding to the intermediate voltage command, the switching elements S _{1 to} S ₄ are fixed in the on state or the off state, and switching is not performed in one switching cycle.

In section 1, since the W-phase voltage command v _w ^* is the minimum value, the on-time ratio of the switching element S _{4 in} FIG. 3 is λ _min ^* . At this time, the _{S 1} because it does not output the voltage _{E d} of DC power supply _{B 1,} off. The _{S 2} is, the _{S 4} because outputs a 0 when the off, a 1-λ _min ^*. Furthermore, the S _3, since never even been turned to short-circuit the DC power supply B _1, is turned on as a reflux mode.
Therefore, the on-time ratio of each of the switching elements S _{1 to} S ₄ with respect to the minimum voltage command is expressed by Equation 5.

ON time ratio calculating means 30 in FIG. 4, the on time ratio λ _max ^*, λ _mid ^*, as ^{_{λ min *, λ maxS1 *,}} λ midS2 *, and outputs _λ minS4 ^*, respectively.
Each phase-on-time ratio calculating means 40 calculates λ _max ^* , λ _mid ^* , λ _min ^* (λ _maxS1 , λ _midS2 , λ _minS4 ) of Equation 3, Equation 4, and Equation 5 obtained by using the section 1 as an example. Inverse conversion of Table 1 is performed to convert the on-time ratios λ _u , λ _v , and λ _w of the voltage commands for the U, V, and W phases.

The triangular wave comparison means 50 as the carrier comparison means compares each phase voltage command v _u0 , v _v0 , v _w0 based on the on-time ratios λ _u , λ _v , λ _w with a triangular wave, and the switching element of the three-phase each phase. Obtain an on / off command. Incidentally, in FIG. 4, _S u1 _{to S u4} outputted from the triangular wave comparator 50 is on-off command for the switching elements of the U-phase (corresponding to _S 1 to S ₄ in FIG. _{3), S} v1 _{~S v4} , S _{w1 to} S _w4 are on / off commands for four switching elements of V phase and W phase, not shown.

FIG. 7A shows the carriers and the phase voltage commands v _u0 , v _v0 , and v _w0 in section 1, and FIGS. 7B, 7 _</ b _> C, and 7 _</ b _> D show the ON / OFF states of the switching elements of each phase. The off commands S _{u1 to} S _u4 , S _{v1 to} S _v4 , S _{w1 to} S _w4 , that is, the on / off states are shown. In the following description, the on / off commands S _{u1 to} S _u4 , S _{v1 to} S _v4 , and S _{w1 to} S _w4 are also used as reference numerals for the switching elements.

A triangular wave carrier moving between 0 and 1 is created by an up / down counter such as a microcomputer as shown in FIG. This carrier increases from 0, turns back at 1, and returns to 0 is one switching cycle.
Also, the triangular wave comparison means 50 of FIG. 4 is configured using a comparator built in a microcomputer or the like, and as shown in FIG. 7A, each phase voltage command v _u0 , Compare v _v0 and v _w0 with the carrier. For one carrier, when the voltage command is large, it is 1 (on), and when it is small, it is 0 (off). As shown in FIGS. 7B, 7C, and 7D, each phase is turned on / off. Create a signal.

In FIG. 7B, since the U-phase voltage command v _u0 is the maximum value in the section 1, switching is performed twice between the switching elements S _u1 and S _u3 (for example, S _u1 is turned on). → Off → On), and S _u2 and S _u4 are not switched (on / off).
In FIG. 7C, in the section 1, the V-phase voltage command v _v0 is an intermediate value, the switching elements S _v2 and S _v3 are on, and the S _v1 and S _v4 are off. In FIG. 7C, only the characteristic lines of S _v3 and S _v4 are shown in order to avoid the overlapping of characteristic lines, but in reality, S _v3 and S _v2 overlap, and S _v4 and S _v1 are overlapping. Thus, in the V phase, all the switching elements S _{v1 to} S _v4 are not switched, and the number of times of switching in one switching cycle is zero.
In FIG. 7D, since the W-phase voltage command v _v0 is the minimum value in the section 1, switching is performed twice between the switching elements S _w2 and S _w4 , and the same S _w1 , S _w3. Is not switching.

As described above, according to the prior invention, the three-level inverter can be controlled by switching four times per switching period. The carriers for determining the on-time ratios λ _u , λ _v , and λ _w of each phase can be easily generated using a general microcomputer, eliminating the need for a high-performance and expensive arithmetic unit and reducing the cost. An increase can be avoided.

JP 2007-282484 A (paragraphs [0008] to [0028], FIGS. 1 to 3 etc.) JP 2010-206931 A (paragraphs [0027] to [0036], FIGS. 1 to 3 etc.)

In FIG. 3 described above, from the state where the switching element S ₁ is turned on, the S _{2 to} S ₄ are turned off and the voltage _Ed is output, the S ₂ and S ₃ are turned on, and the S ₁ and S ₄ are turned on. when switching the output voltage as an off state of 0, it is necessary to turn on the S ₃ is turned off the same S _1. However, if there are variations in the timing of the on-off switching element S _1, S _3, they may inadvertently turned on simultaneously, as a result of DC power supply B ₁ is short-circuited via a switching element S _1, S ₃ , S ₁ and S ₃ may be destroyed by overcurrent.

Similarly, when the switching elements S ₂ and S ₃ are on, the S ₁ and S ₄ are off, and the output voltage is 0, the output voltage is set by turning on the S ₄ and turning off the S _{1 to} S _3. even when switching to -E _d, the _S 2, _{S 4} are short-circuited the DC power source _{B 2} and turned on at the same time.
Accordingly, it is necessary to provide a delay time (on-delay time) during the on-operation so that the switching elements S ₁ , S ₃ or S ₂ , S ₄ are not simultaneously turned on.

  Thus, if the on-delay time is provided, it is possible to prevent a power supply short-circuit due to simultaneous on-time, but an error occurs between the output voltage command and the actual output voltage by changing the on-time of the switching element. Due to this output voltage error, when the inverter drives the electric motor, torque ripple, rotation unevenness, etc. occur, leading to deterioration of control performance and increasing loss.

In a general two-level inverter, the output voltage error can be reduced by correcting the voltage command using a correction value based on the ratio between the on-delay time and the switching period.
However, in the prior invention intended for a three-level inverter that requires control of an intermediate voltage, the output voltage error reduction technique in the two-level inverter cannot be simply applied.

  SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a control method and a control apparatus for a three-level inverter that improves the control performance by reducing the output voltage error caused by the on-delay time.

In order to solve the above-described problem, a control method according to claim 1 includes a plurality of switching elements connected between a DC circuit having a high voltage point, a medium voltage point, and a low voltage point and an AC output terminal for one phase. 3 phase inverters that can output three voltage levels consisting of DC high voltage, DC medium voltage, and DC low voltage are provided for three phases, and the switching element is operated according to the three-phase output voltage command. Is a control method of a three-level inverter that outputs a three-phase AC voltage,
Per switching period of the switching element,
A three-level inverter for the first phase turns on and off the switching element connected to the high voltage point and the switching element connected to the medium voltage point to output a DC high voltage and a DC medium voltage, A three-level inverter for two phases fixes a switching element connected to the medium voltage point in an ON state and outputs a DC medium voltage, and a three-level inverter for a third phase connects to the medium voltage point In a control method for calculating an on-time ratio of each switching element so as to output a DC intermediate voltage and a DC low voltage by turning on and off the switching element connected to the low voltage point and outputting a DC medium voltage and a DC low voltage,
A three-level inverter for the first phase and the third phase using the ratio of the on-delay time and switching period set for preventing power supply short-circuiting by simultaneously turning on a plurality of switching elements and the polarity of the load current On-delay correction values for the switching elements are calculated, and the on-time ratios for the switching elements of the three-level inverters for the first phase and the third phase are respectively corrected by the on-delay correction values.

The control device according to claim 2 turns on and off a plurality of switching elements connected between a DC circuit having a high voltage point, a medium voltage point, and a low voltage point and an AC output terminal for one phase. A three-phase inverter that can output three voltage levels consisting of a high voltage, a medium DC voltage, and a low DC voltage is provided for three phases, and a three-phase AC voltage is output by operating the switching element according to a three-phase output voltage command. A three-level inverter control device,
Per switching period of the switching element,
A three-level inverter for the first phase turns on and off the switching element connected to the high voltage point and the switching element connected to the medium voltage point to output a DC high voltage and a DC medium voltage, A three-level inverter for two phases fixes a switching element connected to the medium voltage point in an ON state and outputs a DC medium voltage, and a three-level inverter for a third phase connects to the medium voltage point In a control device for calculating the on-time ratio of each switching element so as to output a DC medium voltage and a DC low voltage by turning on and off the switching element connected to the low voltage point and outputting a DC medium voltage and a DC low voltage,
Intermediate phase selection means for selecting a voltage command having an intermediate amplitude from the three-phase output voltage commands in a predetermined section;
The three-phase output voltage command is divided into the maximum voltage command, intermediate voltage command, and minimum voltage command according to the amplitude, and the maximum voltage command, intermediate voltage command, and minimum voltage command are set so that the intermediate voltage command is always zero. Maximum / intermediate / minimum voltage command calculation means to correct and output,
On-time with respect to the switching element of the three-level inverter for three phases to output the voltage according to the corrected maximum voltage command / intermediate voltage command / minimum voltage command using the DC high voltage and DC low voltage An on-time ratio calculating means for calculating a ratio;
A three-level inverter for the first phase and the third phase using the ratio of the on-delay time and switching period set for preventing power supply short-circuiting by simultaneously turning on a plurality of switching elements and the polarity of the load current Correction value calculation means for calculating an on-delay correction value for each of the switching elements,
On-delay correction for correcting the on-time ratios for the switching elements of the three-level inverters for the first phase and the third phase among the on-time ratios output from the on-time ratio calculation means, respectively, by the on-delay correction value Means.

  According to the present invention, by correcting the output voltage error due to the on-delay time, it is possible to exhibit high control performance by preventing the occurrence of torque ripple or rotation unevenness when driving the electric motor. Further, similarly to the prior invention, it is possible to reduce the number of times of switching to reduce the loss and to improve the efficiency.

It is a block diagram of the control apparatus of the 3 level inverter which concerns on embodiment of this invention. It is a circuit diagram which shows one phase part of a 3 level inverter. It is a circuit diagram which shows one phase part of the 3 level inverter of another structure. It is a functional block diagram of a control device concerning a prior application. It is a waveform diagram of three-phase output voltage commands v _u ^* , v _v ^* , v _w ^{* in} the prior invention. It is a waveform diagram of corrected voltage commands v _max ^* , v _mid ^* , v _min ^* (v _u0 , v _v0 , v _w0 ) in the prior application invention. In the prior application invention, it is explanatory drawing of the carrier of each section, each phase voltage command (Fig.7 (a)), and the ON / OFF state (FIGS.7 (b)-(d)) of the switching element of each phase. .

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram of a control device according to this embodiment. Here, a case where the three-level inverter of FIG. 3 is controlled will be described as an example. 1, components having the same functions as those shown in FIG. 4 are given the same reference numerals.

In FIG. 1, three-phase output voltage commands v _u ^* , v _v ^* , v _w ^* (see FIG. 5) are input to the maximum / intermediate / minimum voltage command calculation means 10, and the intermediate phase selection means 20 Among the voltage commands v _u ^* , v _v ^* , and v _w ^* , a voltage command having an intermediate value is selected as the intermediate voltage command v _mid ^* .
As shown in FIG. 5, the maximum / intermediate / minimum voltage command calculation means 10 determines that the voltage command v _u ^* , v _v ^* , v _w ^* _{Is assigned} to the maximum, intermediate, and minimum voltage commands v _max , v _mid , and v _min . Here, the maximum, intermediate, and minimum voltages are synonymous with the DC high voltage, DC medium voltage, and DC low voltage in the claims.

The intermediate voltage command v _mid ^* selected from the voltage commands v _u ^* , v _v ^* , and v _w ^* by the intermediate phase selection means 20 is the maximum / intermediate / minimum voltage command calculation means 10 and the maximum / intermediate / minimum phase. This is input to the current classification means 60.
The maximum / intermediate / minimum voltage command calculation means 10 corrects each voltage command v _max , v _mid , v _{min according} to the above-described equation 1 so that the intermediate voltage command v _mid ^* is always 0, and the corrected voltage command Outputs v _max ^* , v _mid ^* , and v _min ^* . The on-time ratio calculating means 30 obtains the time ratios λ _max ^* and λ _min ^{* at} which the switching element is turned on per switching cycle by the equation 2, and further calculates the on-time ratio by calculating the equations 3 to 5. ^{_{λ max *, λ mid *,}} λ min * as _λ maxS1 ^*, λ midS2 ^*, the output _λ minS4 ^*, respectively.

On the other hand, the maximum / intermediate / minimum phase current classifying means 60 uses the detected current values i _u , i _v , i _w of each phase based on the intermediate voltage command v _mid ^* and the maximum voltage phase current i _max and the minimum voltage. The current is classified into the phase current i _min .
That is, according to Table 1 described above, the phases that become the maximum voltage command and the minimum voltage command are specified in accordance with the intermediate voltage command v _mid ^* in each section shown in FIG. For example, in section 1 of Table 1 and FIG. 5, the intermediate voltage command v _mid ^* is the V phase, the maximum voltage command v _max ^* is the U phase, and the minimum voltage command v _min ^* is the W phase. The current detection value i _u of the U phase is selected as the current i _max of the current phase, and the current detection value i _w of the W phase is selected as the current i _min of the minimum voltage phase.

As described above, the current i _max , i _min is determined by classifying the current detection values i _u , i _v , i _w of each phase according to the maximum, middle, and minimum of the voltage command. Is not constant but depends on the load power factor, and is not the maximum, middle, or minimum of the current detection value, but a correction value i _maxcomp, which will be described later, based on currents i _max and i _min focusing on the magnitude relation of the voltage command. , I _mincomp .

The currents (load currents) i _max and i _min determined by the maximum / intermediate / minimum phase current classifying means 60 are input to the correction value calculating means 70. In this correction value calculation means 70, using the current i _max , i _min , the on delay time T _d set by the timer, and the switching period T _s , the correction value λ _maxcmp , λ _mincmp is calculated.
In Expression 6, sign (i _max ) and sign (i _min ) indicate the polarities of i _max and i _min , respectively, and are “1” if the polarity is positive and “−1” if the polarity is negative. Accordingly, the correction values λ _maxcmp and λ _mincmp take a value of T _d / T _s or (−T _d / T _s ) depending on the polarity of the load current.

Here, the correction value λ _maxcmp is a correction value for the on-time ratio λ _maxS1 ^* of the maximum voltage command (for example, the U-phase voltage command v _u ^{* in} section 1 in FIG. 5), and the correction value λ _mincmp is the minimum This is a correction value for the on-time ratio λ _minS4 ^* of the voltage command (in section 1 in FIG. 5, the W-phase voltage command v _w ^* ).
Thus the maximum voltage command of the on-time ratio _λ maxS1 ^* and the minimum voltage command of the on-time ratio _λ minS4 ^* subject to the correction, the intermediate voltage command (in the interval 1 in FIG. 5, V-phase voltage command _v ^{v *)} The _{reason why the} on-time ratio λ _midS2 ^* is not corrected is that the three-level inverter for one phase corresponding to the intermediate voltage phase does not originally perform switching, so that correction is not necessary.

ON-delay correction unit 80, as well as obtaining a correction value lambda _Maxcmp ON time ratio _λ maxS1 ^** by correcting the on-time of the maximum voltage command ratio _λ maxS1 ^* using a minimum voltage command using the correction value lambda _Mincmp obtain oN time ratio _λ minS4 ^** by correcting the on-time ratio _λ minS4 ^*. The on-time ratio λ _midS2 ^* of the intermediate voltage command is output as it is as λ _midS2 ^** .

Each phase on-time ratio calculating means 40 performs reverse conversion of Table 1 on the on-time ratios λ _maxS1 ^** , λ _midS2 ^** , λ _minS4 ^** , and the on-time of the voltage command for the U, V, and W phases. The ratios are converted into λ _u , λ _v , and λ _w .
The triangular wave comparison means 55 compares each phase voltage command v _u0 , v _v0 , v _w0 based on the on-time ratios λ _u , λ _v , λ _w with a triangular wave, and turns on / off command S for the switching element of each of the three phases. seek _{u1 ~S u4, S v1 ~S v4} , S w1 ~S w4.

Here, the on-time ratios λ _u , λ _v , and λ _w are values obtained by correcting the output voltage error caused by the on-delay time T _d according to the polarity of the current for the maximum phase and the minimum phase. If each switching element is driven using the ON / OFF commands S _{u1 to} S _u4 , S _{v1 to} S _v4 , and S _{w1 to} S _w4 , a three-phase AC voltage having no error with respect to the voltage command is output from the inverter. be able to.
The series of operations by the on-delay correction unit 80, each phase on-time ratio calculation unit 40, and the triangular wave comparison unit 55 in FIG. 1 is based on the on-time ratios λ _maxS1 ^* , λ _midS2 ^* , and λ _minS4 ^* before the on-delay correction. The logical product of the ON / OFF command of the switching element of each phase and the ON / OFF command of the switching element of each phase by the ON time ratios λ _maxS1 ^* , λ _midS2 ^* , λ _minS4 ^* after the on-delay correction is obtained This corresponds to an operation for calculating a typical on / off command.

10: Maximum / intermediate / minimum voltage command calculation means 20: Intermediate phase selection means 30: On time ratio calculation means 40: Each phase on time ratio calculation means 55: Triangular wave comparison means 60: Maximum / intermediate / minimum phase current classification means 70 : Correction value calculation means 80: On-delay correction means B ₁ and B ₂ : DC power supplies S _{1 to} S ₄ : Switching elements D ₁ and D ₂ : Diodes

Claims (2)

Turns on and off multiple switching elements connected between a DC circuit having a high voltage point, a medium voltage point, and a low voltage point, and an AC output terminal for one phase, thereby generating a DC high voltage, a DC medium voltage, and a DC low voltage. This is a control method for a three-level inverter that includes three-level inverters capable of outputting three voltage levels consisting of voltages for three phases and outputs a three-phase AC voltage by operating the switching element in accordance with a three-phase output voltage command. And
Per switching period of the switching element,
A three-level inverter for the first phase turns on and off the switching element connected to the high voltage point and the switching element connected to the medium voltage point to output a DC high voltage and a DC medium voltage, A three-level inverter for two phases fixes a switching element connected to the medium voltage point in an ON state and outputs a DC medium voltage, and a three-level inverter for a third phase connects to the medium voltage point In a control method for calculating an on-time ratio of each switching element so as to output a DC intermediate voltage and a DC low voltage by turning on and off the switching element connected to the low voltage point and outputting a DC medium voltage and a DC low voltage,
A three-level inverter for the first phase and the third phase using the ratio of the on-delay time and switching period set for preventing power supply short-circuiting by simultaneously turning on a plurality of switching elements and the polarity of the load current The on-delay correction value for each of the switching elements is calculated, and the on-time ratio for the switching elements of the three-level inverters for the first phase and the third phase is respectively corrected by the on-delay correction value. 3-level inverter control method. Turns on and off multiple switching elements connected between a DC circuit having a high voltage point, a medium voltage point, and a low voltage point, and an AC output terminal for one phase, thereby generating a DC high voltage, a DC medium voltage, and a DC low voltage. A control device for a three-level inverter that includes three-phase inverters capable of outputting three voltage levels consisting of voltages for three phases, and outputs the three-phase AC voltage by operating the switching element in accordance with a three-phase output voltage command. And
Per switching period of the switching element,
A three-level inverter for the first phase turns on and off the switching element connected to the high voltage point and the switching element connected to the medium voltage point to output a DC high voltage and a DC medium voltage, A three-level inverter for two phases fixes a switching element connected to the medium voltage point in an ON state and outputs a DC medium voltage, and a three-level inverter for a third phase connects to the medium voltage point In a control device for calculating the on-time ratio of each switching element so as to output a DC medium voltage and a DC low voltage by turning on and off the switching element connected to the low voltage point and outputting a DC medium voltage and a DC low voltage,
Intermediate phase selection means for selecting a voltage command having an intermediate amplitude from the three-phase output voltage commands in a predetermined section;
The three-phase output voltage command is divided into the maximum voltage command, intermediate voltage command, and minimum voltage command according to the amplitude, and the maximum voltage command, intermediate voltage command, and minimum voltage command are set so that the intermediate voltage command is always zero. Maximum / intermediate / minimum voltage command calculation means to correct and output,
On-time with respect to the switching element of the three-level inverter for three phases to output the voltage according to the corrected maximum voltage command / intermediate voltage command / minimum voltage command using the DC high voltage and DC low voltage An on-time ratio calculating means for calculating a ratio;
A three-level inverter for the first phase and the third phase using the ratio of the on-delay time and switching period set for preventing power supply short-circuiting by simultaneously turning on a plurality of switching elements and the polarity of the load current Correction value calculation means for calculating an on-delay correction value for each of the switching elements,
On-delay correction for correcting the on-time ratios for the switching elements of the three-level inverters for the first phase and the third phase among the on-time ratios output from the on-time ratio calculation means, respectively, by the on-delay correction value Means,
A control device for a three-level inverter.

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