JP5493783B2 - Three-phase inverter device - Google Patents

Description

  The present invention relates to a three-phase inverter device that converts a DC power from a DC power source such as a solar cell or a fuel cell into an AC power and employs a hysteresis comparator control. This three-phase inverter device can be used, for example, for performing an operation for connecting the converted AC power to a commercial power system (this is referred to as a “interconnection operation”).

  A conventional example of this type of three-phase inverter device is shown in FIG. The three-phase inverter device includes a three-phase inverter circuit 4 that converts DC power from the DC power source 2 into three-phase AC power and outputs the output, and a hysteresis comparator control circuit 14 that controls the three-phase inverter circuit 4. I have. Reference numeral 3 denotes a DC input terminal, and reference numeral 11 denotes a three-phase AC output terminal. This three-phase inverter device is a so-called three-phase three-wire device.

The three-phase inverter circuit 4 has six switching elements S _{1 to} S ₆ connected in a three-phase bridge. Each of the switching elements S _{1 to} S ₆ is, for example, an IGBT (Insulated Gate Bipolar Transistor), but is not limited thereto. Each of the switching elements S _{1 to} S ₆ usually has a feedback diode (also referred to as a freewheeling diode, a freewheeling diode, or a freewheeling diode) for returning the energy stored in the load inductance to the DC power supply, as shown in the illustrated example. D _{1 to} D ₆ are connected in parallel in the reverse direction.

The hysteresis comparator system control circuit 14 controls the three-phase inverter circuit 4 by a hysteresis comparator system which is a kind of PWM (pulse width modulation) control. That is, the gate signals G _{1 to} G for controlling the output currents I _U , I _V , I _W of each phase of the three-phase inverter circuit 4 within a predetermined hysteresis width with respect to the current command value of the sine wave for each phase. ₆ is prepared and supplied to the switching elements S _{1 to} S ₆ of the three-phase inverter circuit 4.

  The hysteresis comparator method is a known technique as described in Patent Document 1, for example. The principle will be briefly described below.

Taking the U phase as an example, as shown in FIG. 14, in the hysteresis comparator system, the output current I _U is a sine wave current (which is actually a sine wave although it looks straight because it is enlarged in FIG. 14). The gate signal G ₁ supplied to the U-phase switching element S ₁ is controlled to be turned on / off so that it falls within a predetermined hysteresis width ± ΔI _{H with} respect to the command value I _CU . The gate signal G ₂ supplied to the lower switching element S ₂ in the same phase is controlled so that the on / off state is opposite to the gate signal G ₁ . That is, in order to avoid a power supply short circuit, the switching elements S ₁ and S ₂ of the same phase are controlled so as to provide a dead time and to turn on / off operations opposite to each other.

For the V-phase and the W-phase, the same control as described above is performed using a sinusoidal current command value whose phase is delayed by 120 degrees and 240 degrees from the U-phase current command value I _CU , respectively.

Referring to FIG. 13 again, in this example, the output section of the three-phase inverter circuit 4 is connected to a commercial three-phase circuit via three reactors 8 and three capacitors 10 constituting a filter for removing harmonic components. It is connected to the power system 12. Each reactor 8 is connected in series to each phase, and each capacitor 10 is connected in parallel between the phases. The output currents I _U , I _V , and I _W of each phase are measured using the current transformer 6, and the line voltages V _UV , V _VW , and V _WU of the power system 12 are measured using an instrument transformer (not shown). Each of the measured values is supplied to the hysteresis comparator control circuit 14 for the above control.

JP 2008-167524 A (paragraphs 0093-0106, FIGS. 12-13)

In the conventional three-phase inverter device, when the U phase is taken as an example, the gate signal G ₁ is repeatedly turned on and off even near the positive and negative peaks of the output current I _U as shown in the example shown in FIG. (Refer to the parts a and b), switching of the switching element S ₁ is performed. The same applies to the switching element S ₂ of the same phase. The same applies to the switching elements S _{3 to} S ₆ of other phases. FIG. 15 is an example in which the output current (amplitude) is 40 A and the hysteresis width is ± 1 A (the same applies to the examples in FIGS. 16 and 6 to 8).

When the switching elements S _{1 to} S ₆ perform switching, a switching loss always occurs, and the switching loss increases when the current is large. Therefore, the switching loss is equivalent to the amount of switching performed near the current peak as described above. Increases the efficiency of the inverter.

Further, a control system including a measuring instrument (specifically, a control system including the current transformer 6 and the hysteresis comparator control circuit 14) for controlling the output currents I _{U to} I _W is offset. (Residual deviation) exists. Therefore, a direct current component is superimposed on the output currents I _{U to} I _W. An example of this is shown in FIG. 16 taking the U phase as an example.

In the example of FIG. 16, by the offset, the DC component is superimposed on the output current I _U, the entire output current I _U is slightly shifted to the positive side. At this time, in the vicinity of the negative peak of the output current I _U (see part c), the absolute value of the output current I _U is smaller than the original value (that is, on the positive side), and the hysteresis in the control of the hysteresis comparator system is performed. Since the frequency of exceeding the upper limit value + ΔI _H of the width increases, the switching of the switching element S ₁ is performed by frequently turning on and off the gate signal G ₁ (refer to the part d). The same applies to the switching element S ₂ of the same phase. Contrary to the above example, when the output current I _U is shifted to the negative side, the gate signal G ₁ is frequently turned on and off in the vicinity of the positive peak of the output current I _U to switch the switching element S ₁ . Is done. The above also applies to the switching elements S _{3 to} S ₆ of other phases.

When the switching elements S _{1 to} S ₆ perform extra switching as described above due to the presence of an offset, as described above, the switching loss increases accordingly, so that the inverter efficiency further decreases.

  In view of this, the main object of the present invention is to reduce the switching loss as described above in a three-phase inverter device controlled by a hysteresis comparator system, thereby enabling high efficiency of the inverter.

The three-phase inverter device according to the present invention is a three-phase inverter device that is connected to a commercial three-phase power system and performs a linked operation with the power system, and has six switching elements connected in a three-phase bridge. And controlling the output current of each phase of the three-phase inverter circuit within a predetermined hysteresis width with respect to the current command value of the sine wave for each phase. In a three-phase inverter device comprising a hysteresis comparator system control circuit that creates a gate signal to be generated and supplies the gate signal to each switching element of the three-phase inverter circuit, a positive-side current command value for each phase The current command of the three-phase inverter circuit is not dependent on the gate signal from the hysteresis comparator control circuit for a predetermined period including the time point of the peak value. A switching element on the upper side of each phase corresponding to the value is forcibly turned on and a switching element on the lower side is forcibly turned off, and includes a time point of a negative peak value of the current command value for each phase For the period only, the lower switching element of each phase corresponding to the current command value of the three-phase inverter circuit is forcibly turned on and does not depend on the gate signal from the hysteresis comparator control circuit. A forced on control circuit that performs control to forcibly turn off the power, and the forced on control circuit obtains (a) the phase of at least one phase voltage of the power system, and By adding the desired power factor for operating the three-phase inverter device to the phase of the phase voltage, the phase of the current command value for each phase corresponding to the power factor is obtained. Phase determining means for instructing the hysteresis comparator system control circuit to determine the phase of the current command value for each phase obtained, and (b) based on the phase of the phase voltage of the power system obtained by the phase determining means, And a forcible control means for performing the control to forcibly turn on and off the switching elements of the three-phase inverter circuit as described above .

  In this three-phase inverter device, the forced on control circuit forcibly turns on the switching elements of each phase for a predetermined period including the time point of the peak value of the current command value for each phase without switching. Thus, it is possible to prevent a switching loss from occurring during the predetermined period. The same applies to the case where there is an offset in the control system, and it is possible to prevent the occurrence of switching loss in the predetermined period.

  The predetermined period is, for example, a period of 60 degrees represented by a phase width.

The three-phase inverter device according to the present invention includes : ( A) a feedback diode connected in antiparallel to each switching element of the three-phase inverter circuit; and (B) an output unit of each phase of the three-phase inverter circuit. (C) an input voltage variable circuit that is provided on the input side of the three-phase inverter circuit and changes the magnitude of the inverter input DC voltage supplied to the three-phase inverter circuit; ) (A) Based on the phase voltage of the power system and the voltage across the reactor for any one of the two phases other than the phase in which the switching element of the three-phase inverter circuit is forcibly turned on The absolute value of the output phase voltage of the three-phase inverter circuit for the one phase is calculated, and (b) the absolute value of the output phase voltage is multiplied by √3 to Calculating an absolute value of the output line voltage, and (c) adding a forward voltage drop of one feedback diode and an internal voltage drop of the switching element when the switching element is turned on to the absolute value of the output line voltage. To calculate a command value of the inverter input DC voltage to be supplied to the three-phase inverter circuit, and (d) and the input so that the inverter input DC voltage output from the input voltage variable circuit becomes the command value. And an input voltage control circuit for controlling the voltage variable circuit.

  The input voltage variable circuit is, for example, a DC-DC converter.

  According to the first and second aspects of the present invention, the forced on-control circuit forcibly switches the switching element of each phase without switching it for a predetermined period including the time point of the peak value of the current command value for each phase. Therefore, switching loss can be prevented from occurring during the predetermined period. The same applies to the case where there is an offset in the control system, and it is possible to prevent the occurrence of switching loss in the predetermined period. Since the switching loss can be reduced in this way, the inverter can be made highly efficient.

  In the prior art, the switching frequency of the switching element is low near the peak of the output current, but it is difficult to determine the minimum switching frequency. Therefore, a filter for removing harmonic components provided on the output side of the three-phase inverter circuit. It was difficult to set the cut-off frequency, and the filter design was difficult. On the other hand, according to the present invention, the switching element is not switched in the vicinity of the peak of the output current where the switching frequency becomes low, that is, in a predetermined period including the peak point of the output current, so that the minimum switching frequency can be easily determined. Accordingly, calculation of the filter cutoff frequency is facilitated, and filter design is facilitated. Further, since the cut-off frequency can be made higher than before, the reactor and the capacitor constituting the filter can be reduced in size.

  In addition, a surge voltage (turn-off surge voltage) is normally generated at both ends of each switching element when the current is interrupted by the switching element, and when the reverse recovery current flowing when the switching element on the opposite side of the same arm is turned on is recovered. It has been conventionally known that surge voltages (recovery surge voltages) are generated, and these surge voltages become large when switching is performed when the value of the output current is large. On the other hand, according to the present invention, when the output current is large as described above, that is, during the predetermined period including the peak time of the output current, the switching elements are not switched. Surge voltages (turn-off surge voltage and recovery surge voltage) can be suppressed to be small. As a result, for example, the capacity of the capacitor constituting the snubber circuit added to each switching element as a countermeasure against surge voltage can be reduced, and thus the number of capacitors can be reduced.

  According to invention of Claim 3, 4, there exists the following further effect. That is, by controlling the inverter input DC voltage as described above by the input voltage control circuit and the input voltage variable circuit, the inverter input DC voltage can be controlled to a value suitable for the line voltage of the interconnection power system. Therefore, in the vicinity of the positive and negative peaks of the output current of each phase, the on period during which the switching element is turned on without switching can be made longer than the period during which the forced on control circuit forcibly turns on. it can. Accordingly, the switching loss can be further reduced by that amount, so that the inverter can be further improved in efficiency.

1 is a circuit diagram showing an embodiment of a three-phase inverter device according to the present invention. FIG. 2 is a block diagram illustrating an example of a configuration of a hysteresis comparator control circuit and a forced on control circuit in FIG. 1. FIG. 2 is a block diagram illustrating an example of a configuration of a gate signal output circuit in FIG. 1 and the like. It is a figure which shows an example of the control mode of a switching element. It is a figure which shows an example of operation | movement of the forced ON control circuit in FIG. It is a figure which shows an example of the simulation waveform of the gate signal and U-phase output current which are supplied to the switching element of a U-phase upper side in embodiment shown in FIG. It is a figure which shows an example of the relationship between the output current command value and the switching frequency of a switching element in the conventional three-phase inverter apparatus. It is a figure which shows an example of the relationship between the output electric current command value in the embodiment shown in FIG. 1, and the switching frequency of a switching element. FIG. 7 is a block diagram showing another example of the configuration of the hysteresis comparator control circuit and the forced on control circuit in FIG. 1. It is a circuit diagram which shows other embodiment of the three-phase inverter apparatus based on this invention. It is a block diagram which shows an example of a structure of the hysteresis comparator system control circuit in FIG. 10, a forced ON control circuit, and an input voltage control circuit. It is a figure which shows an example of the simulation waveform of the gate signal and each phase output current which are supplied to the switching element of each phase upper side in embodiment shown in FIG. It is a circuit diagram which shows an example of the conventional three-phase inverter apparatus. It is a figure which shows the principle of a hysteresis comparator system control. It is a figure which shows an example of the simulation waveform of the gate signal and U phase output current which are supplied to the switching element of the U phase upper side in the conventional apparatus shown in FIG. FIG. 14 is a diagram illustrating an example of simulation waveforms of a gate signal and a U-phase output current supplied to a switching element on the upper side of the U phase when an offset exists in the control system in the conventional apparatus illustrated in FIG. 13. FIG. 11 is a diagram illustrating an example of a state of each switching element with a switch symbol while extracting the periphery of the three-phase inverter circuit in FIG. 10. It is a figure which shows an example of the vector of each voltage and each current in the state of FIG.

(1) Embodiment in which switching element is forcibly turned on FIG. 1 shows an embodiment of a three-phase inverter device according to the present invention. Portions that are the same as or correspond to those in the conventional example shown in FIG. 13 are denoted by the same reference numerals, and differences from the conventional example will be mainly described below.

The three-phase inverter device of this embodiment includes a three-phase inverter circuit 4 described above, a hysteresis comparator control circuit 14a having substantially the same function as the hysteresis comparator control circuit 14, and the hysteresis comparator control circuit 14a. A forced-on control circuit 16 is provided between the three-phase inverter circuit 4 and forcibly turns on / off the switching elements S _{1 to} S ₆ of the three-phase inverter circuit 4. Other configurations are the same as those shown in FIG.

Although details will be described later with reference to FIG. 2, the hysteresis comparator control circuit 14 a uses the output currents I _U , I _V , I _W of each phase of the three-phase inverter circuit 4 as sine wave current commands for each phase. A gate signal that is controlled within a predetermined hysteresis width with respect to the value is created and supplied to the switching elements S _{1 to} S ₆ of the three-phase inverter circuit 4.

The forced-on control circuit 16 does not depend on the gate signal from the hysteresis comparator control circuit 14a for a predetermined period including the time point of the positive peak value of the current command value for each phase. The upper switching element S ₁ , S ₃ or S ₅ of each phase corresponding to the current command value is forcibly turned on and the lower switching element S ₂ , S ₄ or S ₆ of the same phase is forcibly turned off And the current command value of the three-phase inverter circuit 4 for a predetermined period including the time point of the negative peak value of the current command value for each phase without depending on the gate signal from the hysteresis comparator control circuit 14a. The switching elements S ₂ , S ₄ or S ₆ on the lower side of each phase corresponding to are forcibly turned on, and the upper switching elements S ₁ , S ₃ or S ₅ of the same phase are forcibly turned off. Control is performed.

The predetermined period is, for example, a period of 60 degrees represented by a phase width. FIG. 4 and Table 1 collectively show control modes M _{1 to} M ₆ representing the on / off states of the switching elements S _{1 to} S ₆ in this case. But the said predetermined period is not restricted to a period of 60 degree | times, What is necessary is just a period larger than 0 degree | times and below 60 degree | times.

  That is, forcible on / off control of one of the three-phase switching elements is performed by the forced on-control circuit 16, and switching control is performed on the remaining two-phase switching elements by the hysteresis comparator control circuit 14a.

  An example of the configuration of the hysteresis comparator control circuit 14a and the forced on control circuit 16 is shown in FIG. FIG. 2 is an example in the case where the output part of the three-phase inverter circuit 4 is connected to the commercial three-phase power system 12 to perform the interconnection operation.

  In this example, the hysteresis comparator control circuit 14a includes the phase voltage conversion circuit 22, the current command value creation circuit 24, the hysteresis width setter 26, the hysteresis upper limit value calculation circuit 28, the hysteresis lower limit value calculation circuit 30, and the comparators 32 and 34. And a gate signal generation circuit 36. The comparators 32 and 34 constitute a hysteresis comparator.

The phase voltage conversion circuit 22 measures line voltages V _UV , V _VW , V _WU of the three-phase power system 12 and converts them to phase voltages V _U , V _V , V _W. This is because the phase information of the phase voltage is used in the current command value creation circuit 24.

The current command value generation circuit 24 is configured to output three-phase signals based on the phase information of each phase voltage V _U , V _V , V _W given from the phase voltage conversion circuit 22 and the current amplitude I _P commanded from the outside. It generates and outputs sinusoidal current command values I _CU , I _CV , and I _CW for the output currents I _U , I _V , and I _W. The current amplitude I _P is common to the three phases. As is well known in the case of three-phase alternating current, the phases of the U phase, the V phase, and the W phase are only delayed by 120 degrees each, so that the phase voltage of one phase (for example, the phase voltage V _{U of the} U phase) The phase of the V phase and the W phase may be calculated by detecting the phase and delaying the phase by 120 degrees.

The hysteresis width setting unit 26 sets the hysteresis width ΔI _H described above (see FIG. 14). This is common to the three phases in this example.

The hysteresis upper limit calculation circuit 28 calculates and outputs three-phase hysteresis upper limit values I _HU , I _HV , and I _HW according to the following equation.

[Equation 1]
I _HU = I _CU + ΔI _H
I _HV = I _CV + ΔI _H
I _HW = I _CW + ΔI _H

The hysteresis lower limit value calculation circuit 30 calculates and outputs three-phase hysteresis lower limit values I _LU , I _LV , and I _LW according to the following equations.

[Equation 2]
I _LU = I _CU -ΔI _H
I _LV = I _CV -ΔI _H
I _LW = I _CW −ΔI _H

The comparator 32 outputs the output currents I _U , I _V , I _{W of} the three-phase inverter circuit 4 measured using the current transformer 6, and the hysteresis upper limit values I _HU , I _HV , I from the hysteresis upper limit value calculation circuit 28. Compared with _HW , the U phase will be described as an example. When the output current I _U becomes larger than the hysteresis upper limit value I _HU, the gate signal GS ₁ that turns off the switching element S ₁ and turns on the switching element S ₂ . A signal that causes GS ₂ to be output from the gate signal generation circuit 36 is output (see also FIG. 14). The same applies to the V phase and the W phase.

The comparator 34 measures the output currents I _U , I _V , I _{W of} the three-phase inverter circuit 4 measured using the current transformer 6 and the hysteresis lower limit values I _LU , I _LV , I _W from the hysteresis lower limit calculation circuit 30. Comparing _LW with each other and explaining the U phase as an example, when the output current I _U becomes smaller than the hysteresis lower limit value I _LU, the gate signal GS ₁ that turns on the switching element S ₁ and turns off the switching element S ₂ . A signal that causes GS ₂ to be output from the gate signal generation circuit 36 is output (see also FIG. 14). The same applies to the V phase and the W phase.

The gate signal generating circuit 36, based on a signal from the comparator 32 and 34, to create a gate signal GS ₁ ~GS ₆ to respectively turn on and off the switching elements S ₁ to S ₆ of the three-phase inverter circuit 4 Output. Each of the gate signals GS _{1 to} GS ₆ is a pulse signal that takes a logical value 1 or 0. In this case, as described above, taking the U phase as an example, the logic values of the gate signals GS ₁ and GS ₂ are set so that the switching elements S ₁ and S ₂ of the same U phase are turned on and off. Reverse each other. The same applies to the V phase and the W phase.

Incidentally, the gate signal GS ₁ ~GS _6, via a gate signal output circuit 44 to be described later, is supplied is converted into the gate signal G ₁ ~G ₆ to each of the switching elements S ₁ to S _6. In this case, in this embodiment, only the gate signals GS ₂ , GS ₄ , and GS ₆ are used in the gate signal output circuit 44, and the gate signals corresponding to the gate signals GS ₁ , GS ₃ , and GS ₅ of the inverse logic are used. Since the gate signal output circuit 44 generates the signal, that is, the gate signal output circuit 44 has a part of the function of the hysteresis comparator control circuit 14a. ₂ , only GS ₄ and GS ₆ may be created.

With the above control, the output currents I _U , I _V , I _W of each phase output from the three-phase inverter circuit 4 are predetermined with respect to the sine wave current command values I _CU , I _CV , I _CW for each phase. It is controlled so as to be within the hysteresis width ± ΔI _H. This is the details of the hysteresis comparator system control described above.

  In this example, the forced-on control circuit 16 includes a comparator 38, a counter 40, a phase determination circuit 41, a forced control signal generation circuit 42, and a gate signal output circuit 44.

Referring also to FIG. 5, the comparator 38 compares the one-phase phase voltage (in this example, the U-phase voltage V _U ) from the phase voltage conversion circuit 22 with a reference value of 0 V (volts), and the phase voltage V _{When U} is negative, a logical value 1 is output, and when _U is 0 V or higher, a logical value 0 is output.

The counter 40 sets the count value at the falling edge time to 0 from the falling edge time point of the output of the comparator 38 every cycle of the phase voltage V _U , that is, every cycle of the output of the comparator 38. Start counting.

Here, as an example, the phase determination circuit 41 uses a count value for one cycle previously counted by the counter 40 and divides the value by 360 to calculate a count value per degree. Then by multiplying the count value of the current count per the once value of the counter 40 to determine the current phase of the phase voltage V _U [degrees]. Further, by adding a desired power factor for operating the three-phase inverter device, the phase of the current command value I _CU corresponding to the power factor (this is the same as the phase of the output current I _U ) is obtained. For example, if the power factor is 1, the phase voltage V _U and the current command value I _CU are in the same phase. The phases of the V phase and the W phase are obtained by delaying each by 120 degrees from the phase of the U phase.

The compulsory control signal generation circuit 42 is configured to control the switching mode M in which the current phase forcibly turns on / off the switching elements S _{1 to} S ₆ of the three-phase inverter circuit 4 based on the phase obtained by the phase determination circuit 41. _{1 to} M ₆ (refer to FIG. 4, Table 1) is determined, and the switching elements S _{1 to} S ₆ are forced as shown in FIG. 4 and Table 1 in the determined control mode. Forcible control signals CS _{1 to} CS ₆ that realize turning on and off are generated and output. Taking the switching element S _1, the forced control signal CS ₁ for S _2, CS ₂ as an example, as can be seen from Figure 4, the forced control signal CS _1, CS _2, the control mode M in ₂ each logical value 1 , 0, the control mode M in ₅ respectively next logical values 0 and 1, respectively the logical values 0, 0 in the other control mode (see also Table 2). Similarly be seen from Figure 4 also forced control signal CS ₃ to CS ₆ for switching element S ₃ to S _6. Table 2 summarizes the logical value states of the forced control signals CS _{1 to} CS _{6 in} the control modes M _{1 to} M ₆ .

The gate signal output circuit 44 forces the switching elements based on the gate signals GS _{1 to} GS ₆ from the gate signal creation circuit 36 and the forced control signals CS _{1 to} CS ₆ from the forced control signal creation circuit 42. in the control mode to be turned on and off by a gate signal G ₁ ~G ₆ of the same logical value as the logical value of the forced control signal CS ₁ to CS _6, the logic value of the gate signal GS ₁ ~GS ₆ in the other control modes The gate signals G _{1 to} G ₆ having the same logical value as the above are output.

An example of the configuration of the gate signal output circuit 44 is shown in FIG. The gate signal output circuit 44 includes circuits 45a to 45c having the same configuration for U phase, V phase, and W phase. To explain U-phase as an example, the circuit 45a for the U-phase includes a NOT circuit 52 to force the control signal CS ₁ is input, the forced control signal CS ₂ and the gate signal OR circuit 54 GS ₂ is input, the It has an AND circuit 56 to which the outputs of the NOT circuit 52 and the OR circuit 54 are input, and a NOT circuit 58 to which the output of the AND circuit 56 is input. The output of the AND circuit 56 is a gate signal G _1, output of the NOT circuit 58 is a gate signal G _2. Table 3 summarizes the logical value states of the U-phase circuit 45a.

As can be seen from Table 3, the U-phase circuit 45a provides a forced control signal CS ₁ in the control modes M ₂ and M ₅ forcing the U-phase switching elements S ₁ and S ₂ on and off. , and outputs a gate signal G _1, G ₂ of the same logical value as the logical value of CS _2, the gate of the gate signals G ₂ and therewith reverse logic of the same logical value as the logical value of the gate signal GS ₂ is in the other control modes and it outputs the signal G _1.

  The same applies to the V-phase and W-phase circuits 45 b and 45 c constituting the gate signal output circuit 44.

That is, the V-phase circuit 45b has the same logic value as the logical values of the forced control signals CS ₃ and CS ₄ in the control modes M ₁ and M ₄ forcing the V-phase switching elements S ₃ and S ₄ on and off. outputs gate signals G _3, G ₄ value, and outputs a gate signal G ₄ and its opposite logic of the gate signal G ₃ having the same logical value as the logical value of the gate signal GS ₄ in the other control mode.

The W-phase circuit 45c has the same logical value as that of the forced control signals CS ₅ and CS ₆ in the control modes M ₃ and M ₆ forcibly turning on and off the W-phase switching elements S ₅ and S ₆ . outputs gate signals G _5, G _6, and outputs a gate signal G ₅ of the gate signals G ₆ and its opposite logic of the same logical value as the logical value of the gate signal GS ₆ in the other control mode.

As described above, in the three-phase inverter device, the forced-on control circuit 16 causes the switching elements of the respective phases to be applied for a predetermined period including the peak value of the current command values I _{CU to} I _CW for each phase. Since the switch is forcibly turned on without switching, it is possible to prevent a switching loss from occurring during the predetermined period.

An example of the simulation result is shown in FIG. This is for the U phase. In this example, the switching element S ₁ is forcibly turned on by setting the gate signal G ₁ to a logical value 1 only for a predetermined period T ₁ including the time point of the positive peak value of the U-phase current command value (in the meantime, The switching element S ₂ is forcibly turned off as described above), and the gate signal G ₁ is set to a logical value 0 for a predetermined period T ₂ including the time point of the negative peak value of the U-phase current command value, thereby switching the switching element S ₁ It is forcedly turned off (during which the switching element S ₂ as described above is forcibly turned on). This is a significant difference from the conventional example shown in FIG.

Except for the predetermined periods T ₁ and T ₂ , switching control of the switching elements S ₁ and S ₂ is performed under the control of the hysteresis comparator control circuit 14a. Further, during the predetermined periods T ₁ and T ₂ , in the remaining two phases (V phase and W phase), the switching control of the switching elements S _{3 to} S ₆ is performed by the control of the hysteresis comparator control circuit 14a.

Even if the forced on control as described above is performed, as shown in FIG. 6, a sinusoidal output current I _U having a set amplitude (40 A in this example) can be output. This is not much different from the conventional example shown in FIG.

  The same applies to the V phase and the W phase.

  In addition, even if there is an offset in the control system as described above, the present invention relates to the present invention in a period near the peak that has been conventionally switched due to the presence of the offset (see portions c and d in FIG. 16). In the three-phase inverter device, since the switching element is forcibly turned on as described above, switching due to the presence of the offset can be prevented. Therefore, it is possible to prevent switching loss from occurring accordingly.

  As described above, according to the three-phase inverter device according to the present invention, the switching loss can be reduced, so that the efficiency of the inverter can be increased.

In the prior art, the switching frequency of the switching element is lowered near the peak of the output current as in the example shown in FIG. 15, but it is difficult to determine the minimum switching frequency. This will be described with reference to simulation results using the U phase as an example. As shown in FIG. 7, in the conventional technique, the current command value I _CU (which corresponds to the output current of the U phase; the same applies hereinafter) is positive / negative. In the vicinity of the peak of, switching is performed to a very low frequency region. The same applies to the V phase and the W phase. For this reason, it is difficult to determine the minimum switching frequency. Therefore, the cutoff frequency of the harmonic component removing filter (which is constituted by the reactor 8 and the capacitor 10) provided on the output side of the three-phase inverter circuit 4 is provided. It was difficult to set the filter and the filter design was difficult.

On the other hand, according to the three-phase inverter device according to the present invention, the switching element is not switched in the vicinity of the peak of the output current where the switching frequency becomes low, that is, in the predetermined period including the peak point of the output current. The frequency can be easily determined. This will be explained using simulation results with the U phase as an example. As shown in FIG. 8, since switching is not forcibly performed in the vicinity of the positive / negative peak of the current command value I _CU , the boundary portion with the portion to be switched The switching frequency (about 5 kHz) at (around ± 30 A in the example of FIG. 8) is the lowest switching frequency. The same applies to the V phase and the W phase. Therefore, it is easy to determine the minimum switching frequency. Therefore, it becomes easy to calculate the cutoff frequency of the filter, and the filter design is facilitated. Further, since the cut-off frequency can be made higher than before, the reactor 8 and the capacitor 10 constituting the filter can be downsized.

Further, normally, a surge voltage (turn-off surge voltage) is generated at both ends of each of the switching elements S _{1 to} S ₆ constituting the three-phase inverter circuit 4 when the current is interrupted by the switching element, and the opposite side of the same arm. It has been conventionally known that a surge voltage (recovery surge voltage) is generated even when the reverse recovery current that flows during the ON operation of the switching element is recovered, and that the surge voltage increases when switching is performed when the value of the output current is large. ing. On the other hand, according to the three-phase inverter device according to the present invention, when the output current is large as described above, that is, during the predetermined period including the peak time of the output current, the switching element is not switched. The surge voltage (turn-off surge voltage and recovery surge voltage) generated at both ends of S _{1 to} S ₆ can be suppressed to a small level. As a result, for example, the capacitance of the snubber circuit added to each of the switching elements S _{1 to} S ₆ as a countermeasure against surge voltage can be reduced, and the number of capacitors can be reduced.

  In addition to the example shown in FIG. 2, for example, the following method is used as a method for determining the period during which the switching elements are forcibly turned on (the switching elements on the opposite side of the same phase are turned off) in the forced on control circuit 16. May be adopted. The following description is easy to understand with reference to FIG.

(A) A period in which the absolute value of the phase having a larger absolute value than the other two phases is large by comparing the absolute values of the current command values I _CU , I _CV and I _CW of the three phases.

(B) The polarity of the three-phase current command values I _CU , I _CV , and I _CW is determined (positive / negative), and the inversion period of the phase inverted from the other two phases.

  (C) In the case of performing the interconnection operation, when the operation with the power factor of 1 is performed, the phase voltage of the power system 12 and the output current of the three-phase inverter device are in phase. Period during which a) or (b).

  Further, the three-phase inverter device can be applied to a case where a self-sustained operation for supplying a current to a local load or the like is performed separately from the power system 12 in addition to the interconnected operation. When the autonomous operation is performed, for example, as shown in FIG. 9, instead of inputting the system line voltage to the hysteresis comparator control circuit 14a, a sine wave oscillator 50 is provided, and then the system line voltage is set. And a three-phase sine wave voltage corresponding to is outputted to the hysteresis comparator control circuit 14a (more specifically, the phase voltage conversion circuit 22). The voltage supplied to the hysteresis comparator system control circuit 14a may be switched between the system line voltage and the sine wave voltage from the sine wave oscillator 50. In this case, the interconnection operation and the independent operation are performed. And can be switched easily.

(2) Embodiment in which Forced ON Control of Switching Element and Inverter Input DC Voltage Control are Used Together FIG. 10 shows another embodiment of a three-phase inverter device according to the present invention, and FIG. 11 shows the hysteresis in FIG. An example of the configuration of a comparator control circuit, a forced on control circuit, and an input voltage control circuit is shown. Portions that are the same as or correspond to those in the embodiment shown in FIG. 1, FIG. 2, and the like are denoted by the same reference numerals.

  The three-phase inverter device of this embodiment is connected to a commercial three-phase power system 12 and performs a linked operation with the power system 12.

On the input side of the three-phase inverter circuit 4, an input voltage variable circuit 20 that changes the magnitude of the inverter input DC voltage E ₂ supplied to the three-phase inverter circuit 4 is provided. That is, the input voltage variable circuit 20 converts the DC voltage E ₁ supplied from the DC power supply 2 into an inverter input DC voltage E ₂ having a variable magnitude and outputs the inverter input DC voltage E ₂ . The input voltage variable circuit 20 is a DC-DC converter, for example, but is not limited thereto.

The three-phase inverter device of this embodiment further includes an input voltage control circuit 18, and the inverter input DC voltage E ₂ is determined by a voltage control signal ES given from the input voltage control circuit 18 to the input voltage variable circuit 20. Control is performed so as to _obtain a command value E _2C described below. The inverter input DC voltage E ₂ output from the input voltage variable circuit 20 is fed back to the input voltage control circuit 18.

The input voltage control circuit 18 includes a phase voltage and a reactor of the power system 12 for any one of the two phases other than the phase in which the switching elements S _{1 to} S ₆ of the three-phase inverter circuit 4 are forcibly turned on. A function of calculating the absolute value of the output phase voltage of the three-phase inverter circuit 4 for the one phase based on the both-end voltage of 8, and (b) a three-phase inverter by multiplying the absolute value of the output phase voltage by √3 The function of calculating the absolute value of the output line voltage of the circuit 4; and (c) the forward voltage drop of the feedback diodes D _{1 to} D ₆ and the switching element S _{1 to} the absolute value of the output line voltage. A function of calculating a command value E _2C of the inverter input DC voltage E ₂ to be supplied to the three-phase inverter circuit 4 by adding one of the internal voltage drops at ON of S ₆ to (d) Inverter output from variable input voltage circuit 20 Data input DC voltage E ₂ has a function of controlling an input voltage varying circuit 20 so that the command value E _2C. This will be described in detail with reference to FIGS.

Here, as an example, as shown in FIG. 17, the U-phase switching element S ₁ is forcibly turned on by the above-described forced-on control (therefore, the switching element S ₂ is forcibly turned off). The phase switching elements S _{3 to} S ₆ are controlled by switching, and of these, the switching elements S ₃ and S ₆ are in the on state and the switching elements S ₄ and S ₅ are in the off state. To do. This state is summarized in Table 4. Therefore, in the following description, the V phase and the W phase that are switching-controlled will be mainly described.

Assuming that the direction of current flows from the three-phase inverter circuit 4 to the power system 12 is positive, in the above state, the output current I _U (= − (I _V + I _W )) of the three-phase inverter circuit 4 is positive and output. The currents I _V and I _W are in the negative direction. Accordingly, as shown in FIG. 17, the U-phase output current I _U is the switching element S ₁ , and the V-phase output current I _V is the feedback diode D ₃ (the switching element S ₃ does not flow in the reverse direction). , W-phase output current I _W flows through switching element S ₆ .

FIG. 18 shows vectors of voltages and currents in the above case. This figure shows an example in which the three-phase inverter device is operating at a power factor of 1, and the output currents I _U , I _V , I _W are the phase voltages V _U , V _V , V of the power system 12. Each is in phase with _W. The voltages V _LU , V _LV , and V _LW at both ends of each reactor 8 have a 90 degree advance relationship with respect to the phase voltages V _U , V _V , and V _W. The size is expressed by the following equation. ω is an angular frequency, t is time, and L is an inductance of each reactor 8.

[Equation 3]
| V _LU | = | ωL · I _U |
| V _LV | = | ωL · I _V |
| V _LW | = | ωL · I _W |

As can be seen from Figure 18, the absolute value of the output phase voltage V _IV of the V phase of the three-phase inverter circuit 4 | V _IV | Both ends of the V-phase of the phase voltage V _V and V-phase of the reactor 8 of the electric power system 12 It can be calculated by the square root of the square sum of the voltage V _LV . The phase voltage V _V of the power system 12 can be calculated from the line voltage V _VW . The absolute value | V _IW | of the W-phase output phase voltage V _IW can be calculated based on the same idea. When these are expressed by equations, Equations 4 and 5 are obtained.

The absolute values | V _IV | and | V _IW | of the output phase voltage are substantially the same. Since this is a symmetrical three-phase alternating current, the peak values V _V and V _W of the voltages of the respective phases are the same, the peak values I _V and I _W of the currents of the respective phases are also the same, and the reactor of each phase This is because the inductances L of 8 are the same as each other, and only have different phases. Therefore, only one of them needs to be calculated. The calculation is performed by the input voltage control circuit 18. Here, a case will be described as an example where the absolute value | V _IV | of the V-phase output voltage V _IV is calculated (that is, the calculation of Equation 4).

The output line voltage of the three-phase inverter circuit 4 is 30 degrees ahead of the output phase voltage, and the absolute value is √3 times. Therefore, the absolute value | V _IVW | of the output line voltage V _IVW between the V phase and the W phase of the three-phase inverter circuit 4 can be calculated by the following equation. The second row of the following equation is obtained by substituting Equation 4 into | V _IV |. This calculation is performed by the input voltage control circuit 18.

One forward voltage drop (voltage drop when a forward current flows) of the feedback diodes D _{1 to} D ₆ is V _D , and one of the switching elements S _{1 to} S ₆ is turned on. Assuming that the voltage drop (voltage drop due to the internal resistance at the time of ON) is V _S , the input voltage control circuit 18 calculates the following equation and instructs the inverter input DC voltage E ₂ to be supplied to the three-phase inverter circuit 4. The value E _2C is calculated. The second line of the following equation is obtained by substituting Equation 6 into | I _IVW |.

The forward voltage drop V _D is substantially the same for all feedback diodes D ₁ -D ₆ . This is because feedback diodes having substantially the same characteristics are generally used as the feedback diodes D _{1 to} D ₆ .

The internal voltage drop V _S can be obtained by multiplying the resistance value R _ON when the switching element is on by the current value flowing therethrough. The on-resistance value R _ON is substantially the same for all the switching elements S _{1 to} S ₆ . This is because switching elements having substantially the same characteristics are generally used as the switching elements S _{1 to} S ₆ . Therefore, taking the switching element S ₆ as an example, the internal voltage drop V _S can be obtained by the following equation. The input voltage control circuit 18 performs this calculation.

[Equation 8]
| V _S | = | I _W | × R _ON

In the above description, as shown in FIG. 17 and Table 4, the state when the U-phase switching element S ₁ is forcibly turned on (and thus the switching element S ₂ is forcibly turned off) has been described as an example. The same result is obtained even when the V-phase or W-phase switching element is forcibly turned on as described above. This is because symmetric three-phase alternating current is handled.

  FIG. 11 shows an example of the configuration of the input voltage control circuit 18 that performs the above calculation and control. The input voltage control circuit 18 includes a phase voltage calculation circuit 45, a command value calculation circuit 46, and a voltage control circuit 48. Elements other than the input voltage control circuit 18 in FIG. 11 are as described with reference to FIG.

The phase voltage calculation circuit 45 calculates a required phase voltage of the power system 12, for example, the phase voltage V _V of the V phase, based on the line voltage of the power system 12 (for example, the line voltage V _VW ). As described above, since the phase voltage conversion circuit 22 also has a function of obtaining the phase voltage of the power system 12, the phase voltage conversion circuit 22 may be shared instead of providing the phase voltage calculation circuit 45.

The command value calculation circuit 46 outputs the phase voltage supplied from the phase voltage calculation circuit 45 and the output current of a required phase of the three-phase inverter circuit 4 measured using the current transformer 6 (see FIG. 1), for example, the V Based on the phase output current I _V , the forward voltage drop V _D, and the internal voltage drop V _S , the command value E _2C is calculated according to _Equation 7 above.

The voltage control circuit 48 compares the command value E _2C given from the command value calculation circuit 46 with the inverter input DC voltage E ₂ output from the input voltage variable circuit 20, and the inverter input DC voltage E ₂ is commanded. The input voltage variable circuit 20 is controlled by the voltage control signal ES so that the value E _2C is obtained.

By controlling the inverter input DC voltage E ₂ output from the input voltage variable circuit 20 to be the command value E _2C , the inverter input DC voltage E ₂ is a value suitable for the line voltage of the interconnection power system 12. In the vicinity of the positive and negative peaks of the output current of each phase of the three-phase inverter circuit 4, the on-period in which the switching element is turned on without switching is controlled by the forced on-control circuit 16. It can be expanded beyond the period when it is forcibly turned on (expansion of the on period). This is because the inverter input DC voltage E ₂ becomes a value suitable for the voltage of the electric power system 12 by the above control, and the difference between the input voltage and the output voltage of the three-phase inverter circuit 4 becomes small, and in the vicinity of the peak of the output current. This is because the period in which switching is not performed is extended (longened) by the hysteresis comparator system control described above. Accordingly, the switching loss can be further reduced by that amount, so that the inverter can be further improved in efficiency.

An example of the simulation result is shown in FIG. This corresponds to FIG. In this example, the ON period T ₁₀ in which the switching signals S ₁ , S ₃ , S ₅ are ON because the U-phase, V-phase, and W-phase gate signals G ₁ , G ₃ , G ₅ are at the logical value 1. , T ₃₀ and T ₅₀ are wider than the forced on-period T ₁ shown in FIG. If it sees at one certain time, it can also be said that the switching of only one phase is sufficient.

Even in the above case, as the output current, as shown in FIG. 12, sinusoidal output currents I _U , I _V , I _W having the amplitude as set (40 A in this example) can be output. In this respect, there is no significant difference from the case of FIG.

4 3-phase inverter circuit 8 a reactor 12 power system 14a hysteresis comparator system control circuit 16 forcibly on control circuit 18 the input voltage control circuit 20 the input voltage varying circuit S ₁ to S ₆ switching elements D ₁ to D ₆ feedback diodes E ₂ inverter input DC Voltage

Claims (4)

A three-phase inverter device connected to a commercial three-phase power system and connected to the power system,
A three-phase inverter circuit having six switching elements connected in a three-phase bridge and converting DC power to AC power;
A gate signal for controlling the output current of each phase of the three-phase inverter circuit within a predetermined hysteresis width with respect to the current command value of the sine wave for each phase is created, and the gate signal is generated for each of the three-phase inverter circuits. In a three-phase inverter device comprising a hysteresis comparator system control circuit for supplying to a switching element,
Corresponding to the current command value of the three-phase inverter circuit for a predetermined period including the time point of the positive peak value of the current command value for each phase without depending on the gate signal from the hysteresis comparator control circuit. Forcibly turning on the upper switching element of each phase and forcibly turning off the lower switching element, and only for a predetermined period including the time point of the negative peak value of the current command value for each phase Regardless of the gate signal from the hysteresis comparator control circuit, the lower switching element of each phase corresponding to the current command value of the three-phase inverter circuit is forcibly turned on and the upper switching element is forcibly turned on. It has a forced on control circuit that controls to turn off ,
The forced-on control circuit obtains (a) a phase of at least one phase voltage of the power system and a desired power factor for operating the three-phase inverter device to the phase voltage phase of the determined power system. To determine the phase of the current command value for each phase according to the power factor, and command the phase of the obtained current command value for each phase to the hysteresis comparator control circuit And (b) forced control means for performing the control to forcibly turn on and off the switching elements of the three-phase inverter circuit as described above based on the phase of the phase voltage of the power system obtained by the phase determination means. And a three-phase inverter device.   2. The three-phase inverter device according to claim 1, wherein the predetermined period is a period that is greater than 0 degree and less than or equal to 60 degrees in terms of a phase width. ( A) a feedback diode connected in antiparallel to each switching element of the three-phase inverter circuit;
(B) a reactor connected in series to the output section of each phase of the three-phase inverter circuit;
(C) an input voltage variable circuit that is provided on the input side of the three-phase inverter circuit and changes the magnitude of the inverter input DC voltage supplied to the three-phase inverter circuit;
(D) (a) The phase voltage of the power system and the voltage across the reactor for any one of the two phases other than the phase forcibly turning on the switching element of the three-phase inverter circuit Based on this, the absolute value of the output phase voltage of the three-phase inverter circuit for the one phase is calculated. (B) The absolute value of the output phase voltage is multiplied by √3 to obtain the output line voltage of the three-phase inverter circuit. (C) adding the forward voltage drop of one feedback diode and the internal voltage drop when one switching element is turned on to the absolute value of the output line voltage, A command value of the inverter input DC voltage to be supplied to the inverter circuit is calculated, and (d) and the input voltage is allowed so that the inverter input DC voltage output from the input voltage variable circuit becomes the command value. An input voltage control circuit for controlling the circuit,
The three-phase inverter device according to claim 1, further comprising:   The three-phase inverter device according to claim 3, wherein the input voltage variable circuit is a DC-DC converter.

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