JP2016149913A - Power conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a three-level type power conversion device to which a hysteresis comparator control system is applied appropriately.SOLUTION: A power conversion device 1 comprises a three-level type three-phase inverter part 10 and a control part 20. The three-level type three-phase inverter part includes: two switching elements SWand SW(also including SW, SW, SWand SWhereafter) that perform switching in a positive mode for generating a positive side of an output current; and two switching elements SWand SW(also including SW, SW, SWand SWhereafter) that perform switching in a negative mode for generating a negative side of the output current. The control part generates a control signal for controlling the output current within a hysteresis width with respect to a current command value, supplies the control signal to the elements SWand SWin the positive mode and supplies the control signal to the elements SWand SWin the negative mode. When the current command value crosses zero, the control part 20 performs switching mode changeover of the positive mode and the negative mode.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a three-level power converter.

  It is known that a power generation device (for example, a solar battery) or a power storage device in a consumer is connected as a distributed power source to a commercial power system of an electric power company through a power conditioner system (PCS). The power conditioner system includes an inverter (power converter) in order to convert DC power from a distributed power source into AC power equivalent to three-phase AC power of a commercial power system.

  As this type of inverter, a two-level inverter having six switching elements connected in a three-phase bridge is known. A three-level inverter having 12 switching elements (that is, four switching elements that are doubled for each phase) is also known. The three-level type inverter can reduce higher harmonics and reduce the ripple than the two-level type inverter.

  As a control method for this type of inverter, a PWM control method, a vector control method, and the like are known. Patent Document 1 discloses a three-level inverter using a PWM control method.

  As a control method for the two-level inverter, there is a hysteresis comparator control method. According to the hysteresis comparator control method, the response performance can be improved and the ripple can be reduced. Patent Document 2 discloses a two-level inverter using a hysteresis comparator system.

JP-A-64-47277 Japanese Patent No. 5493778

  The inventors of the present application try to apply a hysteresis comparator control system as described in Patent Document 2 to a three-level inverter as described in Patent Document 1.

  In the three-level inverter, for each phase, two positive mode switching elements are exclusively switched in the positive switching mode for generating the positive side of the output current, and the remaining in the negative switching mode for generating the negative side of the output current. These two negative mode switching elements are exclusively switched.

  Even if the hysteresis comparator control method for the two-level type inverter is simply applied to the three-level type inverter, the positive switching mode by the two positive mode switching elements and the negative switching by the two negative mode switching elements Switching mode to mode is not properly performed.

  Therefore, an object of the present invention is to provide a three-level type power conversion device to which the hysteresis comparator control method is suitably applied.

  The power converter of the present invention is a three-level type three-phase inverter unit that converts DC power into AC power, and performs switching exclusively in a positive switching mode that generates the positive side of the output current for each phase. A three-phase inverter section having two switching elements for positive mode and two switching elements for negative mode that perform switching exclusively in a negative switching mode that generates a negative side of the output current, and output current for each phase A control signal for controlling the sinusoidal current command value within the first hysteresis width is generated, and the control signal is supplied to the two positive mode switching elements in the positive switching mode, and the control signal is supplied in the negative switching mode. A control unit of a hysteresis comparator system that supplies two negative mode switching elements. DOO to, when the current command value is zero-crossing, for switching the mode switching between the positive switching mode and negative switching mode.

  According to this power converter, switching mode switching is performed when the current command value is zero-crossed for hysteresis comparator control, so control can be performed well even if hysteresis comparator control is used for a three-level power converter. It is.

  Incidentally, the inventors of the present application disclosed in Patent Document 2 that the switching loss of one phase is reduced in a predetermined period near the peak of a large current in a two-level three-phase inverter using hysteresis comparator system control for the purpose of reducing switching loss. Is forcibly stopped and the output power is adjusted by switching in the other two phases (hereinafter referred to as forced switching stop control). An attempt was made to apply this forced switching stop control to a three-level three-phase inverter using a hysteresis comparator control system, but an overcurrent occurred during the forced switching stop control.

  Therefore, for each phase, the above-described control unit does not depend on the control signal for a predetermined period including the time point of the positive peak value of the current command value, and does not depend on the control signal. The two negative modes are forcibly turned on and the other are forcibly turned off, and only for a predetermined period including the time point of the negative peak value of the current command value without depending on the control signal. Forcible switching stop control that forcibly turns on one of the switching elements connected to the low-potential side input and forcibly turns off the other is performed. During the forced switching stop control, the output current is a current command value. In contrast, the forced switching stop control may be terminated when the second hysteresis width is larger than the first hysteresis width.

  According to this, during the forced switching stop control of any one of the three phases, when the output current deviates from the second hysteresis width wider than the first hysteresis width with respect to the current command value, Since the forced switching stop control of the phase is terminated, the occurrence of overcurrent can be suppressed.

  In addition, the above-described control unit is configured to input, for each phase, a high-potential-side input of the two positive-mode switching elements for a predetermined period including the time point of the positive peak value of the current command value without depending on the control signal. The two negative modes are forcibly turned on and the other are forcibly turned off, and only for a predetermined period including the time point of the negative peak value of the current command value without depending on the control signal. Forcible switching stop control that forcibly turns on one of the switching elements connected to the low-potential side input and forcibly turns off the other is performed. During the forced switching stop control, the output current is a current command value. In contrast, when the second hysteresis width is larger than the first hysteresis width, the forced switching stop control is continued and the forced switching stop control is performed. It may be in a form for switching mode switching prior to the zero crossing point of the current command value in the stomach phase.

  According to this, during the forced switching stop control of any one of the three phases, when the output current deviates from the second hysteresis width wider than the first hysteresis width with respect to the current command value, The forced switching stop control of the phase is continued, and the switching mode switching is performed prior to the zero crossing time point of the current command value in the other phase where the forced switching stop control is not performed, so that the occurrence of overcurrent can be suppressed.

  The three-phase inverter unit described above includes, for each phase, a first switching element connected between the high-potential side input and the corresponding phase output, and the corresponding phase output and the low-potential side input. Third and fourth switching elements connected in series between the connected second switching element, a neutral point input intermediate between the high potential side input and the low potential side input, and the corresponding phase output And the first and third switching elements are the two positive mode switching elements, and the second and fourth switching elements are the two negative mode switching elements. Good.

  Further, the above-described three-phase inverter unit includes, for each phase, the first and fourth switching elements connected in series between the high potential side input and the corresponding phase output, the corresponding phase output and the low potential. From the connection point between the third and second switching elements connected in series in series with the side input and the third and second switching elements, the intermediate point between the high potential side input and the low potential side input A first neutral point clamp diode forward-connected toward the sex point input, and a second forward-connected from the neutral point input toward the connection point between the first and fourth switching elements. A neutral point clamp diode, wherein the first and third switching elements are the two positive mode switching elements described above, and the second and fourth switching elements are the two negative mode switching elements described above. It may be in form

  In addition, the above-described control unit is configured to input, for each phase, a high-potential-side input of the two positive-mode switching elements for a predetermined period including the time point of the positive peak value of the current command value without depending on the control signal. The two negative modes are forcibly turned on and the other are forcibly turned off, and only for a predetermined period including the time point of the negative peak value of the current command value without depending on the control signal. Forcible switching stop control that forcibly turns on one of the switching elements connected to the low-potential side input and forcibly turns off the other is performed. During the forced switching stop control, the output current is a current command value. On the other hand, when the second hysteresis width is larger than the first hysteresis width, the first function for terminating the forced switching stop control and the forced switching stop control are continued. And a second function of switching the switching mode prior to the zero crossing point of the current command value in the phase where the forced switching stop control is not performed, so that the efficiency of the three-phase inverter unit is increased. It may be a form in which either one of the first function and the second function is selected and executed.

  For example, consider a case where the AC output current of the three-phase inverter unit is large. At this time, if the first function for ending the self-phase forced switching stop control is selected, switching loss is increased by resuming switching in the vicinity of the current peak, and efficiency is expected to decrease. On the other hand, when the second function for switching the switching mode prior to the zero crossing point of the current command value is selected in the other phase in which the forced switching stop control of the own phase is continued and the forced switching stop control is not performed, Since the current of the other phase is relatively small, it is expected that the switching loss is relatively small and the efficiency is relatively high.

  The efficiency of the three-phase inverter unit is based on the DC input voltage, DC input current (ie, DC power supply voltage and current), AC output voltage, and AC output current (ie, power system voltage and current) of the three-phase inverter unit. Or based on the DC input power of the three-phase inverter unit (that is, the power of the DC power source), the AC output power (that is, the power of the power system), and further, the temperature of the three-phase inverter unit, the environmental temperature, etc. It can be determined taking into account the parameters.

  ADVANTAGE OF THE INVENTION According to this invention, the three-level type power converter device which applied the hysteresis comparator control system suitably can be provided.

It is a circuit diagram which shows the power converter device which concerns on the 1st-3rd embodiment of this invention. It is a circuit block diagram which shows the control part of 1st Embodiment. It is explanatory drawing of hysteresis comparator system control. It is a figure which shows each part waveform of the control part of 1st Embodiment. It is a figure which shows the simulation result of the power converter device of 1st Embodiment. It is a figure which expands and shows the U-phase waveform in FIG. It is a circuit block diagram which shows the control part of 2nd Embodiment. It is explanatory drawing of forced switching stop control. It is explanatory drawing of forced switching stop control. It is a figure which shows each part waveform of the control part of 2nd Embodiment. It is a figure which shows the simulation result of a power converter device which is provided with forced switching stop control and is not provided with forced switching stop termination control. It is a figure which expands and shows the U-phase waveform in FIG. It is a figure which shows the simulation result of the power converter device of 2nd Embodiment. It is a figure which expands and shows each part waveform in FIG. It is a circuit block diagram which shows the control part of 3rd Embodiment. It is a figure which shows each part waveform of the control part of 3rd Embodiment. It is a figure which shows the simulation result of the power converter device of 3rd Embodiment. It is a figure which expands and shows each part waveform in FIG. It is a circuit diagram which shows the modification of the three-phase inverter part shown in FIG. It is a circuit diagram which shows the modification of the three-phase inverter part shown in FIG.

DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals.
[First Embodiment]

FIG. 1 is a circuit diagram showing a power conversion device according to the first embodiment of the present invention. A power converter 1 shown in FIG. 1 is for connecting a DC power supply 2 to a power system 3. The power converter 1 converts DC power from the DC power source 2 into three-phase AC power. Power conversion apparatus 1 includes a three-phase inverter unit 10, a control unit 20, and a filter consisting of an inductor L and a capacitor C, and the neutral point clamp capacitors C _N, current transformer (current detector) and CT, instrument Transformer (voltage detector) VT.

The three-phase inverter unit 10 converts DC power from the DC power source 2 into three-phase AC power, and supplies the three-phase AC power to the power system 3 via a filter including an inductor L and a capacitor C. The three-phase inverter unit 10 is a three-level inverter having four switching elements for each phase, that is, twelve switching elements in three phases. Specifically, the three-phase inverter unit 10 includes the U-phase first to fourth switching elements SW _U1 , SW _U2 , SW _U3 , SW _U4 , and the V-phase first to fourth switching elements SW _V1 , SW. _V2 , SW _V3 , SW _V4 , and W-phase first to fourth switching elements SW _W1 , SW _W2 , SW _W3 , SW _W4 . An example of the switching elements _{SW U1 ~SW U4, SW V1 ~SW} V4, SW W1 ~SW W4 but is IGBT (Insulated Gate Bipolar Transistor), it is not limited thereto. Since the configuration of each phase is the same, the configuration of the U phase will be described below, and the description of the V phase and the W phase will be omitted.

Specifically, the first switching element SW _U1 is connected between the high potential side DC input power line L _H and the U-phase AC output power line L _U, and the second switching element SW _U2 is The phase AC output power line L _U and the low potential side DC input power line L _L are connected. More specifically, the collector terminal of the first switching element SW _U1 is connected to the high potential side DC input power line L _H, the emitter terminal of the first switching element SW _U1 and the second switching element SW _U2 Are connected to the U-phase AC output power line L _U , and the emitter terminal of the second switching element SW _U2 is connected to the low potential side DC input power line L _L.

Further, the third switching element SW _U3 and the fourth switching element SW _U4 are two neutral points connected in series between the high potential side DC input power line L _H and the low potential side DC input power line L _L. The neutral point input power line L _N between the clamp capacitors C _N , in other words, the neutral point input power line L _N having an intermediate potential between the high potential side DC input power line L _H and the low potential side DC input power line L _L. And the U-phase AC output power line L _U are connected in series in opposite directions. More specifically, the emitter terminal of the third switching element SW _U3 is connected to the neutral point input power line _LN , and the collector terminal of the third switching element SW _U3 is the fourth switching element SW _U4. of which is connected to the collector terminal, an emitter terminal of the fourth switching element SW _U4 is connected to a U-phase AC output power line L _U.

The first to fourth switching elements _{SW U1, SW U2, SW U3} , SW U4, feedback diode (freewheeling diode, freewheeling diodes, also referred to as a freewheeling _{diode) D U1, D U2, D} U3, D U4 parallel It is connected to the. Specifically, the anode terminals of the feedback diodes D _U1 , D _U2 , D _U3 , D _U4 are each connected to the emitter terminal, and the cathode terminal is connected to the collector terminal.

Gate signals (control signals) G _U1 , G _U2 , G _U3 , and G _U4 from the control unit 20 are input to gate terminals of the first to fourth switching elements SW _U1 , SW _U2 , SW _U3 , and SW _U4. The

In the present embodiment, the first switching element SW _U1 and the third switching element SW _U3 are exclusively switched to generate the positive side of the U-phase output current (positive switching mode). That is, the first switching element SW _U1 and the third switching element SW _U3 are two switching elements for the positive mode.

On the other hand, when the second switching element SW _U2 and the fourth switching element SW _U4 are exclusively switched, the negative side of the U-phase output current is generated (negative switching mode). That is, the second switching element SW _U2 and the fourth switching element SW _U4 are two negative mode switching elements.

The control unit 20 controls the inverter unit 10 using a hysteresis comparator method. Specifically, the control unit 20 outputs the output currents I _U , I _V , I _W of each phase of the inverter unit 10 to the sine wave current command values I _CU , I _CV , I _CW for each phase. Gate signals G _{U1 to} G _U4 , G _{V1 to} G _V4 , and G _{W1 to} G _W4 that are controlled within a predetermined hysteresis width ± ΔI _H1 are created, and are generated as switching elements SW _{U1 to} SW _U4 , The power is supplied to SW _{V1 to} SW _V4 and SW _{W1 to} SW _W4 .

  FIG. 2 is a circuit block diagram of an example of the control unit 20. The control unit 20 shown in FIG. 2 includes a phase voltage conversion unit 101, a current command value creation unit 102, a first hysteresis width setting unit 103, a first hysteresis upper limit value calculation unit 104, and a first hysteresis lower limit value calculation unit. 105, a first upper limit comparison unit 106, a first lower limit comparison unit 107, a main gate signal generation unit 108, a positive / negative phase region determination unit 109, and an all gate signal generation unit 110. The first upper limit comparison unit 106 and the first lower limit comparison unit 107 constitute a hysteresis comparator.

The phase voltage conversion unit 101 converts the line voltages V _UV , V _VW , and V _WU of the three-phase power system 3 measured using the instrument transformer VT into phase voltages V _U , V _V , and V _W.

Current command value preparing section 102 includes a phase information of the phase voltages _{V U, V V, V W} from the phase-voltage converter 101, based on the current amplitude command _{I P} commanded from the outside, the 3-phase output current _{I U, I V,} a sinusoidal current command value _I CU for _{I W, I CV,} thereby creating and outputting _{I CW.} 3 and 4 show an example of the U phase. Since FIG. 3 is an enlarged view, the current command value I _CU appears to be a straight line, but is actually a sine wave as shown in FIG. The current amplitude command _IP is common to the three phases. As is well known in the case of three-phase alternating current, the phases of the U phase, the V phase, and the W phase are only delayed by 120 degrees each, so that the phase voltage of one phase (for example, the phase voltage V _{U of the} U phase) The phase of the V phase and the W phase may be calculated by detecting the phase and delaying the phase by 120 degrees.

The first hysteresis width setting unit 103 sets a predetermined first hysteresis width ± ΔI _H1 for the sinusoidal current command values I _CU , I _CV , and I _CW for hysteresis comparator control. This is common to the three phases in this example.

The first hysteresis upper limit calculation unit 104 is based on the current command values I _CU , I _CV , I _CW from the current command value creation unit 102, and the first hysteresis width + ΔI _H1 from the first hysteresis width setting unit 103. Then, as shown in the following equation, the three-phase first hysteresis upper limit values I _H1U , I _H1V , and I _H1W are calculated and output.
I _H1U = I _CU + ΔI _H1
I _H1V = I _CV + ΔI _H1
I _H1W = I _CW + ΔI _H1

The first hysteresis lower limit value calculation unit 105 sets the current command values I _CU , I _CV , I _CW from the current command value creation unit 102 and the first hysteresis width −ΔI _H1 from the first hysteresis width setting unit 103. Based on this, as shown in the following equation, the three-phase first hysteresis lower limit values I _L1U , I _L1V , and I _L1W are calculated and output.
I _L1U = I _CU −ΔI _H1
I _L1V = I _CV −ΔI _H1
I _L1W = I _CW −ΔI _H1

The first upper limit comparison unit 106 outputs the output currents I _U , I _V , I _{W of} the three-phase inverter unit 10 measured using the current transformer CT, and the first hysteresis upper limit value from the first hysteresis upper limit value calculation unit 104. The values I _H1U , I _H1V and I _H1W are respectively compared.

The first lower limit comparison unit 107 outputs the output currents I _U , I _V and I _{W of} the three-phase inverter unit 10 measured using the current transformer CT, and the first hysteresis lower limit value from the first hysteresis lower limit value calculation unit 105. The values I _L1U , I _L1V and I _L1W are respectively compared.

The main gate signal generator 108, based on the comparison result of the first upper limit comparison unit 106 and the first lower limit comparison unit 107, the switching element _SW U1 _{to SW} U4 of the three-phase inverter unit _{10, SW V1 ~SW V4, SW} W1 Main gate signals Q _U , QX _U , Q _V , QX _V , Q _V , and QX _V for turning on and off SW _W4 are created. Each main gate signal Q _U , QX _U , Q _V , QX _V , Q _W , QX _W is a pulse signal that takes a logical value of 1 or 0. Since the main gate signal of each phase is substantially the same except for the phase shift, the U-phase main gate signal will be described below. As shown in FIG. 3 and FIG. 4, the main gate signal generator 108 is configured so that the output current I _U falls within a predetermined hysteresis width ± ΔI _{H1 with} respect to the sine wave current command value I _CU . Main gate signals Q _U and QX _U for turning on / off the switching elements SW _{U1 to} SW _U4 are created.

  The positive / negative phase region determination unit 109 determines a positive phase region where the current command value is a positive value and a negative phase region where the current command value is a negative value. In other words, the positive / negative phase region determination unit 109 determines the zero crossing point of the current command value.

Based on the determination result of the positive / negative phase region determination unit 109, the all gate signal generation unit 110 outputs the main gate signals Q _U , QX _U , Q _V , QX _V , Q _W , QX _W from the main gate signal generation unit 108. Gate signals G _{U1 to} G _U4 , G _{V1 to} G _V4 , and G _{W1 to} G that turn on and off the switching elements SW _{U1 to} SW _U4 , SW _{V1 to} SW _V4 , SW _{W1 to} SW _W4 of the three-phase inverter unit 10, respectively. Assign to _W4 . Since the gate signal of each phase is substantially the same except for the phase shift, the U-phase gate signal will be described below.

As shown in FIG. 4, the gate total gate signal generator 110, a positive phase region where the current command value I _CU is positive value, the main gate signal Q _U, turning on or off the first switching element SW _U1 allocated to the signal _{G U1,} the main gate signals QX _U, assigned to the third gate signal _{G U3} to the on-off switching element _{SW U3.} At this time, the gate signal _{G U2} for the second switching element _{SW U2,} assign the OFF signal always to the gate signal _{G U4} for a fourth switching element _{SW U4,} it allocates the always-on signal.

The total gate signal generator 110 assigns the negative phase region the current command value I _CU is negative value, the main gate signal Q _U, the gate signal G _U4 to the fourth on-off switching element SW _U4 the main gate signal QX _U, assigned to the gate signal _{G U2} for turning on and off the second switching element _{SW U2.} At this time, the gate signal _{G U1} for the first switching element _{SW U1,} assign the OFF signal always to the gate signal _{G U3} for the third switching element _{SW U3,} allocates the always-on signal.

The all-gate signal generator 110 assigns the gate signals G _U1 and G _U2 of the main switching elements SW _U1 and SW _U2 connected to the high potential side DC input power line L _H and the low potential side DC input power line L _L. performs only as a gate signal _{G U3, G U4} neutral phase switching elements _SW U3, _{SW U4} which is connected to the neutral point input power line _{L N,} the inverted signal (NOT signal of the gate signal _{G U1, G U2,} exclusive Target signal) may be used.

In other words, the all gate signal creation unit 110 converts the main gate signals Q _U and QX _U into the first switching element SW that is a positive mode switching element in the positive phase region where the current command value I _CU is a positive value. _In the negative phase region in which the current command value I _CU is a negative value assigned to each of _U1 and the third switching element SW _U3 (positive switching mode), the main gate signals Q _U and QX _U are _Assigned respectively to a certain second switching element SW _U2 and fourth switching element SW _U4 (negative switching mode). That is, the control unit 20 switches the switching mode between the positive switching mode and the negative switching mode when the current command value _{ICU crosses} zero.

As described above, according to the power conversion device 1 of the first embodiment, when the current command values I _CU , I _CV , and I _CW are zero- _crossed for hysteresis comparator control, the positive switching mode and the negative switching mode are negative. Since the switching mode switching to the switching mode is performed, the control can be satisfactorily performed even when the hysteresis comparator system control is used for the control unit 20 for the three-level type three-phase inverter unit 10.

FIG. 5 is a diagram illustrating a simulation result of the power conversion device according to the first embodiment, and FIG. 6 is a diagram illustrating an enlarged U-phase waveform in FIG. 5. According to FIG.5 and FIG.6, the favorable output current _IU , _IV , _IW waveform was obtained.
[Second Embodiment]

  1 A of power converter devices which concern on the 2nd Embodiment of this invention differ from 1st Embodiment by the structure provided with control part 20A instead of the control part 20 in the power converter device 1 shown in FIG. The control unit 20A is forcibly turning on / off the switching element for each phase for a predetermined period including the time point of the peak value of the current command value for each phase without depending on the above-described hysteresis comparator control. Different from the control unit 20 of the first embodiment.

FIG. 7 is a circuit block diagram of an example of the control unit 20A. In addition to the control unit 20 shown in FIG. 2, the control unit 20A shown in FIG. 7 further includes a zero-cross comparison unit 201, a counter 202, a phase determination unit 203, a forced switching stop signal creation unit 204, and a second hysteresis width. A setting unit 303, a second hysteresis upper limit value calculation unit 304, a second hysteresis lower limit value calculation unit 305, a second upper limit comparison unit 306, a second lower limit comparison unit 307, and a second hysteresis width over determination unit 308, , A forced switching stop continuation determination unit 309 and a main gate signal output unit 310 are provided.
(Forced switching stop control)

As shown in FIG. 8, the zero-cross comparison unit 201 compares the one-phase phase voltage (in this example, the U-phase voltage V _U ) from the phase voltage conversion unit 101 with a reference value of 0 V (volts), When _VU is negative, a logical value 1 is output, and when VU is 0 V or higher, a logical value 0 is output.

Counter 202, for each one cycle of the phase voltage V _U, i.e. for every one period of the output of the zero crossing comparator 201, from the falling edge time of the output of the zero crossing comparator 201, the count value of the falling edge point 0 To start counting.

Here, as an example, the phase determination unit 203 uses a count value for one cycle previously counted by the counter 202 and divides the value by 360 to calculate a count value per degree. Then by multiplying the count value of the current count value per above once the counter to determine the current phase of the phase voltage V _U [degrees]. Further, by adding a desired power factor for operating the three-phase inverter device, the phase of the current command value I _CU corresponding to the power factor (this is the same as the phase of the output current I _U ) is obtained. For example, if the power factor is 1, the phase voltage _VU and the current command value _ICU are in the same phase. The phases of the V phase and the W phase are obtained by delaying each by 120 degrees from the phase of the U phase.

As shown in FIG. 9, the forced switching stop signal creation unit 204 will be described based on the phase obtained by the phase determination unit 203 by taking the U phase as an example. The positive peak value time point of the current command value I _CU is determined. The first and third switching elements SW _U1 , which are the above-described two positive mode switching elements, do not depend on the main gate signals Q _U and QX _U from the main gate signal generation unit 108 for a predetermined period including. a first switching element SW _U1 of the SW _U3 forcibly force off the third switching element SW _U3 with turning on and including the time of the negative peak value of the current command value I _CU predetermined period, the main gate signal Q _U from the main gate signal generator _108, irrespective of the QX _U, the second and fourth switching a two negative mode switching element having the above-described Forcibly turn off the fourth switching element _{SW U4} together forcibly turn on the second switching element _{SW U2} of the element _SW U2, _{SW U4,} forced stop signal _SQ U, creates a SQX _U. Similarly, the forced stop signals SQ _V and SQX _V are generated even in the _V phase, and the forced stop signals SQ _W and SQX _W are generated also in the W phase. The forced stop signals SQ _U , SQX _U , SQ _V , SQX _V , SQ _W , SQX _W are pulse signals that take a logical value of 1 or 0.

  The predetermined period is, for example, a period of 60 degrees represented by a phase width. The predetermined period is not limited to a period of 60 degrees, and may be a period that is greater than 0 degrees and less than or equal to 60 degrees.

As a result, one of the three-phase switching elements is forcibly turned on / off, and the remaining two-phase switching elements are controlled by hysteresis comparator control.
(Forced switching stop termination control)

The second hysteresis width setting unit 303 sets a predetermined second hysteresis width ± ΔI _H2 for the current command values I _CU , I _CV , and I _CW . This is common to the three phases in this example. The second hysteresis width ± ΔI _H2 is wider than the first hysteresis width ± ΔI _H1 . FIG. 10 shows an example of the U phase.

The second hysteresis upper limit calculation unit 304 is based on the current command values I _CU , I _CV , I _CW from the current command value creation unit 102, and the second hysteresis width + ΔI _H2 from the second hysteresis width setting unit 303. As shown in the following equation, the three-phase second hysteresis upper limit values I _H2U , I _H2V , and I _H2W are calculated and output.
I _H2U = I _CU + ΔI _H2
I _H2V = I _CV + ΔI _H2
I _H2W = I _CW + ΔI _H2

The second hysteresis lower limit calculation unit 305 is based on the current command values I _CU , I _CV , I _CW from the current command value creation unit 102, and the second hysteresis width −ΔI _H2 from the second hysteresis width setting unit 303. Then, as shown in the following equation, the three-phase second hysteresis lower limit values I _L2U , I _L2V , and I _L2W are calculated and output.
I _L2U = I _CU −ΔI _H2
I _L2V = I _CV −ΔI _H2
I _L2W = I _CW −ΔI _H2

The second upper limit comparison unit 306 outputs the output currents I _U , I _V , I _{W of} the three-phase inverter unit 10 measured using the current transformer CT, and the second hysteresis upper limit value from the second hysteresis upper limit calculation unit 304. I _H2U , I _H2V , and I _H2W are respectively compared.

The second lower limit comparing unit 307 outputs the output currents I _U , I _V , I _{W of} the three-phase inverter unit 10 measured using the current transformer CT, and the second hysteresis lower limit value from the second hysteresis lower limit value calculating unit 305. I _L2U , I _L2V , and I _L2W are respectively compared.

Based on the comparison results of the second upper limit comparison unit 306 and the second lower limit comparison unit 307, the second hysteresis width over determination unit 308 converts the output currents I _U , I _V , and I _W into the second hysteresis upper limit values I _H2U , I _H2V, when more than _{I H2W,} or the output current _{I U, I V, I W} is a second hysteresis limit value _{I L2U, I L2V,} when below _{I L2W,} the output current _{I U, I V, I W} Is deviated (over) from the second hysteresis width ± ΔI _H2 (for example, time point t _{U in} FIG. 10).

The forced switching stop continuation determination unit 309 determines the forced switching based on the determination result of the second hysteresis width over determination unit 308 if the output currents I _U , I _V , and I _W are within the second hysteresis width ± ΔI _H2. It is determined that the stop can be continued, and the forced stop signals SQ _U , SQX _U , SQ _V , SQX _V , SQ _W , SQX _W from the forced switching stop signal creation unit 204 are supplied to the main gate signal output unit 310. On the other hand, when the output currents I _U , I _V , I _W deviate from the second hysteresis width ± ΔI _H2 (over), the forced switching stop continuation determination unit 309 determines that the forced switching stop cannot be continued, and forcibly stops switching. The forced stop signals SQ _U , SQX _U , SQ _V , SQX _V , SQ _W , SQX _W from the signal creation unit 204 are not supplied to the main gate signal output unit 310.

As shown in FIG. 10, the main gate signal output unit 310 includes signals Q _U , QX _U , Q _V , QX _V , Q _W , QX _W from the main gate signal creation unit 108 and a forced switching stop continuation determination unit. Based on the forced stop signals SQ _U , SQX _U , SQ _V , SQX _V , SQ _W , SQX _W from 309, the forced stop signals SQ _U , SQX _U , SQ _V , SQX _V , SQ _W , SQX _W are supplied In the period when the forced stop signals SQ _U , SQX _U , SQ _V , SQX _V , SQ _W , SQX _W are not supplied, the signals Q _U , QX _U , Q _V , QX _V , Q _W , QX _W Are supplied as main gate signals Q _U , QX _U , Q _V , QX _V , Q _W , QX _W to the positive / negative phase region determination unit 109.

Thereafter, as described above, the main gate signals Q _U , QX _U , Q _V , QX _V , Q _W , QX _W from the main gate signal output unit 310 are obtained by the positive / negative phase region determination unit 109 and the all gate signal generation unit 110. the switching element _{SW U1 ~SW U4, SW V1 ~SW} V4, SW W1 ~SW W4 gate signal to each on-off _G U1 _~G U4 of the three-phase inverter unit _{10, G V1 ~G V4, G} W1 ~ assigned to the G _W4.

  Even in the power conversion device 1A of the second embodiment, the same advantages as those of the power conversion device 1 of the first embodiment can be obtained.

By the way, when the forced switching stop control for the two-level type three-phase inverter described in Patent Document 2 is applied to the three-level type three-phase inverter, that is, in the power conversion device 1A, the second hysteresis width setting unit 303, Hysteresis upper limit calculation unit 304, second hysteresis lower limit calculation unit 305, second upper limit comparison unit 306, second lower limit comparison unit 307, second hysteresis width over determination unit 308, and forced switching stop continuation determination If the forced stop signal from the forced switching stop signal creation unit 204 is directly supplied to the main gate signal output unit 310 without the forced switching stop termination control by the unit 309, an overcurrent occurs during the forced switching stop control. (e.g., time _{t U} in FIG. 10. Note that the overcurrent at time _{t W} is strong in the other W-phase It is due to the switching stop control.).

However, according to the power conversion device 1A of the second embodiment, the second hysteresis width setting unit 303, the second hysteresis upper limit value calculation unit 304, the second hysteresis lower limit value calculation unit 305, and the second upper limit comparison Unit 306, second lower limit comparison unit 307, second hysteresis width over determination unit 308, and forced switching stop continuation determination unit 309, and forced switching stop termination control is provided. For example, during forced switching stop control of the U phase shown in FIG. 10, the output currents I _U , I _V , I _W have a first hysteresis width ± ΔI _{H1 with} respect to the current command values I _CU , I _CV , I _CW . Since the self-phase forced switching stop control is terminated when it deviates from the wider second hysteresis width ± ΔI _H2 (for example, time point t _{U in} FIG. 10), the overcurrent Can be suppressed.

FIG. 11 is a diagram illustrating a simulation result of the power conversion device that includes forced switching stop control and does not include forced switching stop termination control, and FIG. 12 is an enlarged view of the U-phase waveform in FIG. 11. Moreover, FIG. 13 is a figure which shows the simulation result of the power converter device of 2nd Embodiment, FIG. 14 is a figure which expands and shows each part waveform in FIG. According to FIG. 11 and 12, overcurrent had occurred more than a first hysteresis limit I _H1U at time t _U of the U-phase forced switching stop control in. Incidentally, the overcurrent at time t _W is due to the forcible switching stop control of other W-phase. On the other hand, according to FIGS. 13 and 14, the occurrence of overcurrent could be suppressed by terminating the self-phase forced switching stop control at the time point tU during the _U -phase forced switching stop control.
[Third Embodiment]

  The power conversion device 1B according to the third embodiment of the present invention is different from the second embodiment in a configuration including a control unit 20B instead of the control unit 20A in the power conversion device 1A illustrated in FIG. During the forced switching stop control, the control unit 20B continues the self-phase forced switching stop control when the output current deviates from the second hysteresis width wider than the first hysteresis width with respect to the current command value. The control unit 20A of the second embodiment is different from the control unit 20A of the second embodiment in that the switching mode switching is performed prior to the zero crossing point of the current command value in the other phase where the forced switching stop control is not performed.

  FIG. 15 is a circuit block diagram of an example of the control unit 20B. A control unit 20B illustrated in FIG. 15 includes a final determination unit 311 instead of the forced switching stop continuation determination unit 309 in the control unit 20A illustrated in FIG.

First, the main gate signal output unit 310 is directly supplied with the forced stop signals SQ _U , SQX _U , SQ _V , SQX _V , SQ _W , SQX _W from the forced switching stop signal creation unit 204, as shown in FIG. In the period when the forced stop signals SQ _U , SQX _U , SQ _V , SQX _V , SQ _W , SQX _W are supplied, the forced stop signals SQ _U , SQX _U , SQ _V , SQX _V , SQ _W , SQX _W In the non-supply period, the signals Q _U , QX _U , Q _V , QX _V , Q _W , QX _W are used as main gate signals Q _U , QX _U , Q _V , QX _V , Q _W , QX _W , and positive / negative phase region determination unit 109.

For example, at the time point t _U during the U-phase forced switching stop control (identified from the forced stop signal from the forced switching stop signal creation unit 204), the final determination unit 311 outputs the output current I _U to the current command value I _CU . When deviating from the second hysteresis width ± ΔI _H2 wider than the first hysteresis width ± ΔI _H1 (determination by the second hysteresis width over determination unit 308), the forced switching stop control of the own phase is continued and forced switching is performed. In the V phase where the stop control is not performed, the switching mode switching between the positive switching mode and the negative switching mode described above is performed prior to the zero crossing time point of the current command value I _CV from the positive / negative phase region determination unit 109. Commands all gate signal generator 110.

Similarly, the final determination unit 311 performs the self-phase forced switching stop control when, for example, the output current _IV is out of the second hysteresis width ± ΔI _H2 at the time point t _V during the _V -phase forced switching stop control. The switching mode between the positive switching mode and the negative switching mode described above precedes the zero-crossing time point of the current command value I _CW from the positive / negative phase region determination unit 109 in the W phase that is continued and the forced switching stop control is not performed. Commands all gate signal generation unit 110 to perform switching.

Similarly, the final determination unit 311 performs the self-phase forced switching stop control when, for example, the output current I _W deviates from the second hysteresis width ± ΔI _H2 at the time point t _W during the _W -phase forced switching stop control. The switching mode between the positive switching mode and the negative switching mode described above precedes the zero crossing time point of the current command value I _CU from the positive / negative phase region determination unit 109 in the U phase that is continued and is not subjected to forced switching stop control. Commands all gate signal generation unit 110 to perform switching.

Thereafter, as described above, the main gate signals Q _U , QX _U , Q _V , QX _V , Q _W , QX _W from the main gate signal output unit 310 are obtained by the positive / negative phase region determination unit 109 and the all gate signal generation unit 110. the switching element _{SW U1 ~SW U4, SW V1 ~SW} V4, SW W1 ~SW W4 gate signal to each on-off _G U1 _~G U4 of the three-phase inverter unit _{10, G V1 ~G V4, G} W1 ~ assigned to the G _W4.

The power converter 1B according to the third embodiment can obtain the same advantages as the power converter 1A according to the second embodiment. That is, also in the power conversion device 1B of the third embodiment, during the forced switching stop control of any one of the three phases (for example, the U phase shown in FIG. 16), the output currents I _U , I _V , When I _W deviates from the second hysteresis width ± ΔI _H2 wider than the first hysteresis width ± ΔI _{H1 with} respect to the current command values I _CU , I _CV , I _CW (for example, time point t _{U in} FIG. 16). In addition to continuing the forced switching stop control of the own phase, the current command values I _CU , I _CV , and I _CW precede the zero crossing point in the other phase (for example, the V phase shown in FIG. 16) in which the forced switching stop control is not performed. Since switching mode switching is performed, the occurrence of overcurrent can be suppressed.

FIG. 17 is a diagram illustrating a simulation result of the power conversion device according to the third embodiment, and FIG. 18 is a diagram illustrating an enlarged waveform of each part in FIG. 17. 17 and 18, the self-phase forced switching stop control is continued at time t _U during the _U -phase forced switching stop control, and the current command value I _CV is zero-crossed in the V phase where the forced switching stop control is not performed. The occurrence of overcurrent could be suppressed by switching the switching mode prior to the time.

  The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, it has both the self-phase forced switching stop termination function shown in the second embodiment and the switching mode switching function of the other phase shown in the third embodiment so that the efficiency of the three-phase inverter unit is increased. In addition, any one of these functions may be selected and executed.

  For example, consider a case where the AC output current of the three-phase inverter unit is large. At this time, if the first function for ending the self-phase forced switching stop control is selected, switching loss is increased by resuming switching in the vicinity of the current peak, and efficiency is expected to decrease. On the other hand, when the second function for switching the switching mode prior to the zero crossing point of the current command value is selected in the other phase in which the forced switching stop control of the own phase is continued and the forced switching stop control is not performed, Since the current of the other phase is relatively small, it is expected that the switching loss is relatively small and the efficiency is relatively high.

  The efficiency of the three-phase inverter unit is based on the DC input voltage, DC input current (ie, DC power supply voltage and current), AC output voltage, and AC output current (ie, power system voltage and current) of the three-phase inverter unit. Or based on the DC input power of the three-phase inverter unit (that is, the power of the DC power source), the AC output power (that is, the power of the power system), and further, the temperature of the three-phase inverter unit, the environmental temperature, etc. It can be determined taking into account the parameters.

  In the present embodiment, the so-called A-NPC (advanced NPC) (also referred to as bidirectional NPC type) inverter configuration illustrated in FIG. 1 is illustrated as the three-level type three-phase inverter unit 10. The features of the present invention can also be applied to the so-called NPC type (Neutral Point Clamped) inverter configuration shown in FIG.

In this NPC type inverter unit, the three-phase inverter unit 10 includes U-phase first to fourth switching elements SW _U1 , SW _U2 , SW _U3 , SW _U4 , and V-phase first to fourth switching elements SW _V1. , SW _V2 , SW _V3 , SW _V4 , W-phase first to fourth switching elements SW _W1 , SW _W2 , SW _W3 , SW _W4 , U-phase first and second NPCs (neutral point clamps) ) Diodes D _U5 and D _U6 , first and second NPC diodes D _V5 and D _V6 for V phase, and first and second NPC diodes D _W5 and D _W6 for W phase. Since the configuration of each phase is the same, the configuration of the U phase will be described below.

Specifically, the first switching element SW _U1 and the fourth switching element SW _U4, are connected in order in series between the high potential side DC input power line L _H and U-phase AC output power line L _U The third switching element SW _U3 and the second switching element SW _U2 are sequentially connected in series between the U-phase AC output power line L _U and the low potential side DC input power line L _L. More specifically, the collector terminal of the first switching element SW _U1 is connected to the high potential side DC input power line L _H, the emitter terminal of the first switching element SW _U1 is the fourth switching element SW _U4 is connected to the collector terminal, an emitter terminal of the fourth switching element SW _U4 is connected to the AC output power U-phase line L _U. On the other hand, the collector terminal of the third switching element SW _U3 is connected to the U-phase AC output power line L _U , and the emitter terminal of the third switching element SW _U3 is connected to the collector terminal of the second switching element SW _U2. The emitter terminal of the second switching element SW _U2 is connected to the low potential side DC input power line L _L.

Further, the first NPC diode D _U5 has a connection point between the third and second switching elements SW _U3 and SW _U2 and an intermediate point between the high potential side DC input power line L _H and the low potential side DC input power line L _L. of which is connected between the neutral point input power line _{L N} having a potential, the second NPC diode _{D U6} includes a neutral input power line _{L N,} the first and fourth switching elements _SW U1, SW _It is connected between the connection points between _U4 . More specifically, the anode terminal of the first NPC diode D _U5 is connected to the connection point between the third and second switching elements SW _U3 and SW _U2 , and the cathode of the first NPC diode D _U5 . The terminal is connected to the neutral point input power line _LN . On the other hand, the anode terminal of the second NPC diode D _U6 is connected to the neutral point input power line L _N , and the cathode terminal of the second NPC diode D _U6 is connected to the first and fourth switching elements SW _U1 , It is connected to the connection point between SW _U4 .

Feedback diodes D _U1 , D _U2 , D _U3 , and D _U4 are connected in parallel to the first to fourth switching elements SW _U1 , SW _U2 , SW _U3 , and SW _U4 . Specifically, the anode terminals of the feedback diodes D _U1 , D _U2 , D _U3 , D _U4 are each connected to the emitter terminal, and the cathode terminal is connected to the collector terminal.

Gate signals (control signals) G _U1 , G _U2 , G _U3 , and G _U4 from the control unit 20 are input to gate terminals of the first to fourth switching elements SW _U1 , SW _U2 , SW _U3 , and SW _U4. The

Also in this embodiment, the first switching element SW _U1 and the third switching element SW _U3 are exclusively switched to generate the positive side of the U-phase output current (positive switching mode). That is, the first switching element SW _U1 and the third switching element SW _U3 are two switching elements for the positive mode.

On the other hand, when the second switching element SW _U2 and the fourth switching element SW _U4 are exclusively switched, the negative side of the U-phase output current is generated (negative switching mode). That is, the second switching element SW _U2 and the fourth switching element SW _U4 are two negative mode switching elements.

Further, in the present embodiment, as shown in FIG. 1, as the three-level type three-phase inverter unit 10, the third switching elements SW _U3 , SW _V3 , SW _W3 , the fourth switching elements SW _U4 , SW _V4 , SW _W4 , Is illustrated as an A-NPC type inverter configuration connected in series in the opposite direction. The feature of the present invention is that the third switching elements SW _U3 , SW _V3 , SW _W3 and the fourth The present invention is also applicable to an A-NPC inverter configuration using a so-called RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) in which switching elements SW _U4 , SW _V4 , and SW _W4 are connected in parallel in the opposite direction.

DESCRIPTION OF SYMBOLS 1,1A, 1B ... Power converter device, 2 ... DC power supply, 3 ... Electric power system, 10 ... Three-phase inverter part, 20, 20A, 20B ... Control part, 101 ... Phase voltage converter part, 102 ... Current command value preparation part DESCRIPTION OF SYMBOLS 103 ... 1st hysteresis width setting part 104 ... 1st hysteresis upper limit calculation part 105 ... 1st hysteresis lower limit value calculation part 106 ... 1st upper limit comparison part 107 ... 1st lower limit comparison part 108 ... Main gate Signal creation unit 109 ... Positive / negative phase region determination unit 110 110 All gate signal creation unit 201 ... Zero cross comparison unit 202 202 Counter 203 Phase determination unit 204 Forced switching stop signal creation unit 303 Second hysteresis Width setting unit, 304 ... second hysteresis upper limit value calculation unit, 305 ... second hysteresis lower limit value calculation unit, 306 ... second upper limit comparison unit, 307 ... second lower limit comparison unit, 3 8 ... second hysteresis width over determination unit, 309 ... forced switching halt continuation determination unit, 310 ... main gate signal output unit, 311 ... final determination section, L ... inductor, C ... Capacitor, C N _... neutral point clamp capacitors , CT ... current transformer (current detector), VT ... instrument transformer (voltage detector), L _H ... high potential side DC input power line, L _L ... low potential side DC input power line, L _N ... neutral point Input power line, L _U , L _V , L _W ... AC output power line, SW _{U1 to} SW _U4 , SW _{V1 to} SW _V4 , SW _{W1 to} SW _W4 ... First to fourth switching elements, D _{U1 to} D _U4 , D _{V1 ~D V4, D W1 ~D W4} ... feedback _{diode, D U5, D U6, D} V5, D V6, D W5, D W6 ... first and second NPC (neutral point clamped) diodes, _{G U ~G U4, G V1 ~G V4,} G W1 ~G W4 ... gate _{signal, Q U, QX U, Q} W, QX W, Q W, QX W ... main gate _{signal, SQ U, SQ U, SQ} V, SQ _V , SQ _W , SQ _W ... Forced stop signal, I _U , I _V , I _W ... Output current, I _P ... Current amplitude command, I _CU , I _CV , I _CW ... Current command value, I _H1U , I _H1V , I _H1W ... first hysteresis upper limit value, I _L1U , I _L1V , I _L1W ... first hysteresis lower limit value, I _H2U , I _H2V , I _H2W ... second hysteresis upper limit value, I _L2U , I _L2V , I _L2W : second hysteresis lower limit value, V _UV , V _VW , V _WU ... line voltage, V _U , V _V , V _W ... phase voltage.

Claims (5)

A three-level type three-phase inverter unit that converts DC power into AC power, and for each phase, two positive mode switching elements that perform switching exclusively in a positive switching mode that generates the positive side of the output current; The three-phase inverter unit having two negative mode switching elements that perform switching exclusively in a negative switching mode that generates the negative side of the output current;
For each phase, a control signal for controlling the output current within a first hysteresis width with respect to a sinusoidal current command value is generated, and in the positive switching mode, the control signal is used as the two positive mode switching elements. A control unit of a hysteresis comparator system that supplies the control signal to the two negative mode switching elements in the negative switching mode;
With
The control unit performs switching mode switching between the positive switching mode and the negative switching mode when the current command value crosses zero for each phase.
Power conversion device. The controller is
For each phase, one of the two positive mode switching elements connected to the high potential side input for a predetermined period including the time point of the positive peak value of the current command value without depending on the control signal. Forcibly turning on the other and forcibly turning off the other, and switching for the two negative modes for a predetermined period including the time point of the negative peak value of the current command value without depending on the control signal. Perform forced switching stop control to forcibly turn on one of the elements connected to the low potential side input and forcibly turn off the other,
During the forced switching stop control, when the output current deviates from a second hysteresis width wider than the first hysteresis width with respect to the current command value, the forced switching stop control is terminated.
The power conversion device according to claim 1. The controller is
For each phase, one of the two positive mode switching elements connected to the high potential side input for a predetermined period including the time point of the positive peak value of the current command value without depending on the control signal. Forcibly turning on the other and forcibly turning off the other, and switching for the two negative modes for a predetermined period including the time point of the negative peak value of the current command value without depending on the control signal. Perform forced switching stop control to forcibly turn on one of the elements connected to the low potential side input and forcibly turn off the other,
During the forced switching stop control, when the output current deviates from the second hysteresis width wider than the first hysteresis width with respect to the current command value, the forced switching stop control is continued and the forced switching The switching mode switching is performed prior to the zero crossing point of the current command value in a phase not performing stop control.
The power conversion device according to claim 1. The three-phase inverter unit is
A first switching element connected between the high potential side input and the corresponding phase output;
A second switching element connected between the corresponding phase output and the low potential side input;
Third and fourth switching elements connected in series between a neutral point input intermediate between the high potential side input and the low potential side input and the corresponding phase output;
With
The first and third switching elements are the two positive mode switching elements;
The second and fourth switching elements are the two negative mode switching elements;
The power converter device of any one of Claims 1-3. The three-phase inverter unit is
First and fourth switching elements connected in series between a high-potential side input and a corresponding phase output,
A third switching element and a second switching element connected in series between the corresponding phase output and the low potential side input;
A first neutral point clamp diode forward-connected from a connection point between the third and second switching elements toward a neutral point input intermediate between the high potential side input and the low potential side input When,
A second neutral point clamp diode forward-connected from the neutral point input to a connection point between the first and fourth switching elements;
With
The first and third switching elements are the two positive mode switching elements;
The second and fourth switching elements are the two negative mode switching elements;
The power converter device of any one of Claims 1-3.