JP2004357358A - Inverter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce switching loss while suppressing distortion in output voltage and output current. <P>SOLUTION: Based on PWM signals Du, Dv, and Dw which are acquired by comparing triangular wave signals to voltage command signals by a two-phase modulation method, corrective PWM signals Cu, Cv, and Cw are generated in which the period of 2×Tc acquired by adding two PWM cycles Tc before correction together, being a period in which the change rate of voltage command signal of each phase is relatively small, is taken as a corrective PWM cycle. The corrective PWM signal Cu is 1 (the switching element on an upper arm side is on) during the period of Tu in which pre-correction times Tu1 and Tu2 are added together, but is 0 (the switching element on a lower arm side is on) during the remaining period (2×Tc-Tu). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an inverter device that generates a PWM signal based on a voltage command signal.
[0002]
[Prior art]
Conventionally, a PWM inverter device has been used. This PWM inverter device generates a PWM signal by comparing a voltage command signal for commanding an output voltage (phase voltage) with a carrier signal such as a triangular wave signal, and drives each switching element forming an inverter circuit by the PWM signal. It is supposed to.
[0003]
[Problems to be solved by the invention]
This PWM inverter has the advantage that the output voltage (line voltage) can have a sinusoidal waveform, but on the other hand, the switching loss due to the on / off driving of the switching element increases, and the efficiency of the inverter decreases. The problem arises. To cope with this, it is effective to lower the frequency of the carrier wave signal. However, simply lowering the frequency causes distortion in the output voltage, and lowers the quality of the output voltage and thus the output current.
[0004]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an inverter device that can reduce switching loss while suppressing distortion of output voltage and output current.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, an inverter device according to claim 1 includes a plurality of switching elements, and based on a voltage command signal, an inverter circuit that outputs an AC voltage by turning off these switching elements. A PWM signal generating means for generating a PWM signal in which each PWM cycle includes a first period corresponding to a first on / off state of the switching element and a second period corresponding to a second on / off state of the switching element; A period in which a plurality of continuous PWM cycles are combined is referred to as a corrected PWM cycle, and the corrected PWM cycle has a time width corresponding to a first period in each of the plurality of continuous PWM cycles and a first ON / OFF of the switching element. The switch has a time width including a first period corresponding to a state and a second period in each of the plurality of continuous PWM cycles. Correction means for generating a correction PWM signal consisting of a second period corresponding to a second on / off state of the switching element, wherein at least one of the plurality of switching elements has a function corresponding to a time zone. It is characterized in that it is configured to be driven by using any one of the PWM signal and the corrected PWM signal.
[0006]
According to this configuration, the inverter circuit outputs an AC voltage according to the voltage command signal. In a certain time zone of the output voltage (phase voltage) (for example, a predetermined period that is predetermined as an angle range in which the rate of change is relatively small), a period obtained by combining a plurality of continuous PWM cycles is one. The corrected PWM cycle is reached, and the PWM frequency becomes an integral one of the basic PWM frequency before correction. If a time zone in which the rate of change of the output voltage (phase voltage) is relatively small is set as the time zone, waveform distortion is unlikely to occur even if the PWM frequency is lowered.
[0007]
On the other hand, in another time zone (for example, a predetermined period predetermined as an angle range in which the rate of change is relatively large), the PWM frequency is kept at the basic PWM frequency, so that the waveform distortion does not increase. Absent. Therefore, by appropriately setting the time zone, the waveform distortion can be reduced for the entire output voltage and output current, and the switching loss can be reduced by the decrease in the PWM frequency in a part of the period. The same operation and effect can be obtained for the inverter device according to the second aspect.
[0008]
The inverter device according to the third and fourth aspects includes an inverter circuit capable of outputting a three-phase AC voltage, and the inverter circuit is capable of outputting a three-phase AC voltage during a predetermined period in which the rate of change of the two-phase modulation and three-phase modulation voltage command signals is small. A configuration for generating a corrected PWM signal with a reduced PWM frequency is provided. This predetermined period is an angle range from 60 ° to 180 ° if the non-zero period of the voltage command signal is 0 ° to 240 ° in the case of two-phase modulation. Is preferably an angle range of 30 ° before and after the maximum value of the sinusoidal voltage command signal and an angle range of 30 ° before and after the minimum value. Thus, a three-phase PWM inverter device with small waveform distortion and low loss can be obtained.
[0009]
According to the inverter device of the fifth aspect, the period in which the number of PWM cycles corresponding to the rate of change of the voltage command signal is combined is the corrected PWM cycle. Frequency drops. When the PWM frequency is variably controlled stepwise, the suppression of the waveform distortion and the reduction of the switching loss can be more finely controlled.
[0010]
According to the inverter device described in claim 6, in the first time zone of one cycle of the AC voltage, the PWM signal having the basic PWM frequency is output from the output terminal of the first phase of the processor, and the second signal is output. A PWM signal having a frequency that is 1 / K (K = 2, 3, 4,...) Of an integral number of the basic PWM frequency is output from the output terminal of the phase. Further, in the second time zone, a PWM signal having a frequency that is an integer fraction of the basic PWM frequency is output from the output terminal of the first phase, and a PWM signal having the basic PWM frequency is output from the output terminal of the second phase. A signal is output. As a result, control is performed such that a period in which the rate of change of the first phase voltage is small corresponds to the second time zone, and a period in which the rate of change of the second phase voltage is small corresponds to the first time zone. For example, it is possible to suppress the waveform distortion and reduce the switching loss as described above.
[0011]
According to the inverter device according to the seventh aspect, the output terminal of the processor in the first time zone (for example, the period in which the voltage change rate is relatively small) in one cycle of the phase voltage output from the inverter circuit. A PWM signal having a frequency that is a fraction of the basic PWM frequency (= 1 / K (K = 2, 3, 4,...)) Is output, and the second time period (for example, the voltage change rate is relatively large) During this period, a PWM signal having a basic PWM frequency is output from the output terminal of the processor. As a result, it is possible to suppress waveform distortion and reduce switching loss.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 shows an electrical configuration of the inverter device. The inverter device 1 drives a brushless motor 2 connected as a load, and includes a DC power supply circuit 3, an inverter circuit 4, a control unit 5, a gate drive circuit 6, and a current detection unit 7.
[0013]
The DC power supply circuit 3 is a voltage doubler rectifier circuit composed of a diode bridge 9 and capacitors 10 and 11, and a single-phase AC power supply 13 is connected to an input terminal of the DC power supply circuit 3 via a reactor 12. ing. The DC power supply circuit 3 outputs a DC voltage to power supply lines 14 and 15, and an inverter circuit 4 is connected between the power supply lines 14 and 15.
[0014]
The inverter circuit 4 is configured by connecting IGBTs Q1 to Q6 in a three-phase bridge between the power supply lines 14 and 15, and is capable of outputting a three-phase AC voltage. IGBTs Q1-Q3 correspond to upper-arm switching elements, and IGBTs Q4-Q6 correspond to lower-arm switching elements. The IGBTs Q1 to Q6 are connected (or integrally formed as elements) to reflux diodes D1 to D6 having the illustrated polarities, respectively. The windings 2u, 2v, 2w of the brushless motor 2 are connected to the U-phase, V-phase, and W-phase output terminals 4u, 4v, 4w of the inverter circuit 4, respectively.
[0015]
The current detection unit 7 includes current sensors 16u and 16v such as a Hall IC and a Hall sensor. These current sensors 16u and 16v output voltages corresponding to the currents flowing from the inverter circuit 4 to the windings 2u and 2v, respectively.
[0016]
The control unit 5 includes a processor 17 such as a DSP (Digital Signal Processor) that can perform high-speed operations. The processor 17 includes an A / D converter 18, a CPU 19, a rewritable nonvolatile memory 20 storing an execution program for controlling the brushless motor 2, a volatile memory 21 storing temporary data, and the like. I have. The processor 17 has six output terminals for outputting corrected PWM signals Cup, Cun, Cvp, Cvn, Cwp, and Cwn, which will be described later.
[0017]
FIG. 2 is a block diagram illustrating functions of the processor 17. That is, the processor 17 uses the hardware circuit and the programs and data stored in the non-volatile memory 20 to execute the detection current calculation unit 22, the command current calculation unit 23, the voltage command signal generation unit 24, and the PWM signal generation unit 25. And a function as the PWM correction unit 26 is realized.
[0018]
The detection current calculation unit 22 converts the output voltages of the current sensors 16u and 16v into digital data by the A / D converter 18 (including a preamplifier circuit), and outputs the currents Iu and Iv flowing through the winding 2 of the brushless motor 2. , Iw. The command current calculation unit 23 calculates, for example, vector control based on the detected currents Iu, Iv, Iw, and calculates the command currents Iur, Ivr, Iwr. This vector control system includes a speed control loop and a current control loop.
[0019]
The voltage command signal generation unit 24 calculates voltage command signals Vu, Vv, Vw corresponding to the output voltage of each phase using the command currents Iur, Ivr, Iwr. In this embodiment, a two-phase modulation method is adopted, and the waveforms of these voltage command signals Vu, Vv, Vw are as shown in FIG. The PWM signal generation unit 25 (corresponding to PWM signal generation means) performs a PWM signal Dup, Dun, Dvp, Dvn, Dwp, based on a comparison between the voltage command signals Vu, Vv, Vw and the triangular wave signal Sc as a carrier signal. Based on the PWM signals Dup, Dun, Dvp, Dvn, Dwp, Dwn, the PWM correction unit 26 (corresponding to the correction means) generates the corrected PWM signals Cup, Cun, Cvp, Cvn, Cwp, Cwn. To generate.
[0020]
The gate drive circuit 6 receives the corrected PWM signals Cup to Cwn from the processor 17, performs level conversion, and generates drive signals Gup to Gwn to be applied to the gates of the IGBTs Q1 to Q6. The IGBTs Q1 to Q6 are turned on when the corrected PWM signals Cup to Cwn are at H level, and turned off when they are at L level. For each phase, the upper arm-side corrected PWM signal and the lower arm-side corrected PWM signal do not go to the H level at the same time, and the upper-arm-side corrected PWM signal and the lower-arm-side corrected PWM signal except for the dead time period. Is at H level.
[0021]
A position detector 27 composed of a Hall IC or the like is attached near the rotor of the brushless motor 2, and the voltage command signal generation unit 24 generates the voltage based on the position signal from the position detector 27. The phases of the command signals Vu, Vv, Vw are determined.
[0022]
Next, the operation of the present embodiment will be described with reference to FIGS.
The voltage command signals Vu, Vv, Vw shown in FIG. 3 generated by the PWM signal generation unit 25 are signals for commanding the phase voltage output from the inverter circuit 4, respectively. When the phase voltage is controlled to have such a waveform, the line voltage output from the inverter circuit 4 can have a sine waveform. In this case, the frequency (carrier frequency fc) of the triangular wave signal Sc used by the PWM signal generation unit 25 is set high in order to accurately match the phase voltage output from the inverter circuit 4 with the voltage command signals Vu, Vv, Vw. Is preferred. However, when the carrier frequency fc is increased, switching loss increases. Therefore, the PWM correction unit 26 generates corrected PWM signals Cup to Cwn based on the PWM signals Dup to Dwn by the following means.
[0023]
The on / off states of the IGBTs Q1 to Q6 are controlled in units of the PWM cycle. However, in a period in which the phase voltage change is relatively gradual, even if the PWM cycle is lengthened, the deviation between the phase voltage and the voltage command signals Vu, Vv, Vw may vary. It is unlikely to occur. Focusing on this point, the PWM correction unit 26 sets the PWM cycle to a predetermined period as an angle range in which the change rate of the phase voltage, that is, the voltage command signals Vu, Vv, Vw is relatively small for each phase. Correct to be longer.
[0024]
This predetermined period is an angle range from 60 ° to 180 °, provided that the non-zero period of the voltage command signals Vu, Vv, Vw is from 0 ° to 240 °. Under the phase angles (electrical angles) shown in FIG. 3, the U phase, the V phase, and the W phase each have an angle range from 60 ° to 180 °, an angle range from 180 ° to 300 °, and 300 ° to 420 ° ( That is, the angle range is 60 °).
[0025]
FIG. 4 shows (a) the PWM signals Du, Dv, Dw and (b) the corrected PWM signals Cu, Cv, Cw at the phase angle A shown in FIG. Here, the PWM signals Du, Dv, Dw and the corrected PWM signals Cu, Cv, Cw indicate that the upper arm IGBTs Q1, Q2, Q3 are turned on by 1, and the lower arm IGBTs Q4, Q5, Q6 are turned on. This is a signal equivalent to the PWM signals Dup to Dwn and the corrected PWM signals Cup to Cwn, respectively.
[0026]
At the time of the phase angle A, since the V-phase voltage command signal Vv is 0, the PWM signal Dv and the corrected PWM signal Cv during the period of the PWM cycle Tc (= 1 / fc) remain 0, and the V-phase lower arm side IGBT Q5 keeps on. On the other hand, the W-phase PWM signal Dw becomes 1 during the period Tw1 (corresponding to the first period) of the PWM cycle Tc, and becomes 0 during the remaining (Tc−Tw1) period (corresponding to the second period). It becomes. However, since the change rate of the W-phase voltage, that is, the voltage command signal Vw, is relatively large, the PWM correction unit 26 outputs the PWM signal Dw as it is as the corrected PWM signal Cw.
[0027]
The U-phase PWM signal Du becomes 1 during the period of Tu1 (corresponding to the first period) in the PWM cycle Tc, and becomes 0 during the remaining (Tc−Tu1) period (corresponding to the second period). The period of Tu1 corresponds to a first on / off state in which the upper arm IGBT Q1 is turned on and the lower arm IGBT Q4 is turned off. During the period (Tc-Tu1), the upper arm IGBT Q1 is turned off and the lower arm is turned off. This corresponds to a second on / off state in which the IGBT Q4 on the side is turned on. Similarly, in the next PWM cycle, the PWM signal Du becomes 1 during the period of Tu2 in the PWM cycle Tc, and becomes 0 during the remaining (Tc−Tu2).
[0028]
The time point of the phase angle A is included in the angle range in which the change rate of the U-phase voltage, that is, the voltage command signal Vu is relatively small, as described above. For this reason, the PWM correction unit 26 sets the period of 2 · Tc, which is the sum of the two PWM periods Tc for the U phase, as the corrected PWM period, and sets the period of the Tu, which is the sum of the times Tu1 and Tu2 (the first corrected period). A corrected PWM signal Cu is generated which becomes 1 during the period (corresponding to the period) and becomes 0 during the remaining (2 · Tc−Tu) period (corresponding to the corrected second period). Such correction of the U-phase is performed in a phase angle of 60 ° to 180 ° shown in FIG. As a result, the U-phase PWM frequency during this period is １ ／ of the basic PWM frequency fc, and the V-phase and W-phase PWM frequencies remain at the basic PWM frequency fc.
[0029]
Similarly, in the period from the phase angle of 180 ° to 300 ° shown in FIG. 3, the PWM cycle of the V phase is corrected, the PWM frequency of the V phase becomes fc / 2, and the phase angle of 300 ° to 420 ° (that is, 60 °). In the period, the PWM cycle of the W phase is corrected, and the PWM frequency of the W phase becomes fc / 2. The ratio of the time during which the upper arm IGBT of each phase is on in the corrected PWM cycle to the time during which the lower arm IGBT is on is determined by the upper arm IGBT of each phase in the pre-correction PWM cycle. Since the ratio is equal to the ratio of the on-time to the on-time of the lower arm IGBT, the effective voltage output from the inverter circuit 4 does not change.
[0030]
After all, when such a correction is performed, in one period of the AC voltage output from the inverter circuit 4, in a period (corresponding to a first time zone) of a phase angle of 60 ° to 180 ° shown in FIG. Corrected PWM signals Cvp, Cvn, Cwp, and Cwn having the basic PWM frequency fc are output from output terminals (corresponding to a first output terminal) related to the V phase and the W phase of the processor 17, and output terminals related to the U phase. (Corresponding to the second output terminal) outputs corrected PWM signals Cup and Cun having a PWM frequency which is の of the basic PWM frequency fc.
[0031]
In the period from the phase angle of 180 ° to 300 ° (corresponding to the second time zone), the output terminals of the processor 17 relating to the U phase and the W phase output the corrected PWM signals Cup, Cun, Cwp and Cwn are output, and corrected PWM signals Cvp and Cvn having a PWM frequency of １ ／ of the basic PWM frequency fc are output from the output terminal related to the V phase. The same applies to the case where the period from the phase angle of 300 ° to 420 (that is, 60 °) is set as the second time zone.
[0032]
As described above, according to the present embodiment, in the angle range where the rate of change of the phase voltage for each phase is relatively small, the period in which two consecutive PWM cycles Tc are combined is set as one correction PWM cycle, and the IGBTs Q1 to Q6 are used. Is switched, so that the PWM frequency is の of the PWM frequency fc before correction in the angle range. Therefore, when viewed as a whole of the three-phase inverter circuit 4, the number of times of switching of the IGBTs Q1 to Q6 is reduced to 3/4 of that of the conventional configuration, and the switching loss can be reduced accordingly.
[0033]
Even if the PWM frequency is reduced in this way, the change rate of the output voltage (phase voltage) is relatively small during the period, so that voltage and current waveform distortions are less likely to occur. On the other hand, during periods other than the predetermined period, the PWM frequency remains at the PWM frequency fc, so that the waveform distortion does not increase. As a result, the waveform distortion of the entire output voltage and output current is reduced.
[0034]
(Second embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. The inverter device according to the present embodiment has the same electrical configuration as the inverter device 1 according to the first embodiment, but generates PWM signals Du, Dv, and Dw by three-phase modulation as a function of a voltage command generation unit. They are different. Also in the case of three-phase modulation, the PWM correction unit sets the PWM cycle to 2 · Tc in a predetermined period that is predetermined as an angle range in which the rate of change of the voltage command signals Vu, Vv, Vw is relatively small for each phase. Correct so that
[0035]
This predetermined period is set to an angle range of 30 ° before and after the maximum value of each of the sinusoidal voltage command signals Vu, Vv, and Vw shown in FIG. 5 and an angle range of 30 ° before and after the minimum value. . That is, under the phase angle (electrical angle) shown in FIG. 5, the angle range from 60 ° to 120 ° and the angle range from 240 ° to 300 ° for the U phase, and the angle range from 0 ° to 60 ° for the V phase. And the angle range from 180 ° to 240 °, and the W phase has an angle range from 120 ° to 180 ° and an angle range from 300 ° to 360 °.
[0036]
FIG. 6 shows (a) the PWM signals Du, Dv, Dw and (b) the corrected PWM signals Cu, Cv, Cw at the phase angle B shown in FIG. The time point of the phase angle B is included in the angle range where the change rate of the U-phase phase voltage, that is, the voltage command signal Vu is relatively small. For this reason, the PWM correction unit sets the period of 2 · Tc, which is the sum of the two PWM periods Tc for the U phase, as the corrected PWM period, and sets 1 (the upper arm side) in the period of Tu, which is the sum of the times Tu1 and Tu2 before correction. IGBT Q1 is turned on), and a corrected PWM signal Cu that is 0 (the lower arm IGBT Q4 is turned on) during the remaining (2 · Tc−Tu) period is generated.
[0037]
On the other hand, since the change rates of the phase voltages of the V phase and the W phase, that is, the voltage command signals Vv and Vw are relatively large, the PWM correction unit outputs the PWM signals Dv and Dw as they are as the corrected PWM signals Cv and Cw. Such correction of the U-phase is performed during the period from 60 ° to 120 ° and the period from 240 ° to 300 ° shown in FIG. 5 as described above. As a result, the U-phase PWM frequency during this period is fc / 2, and the V-phase or W-phase PWM frequency remains at fc. For other angle ranges, the V-phase or W-phase PWM frequency is fc / 2.
[0038]
As described above, according to the present embodiment using three-phase modulation, the switching frequency of the IGBTs Q1 to Q6 is reduced to 5/6 as compared with the conventional configuration when viewed as the whole three-phase inverter circuit. Loss can be reduced. Further, the waveform distortion of the output voltage and the output current can be suppressed small by the same operation as that of the first embodiment.
[0039]
(Other embodiments)
The present invention is not limited to the embodiments described above and shown in the drawings. For example, the present invention can be modified or expanded as follows.
In the angle range where the rate of change of the phase voltage for each phase is relatively small, the period in which two consecutive PWM periods Tc are combined is set as one corrected PWM period, but three or more consecutive PWM periods Tc are combined. The period may be one correction PWM cycle. Further, a period in which the number of consecutive PWM cycles Tc according to the change rates of the voltage command signals Vu, Vv, and Vw may be set as the corrected PWM cycle. When the PWM frequency is stepwise variably controlled in this manner, the smaller the rate of change of the output voltage (phase voltage) is, the lower the PWM frequency in the relevant portion is, so that the suppression of waveform distortion and the reduction of switching loss can be more finely controlled. It becomes.
[0040]
In each embodiment, the angle range in which the rate of change of the voltage command signals Vu, Vv, Vw is relatively small has been described using specific numerical values. However, this angle numerical value is an example, and waveform distortion and The angle range may be set to be narrower or wider than this angle range depending on the switching loss.
[0041]
The invention can be generally applied to not only a three-phase inverter device but also a polyphase inverter device. Further, the configuration of the inverter circuit 4 is not limited to a full-bridge circuit configuration.
The carrier signal used in the PWM signal generator 25 is not limited to the triangular wave signal Sc but may be a sawtooth signal.
The motor is not limited to a brushless motor, but may be an induction motor or a synchronous motor. Further, the load of the inverter device 1 is not limited to a motor.
[0042]
【The invention's effect】
As is apparent from the above description, the inverter device of the present invention generates a corrected PWM signal by using a period obtained by combining a plurality of continuous PWM periods of the PWM signal as the corrected PWM period, and generates the corrected PWM signal and the corrected PWM signal in accordance with the time zone. Since the switching element is driven using any of the PWM signals, the switching loss can be reduced while suppressing the waveform distortion of the output voltage and the output current.
[Brief description of the drawings]
FIG. 1 is an electrical configuration diagram of an inverter device according to a first embodiment of the present invention; FIG. 2 is a block diagram illustrating functions of a processor; FIG. 3 is voltage command signals Vu, Vv, and Vw in the case of two-phase modulation; FIG. 4 is a diagram showing PWM signals before and after correction. FIG. 5 is a diagram showing waveforms of voltage command signals Vu, Vv, Vw in the case of three-phase modulation according to the second embodiment of the present invention. FIG. 6 is a diagram corresponding to FIG.
1 is an inverter device, 4 is an inverter circuit, 17 is a processor, 25 is a PWM signal generation unit (PWM signal generation unit), 26 is a PWM correction unit (correction unit), and Q1 to Q6 are IGBTs (switching elements).

Claims (7)

An inverter circuit that includes a plurality of switching elements and outputs an AC voltage by turning off these switching elements;
A PWM signal that generates a PWM signal in which each PWM cycle includes a first period corresponding to a first on / off state of the switching element and a second period corresponding to a second on / off state based on a voltage command signal. Generating means;
A period obtained by combining a plurality of continuous PWM cycles of the PWM signal is a corrected PWM cycle, and the corrected PWM cycle has a time width corresponding to a first period in each of the plurality of continuous PWM cycles, and A second period corresponding to a first period corresponding to a first on / off state and a second period in each of the plurality of continuous PWM cycles, and having a time width corresponding to a second on / off state of the switching element. Correction means for generating a correction PWM signal comprising:
An inverter device, wherein at least one switching element of the plurality of switching elements is configured to be driven using one of the PWM signal and the corrected PWM signal in accordance with a time zone. An inverter circuit including at least one switching element;
A PWM that generates a PWM signal for driving the switching element, with a total time of a first period in which the switching element is on and a second period in which the switching element is off being taken as one PWM cycle. Signal generation means;
A time obtained by combining a plurality of PWM cycles is set as a corrected PWM cycle, and the switching element is turned on with a time width obtained by adding the first period in each PWM cycle among the plurality of continuous PWM cycles. Correction means for generating a correction PWM signal for turning off the switching element in a time width obtained by combining the second time,
An inverter device configured to drive the switching element using one of the PWM signal and the corrected PWM signal according to a time zone. The inverter circuit is configured to output a three-phase AC voltage, and the PWM signal generating unit is configured to generate the PWM signal based on a voltage command signal of two-phase modulation,
The correcting means is configured to generate the corrected PWM signal in an angle range from 60 ° to 180 ° of the non-zero period of the voltage command signal of each phase from 0 ° to 240 °. The inverter device according to claim 1 or 2, wherein: The inverter circuit is configured to output a three-phase AC voltage, and the PWM signal generation unit is configured to generate the PWM signal based on a sinusoidal voltage command signal for three-phase modulation,
The correction means is configured to generate the corrected PWM signal in an angle range of 30 ° before and after the maximum value of the voltage command signal of each phase and an angle range of 30 ° before and after the minimum value. The inverter device according to claim 1 or 2, wherein: 5. The inverter device according to claim 1, wherein the correction unit sets a period obtained by adding a number of PWM cycles corresponding to a rate of change of the voltage command signal to a corrected PWM cycle. 6. A processor having at least two output terminals for outputting PWM signals of different phases, and an inverter circuit having a switching element driven based on the PWM signal;
The processor outputs a PWM signal having a basic PWM frequency from a first output terminal in a first time zone of one cycle of the AC voltage output from the inverter circuit, and outputs the PWM signal from a second output terminal. A PWM signal having a frequency that is an integer fraction of the PWM frequency is output, and a frequency that is an integer fraction of the basic PWM frequency is output from the first output terminal in a second time zone of one cycle of the AC voltage. An inverter device configured to output a PWM signal having the basic PWM frequency from the second output terminal. A processor having an output terminal for outputting a PWM signal, and an inverter circuit having a switching element driven based on the PWM signal;
The processor outputs, for each phase, a PWM signal having a frequency that is an integer fraction of a basic PWM frequency from the output terminal in a first time zone of one cycle of a phase voltage output from the inverter circuit. An inverter device configured to output a PWM signal having the basic PWM frequency from the output terminal in a second time zone.

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