JP4276097B2 - Inverter driving method and inverter device - Google Patents

Description

  The present invention relates to an inverter driving method and an inverter device, and more particularly to an inverter driving method and an inverter device suitable for operating a synchronous motor.

  Patent Document 1 discloses that, in inverter control of a synchronous machine, a DC drive period for fixing a current flow path to the synchronous machine is provided at the time of startup. When this DC drive period is realized by PWM control, normally, all six semiconductor switches constituting the inverter circuit are controlled to be turned on and off for DC drive.

Japanese Patent No. 2533472 (Overall)

  In the conventional DC drive control, since six semiconductor switches perform switching operation in the PWM cycle, the number of switching of the inverter is large, and the potential fluctuation of the three-phase output neutral point with reference to the potential of the DC input terminal of the inverter There is a problem that the width is large. The switching of the semiconductor switch increases the power loss of the semiconductor switch and the peripheral circuit and decreases the efficiency, and the sharp voltage change of the three-phase output neutral point becomes a source of conduction noise and radiation noise, and the peripheral circuit malfunctions. It may cause communication failure with the host and radio noise.

  An object of the present invention is to provide an inverter driving method and an inverter device capable of reducing power loss of a semiconductor switch and peripheral circuits during a DC driving period.

  Another object of the present invention is to provide an inverter driving method and an inverter device capable of reducing conduction noise and radiation noise.

  In a preferred embodiment of the present invention, the inverter includes a DC drive period for fixing a path of a current flowing through a three-phase load connected to a three-phase AC output terminal of the inverter, and converts a DC input voltage into a three-phase AC voltage. During the DC drive period, the semiconductor switches of the phases other than the one-phase or two-phase are controlled to be turned on / off while the on-off state of the one-phase or two-phase semiconductor switch is fixed.

  In a preferred embodiment of the present invention, in the DC drive period, the negative (or positive) phase of the second or third phase is kept in a state in which the semiconductor switch on the negative (or positive) pole side of the first phase is fixed on. The semiconductor switch is controlled to be turned on and off so as to include a period in which the pole side semiconductor switch is simultaneously turned on.

  In a preferred embodiment of the present invention, the first phase negative (or positive) side semiconductor switch and the second phase negative (or positive) side semiconductor switch are simultaneously turned on during the DC drive period. A combination of a first switch pattern and a second switch pattern that simultaneously turns on a negative (or positive) pole-side semiconductor switch of the first phase and a negative (or positive) pole-side semiconductor switch of the third phase. Switch on and off.

  According to a preferred embodiment of the present invention, the number of switching times of a semiconductor switch can be reduced, and power loss of the semiconductor switch and peripheral circuits can be reduced.

  In addition, according to a preferred embodiment of the present invention, it is possible to reduce the potential fluctuation range of the three-phase output neutral point with reference to the DC input terminal of the inverter, thereby reducing conduction noise and radiation noise.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First embodiment:
FIG. 1 is a block diagram of a circuit configuration of an inverter device according to a first embodiment of the present invention. In FIG. 1, the inverter device includes a DC voltage source 1, a main circuit 2, a synchronous motor 3, a compressor 4, an intermediate power unit 5, and an arithmetic processing unit 6.

  The main circuit 2 makes a voltage supplied from the DC voltage source 1 through the DC reactor 21 and the smoothing capacitor 22, creates a variable voltage and a variable frequency three-phase AC voltage by the inverter circuit 23, and supplies it to the synchronous motor 3. The compressor 4 is driven. The inverter circuit 23 includes U-phase upper and lower arm semiconductor switches 231 and 232, V phase upper and lower arm semiconductor switches 233 and 234, and W phase upper and lower arm semiconductor switches 235 and 236.

  The intermediate power unit 5 includes a drive power source 51, a control power source 52 for an arithmetic processing unit 6 described later, and a drive circuit 53 that drives a semiconductor switch in the inverter circuit 23.

  The arithmetic processing unit 6 includes a current detection process 61, a motor control process 62, a switching frequency reduction process 63, a dead time distortion compensation process 64, a gate pulse setting process 65, and a switching frequency reduction process valid / invalid selection 66. And an on / off stationary phase selection 67.

  The inverter driving method according to the present embodiment is characterized by switching frequency reduction processing 63, gate pulse setting processing 65, switching frequency reduction processing valid / invalid selection 66, and on / off stationary phase selection 67 among the arithmetic processing unit 6. There is.

The current detection processing 61 inputs the output of the current detector 24 that detects the current flowing through the semiconductor switch 232 of the U-phase lower arm and the semiconductor switch 234 of the V-phase lower arm of the inverter circuit 23, and performs analog / digital conversion processing. After that, the detected current value of each phase is output. The motor control process 62 inputs the detected current value obtained in the current detection process 61, calculates the voltage command value of each phase, converts it to time data, and converts it into time data, U-phase voltage command time data Vu ^* 621, V-phase Voltage command time data Vv ^* 622 and W-phase voltage command time data Vw ^* 623 are output.

The switching frequency reduction process 63 receives the instruction signal from the switching frequency reduction process valid / invalid selection 66 and each phase voltage command time data calculated in the motor control process 62. When the valid / invalid selection 66 selects invalid, each phase voltage command time data calculated in the motor control process 62 is output as it is. On the other hand, if the valid / invalid selection 66 is selected as valid, using the phase voltage command time data calculated in the motor control process 62, the calculation according to the process flow of FIG. Each phase voltage command time data Vu ^* '631 to Vw ^* ' 633 is output.

  The dead time distortion compensation processing 64 inputs each phase voltage command time data after the number of times of switching is reduced, adds dead time distortion compensation, and then outputs each phase voltage command time data after dead time distortion compensation. The gate pulse setting process 65 includes an instruction signal from the valid / invalid selection 66 of the switching frequency reduction process, an instruction signal from the on / off stationary phase selection 67, and dead time distortion compensation that is an output of the dead time distortion compensation process 64. The subsequent phase voltage command time data is input. When the valid / invalid selection 66 selects invalid, time data obtained by adding carrier amplitude to each phase voltage command time data after dead time distortion compensation is set in each phase gate pulse. On the other hand, when the valid / invalid selection 66 selects valid, and the on / off stationary phase selection 67 instructs the U-phase lower arm semiconductor switch 232 and the V-phase lower arm semiconductor switch 234 to be fixed on. If so, do different settings as follows: That is, the U-phase and V-phase gate pulse setting values are set to 0 in the time data obtained by adding the carrier amplitude to each phase voltage command time data after dead time distortion compensation. Thus, in addition to the semiconductor switch 232 of the U-phase lower arm, the semiconductor switch 234 of the upper and lower arms of the W-phase is switched while the semiconductor switch 234 of the V-phase lower arm remains on. Further, when the valid / invalid selection 66 instructs valid, and the on / off fixed phase selection 67 instructs the U-phase lower arm semiconductor switch 232 and the W-phase lower arm semiconductor switch 236 to be fixed on, Set as follows. That is, the U-phase and W-phase gate pulse setting values are set to 0 in the time data obtained by adding the carrier amplitude to each phase voltage command time data after compensation for dead time distortion. Thereby, in addition to the semiconductor switch 232 of the U-phase lower arm, the semiconductor switch 236 of the W-phase lower arm remains on, and only the semiconductor switches 233 and 234 of the V-phase upper and lower arms are switched.

  The switching number reduction process valid / invalid selection 66 selects valid during the DC drive period, instructs the switching number reduction process 63 and the gate pulse setting process 65 to operate, and the current flowing through the synchronous motor connected to the three-phase output terminal The current path is fixed and current is passed. Invalid is selected during a period other than the DC drive period.

  The on / off fixed phase selection 67 instructs the gate pulse setting processing 65 to select a phase to be fixed on or off at an arbitrary cycle. In the present embodiment, the on / off stationary phase is switched in the PWM carrier valley period.

  Next, the inverter driving method according to the first embodiment will be described in detail with reference to FIGS.

  FIG. 2 shows a U-phase current waveform of the synchronous motor 3. In FIG. 2, after the motor stop period Ps in which the three-phase voltage is not output from the inverter 23 to the motor 3, there is an AC drive period Pa through the DC drive period Pd. As described above, the period during which the switching frequency reduction process is effective is the DC drive period Pd, and the present invention is effective during this period.

  In the conventional inverter driving method, the PWM pulse waveform in the DC driving period Pd and the neutral point potential waveform of the three-phase load with reference to the negative terminal Tn of the DC input terminal are the waveforms shown in FIG. As a result, all of the six semiconductor switches constituting the inverter perform switching operation as shown in FIG. The neutral point potential waveform shown in FIG. 3 represents the potential waveform of the neutral point Np of the three-phase load with reference to the DC input terminal Tn on the negative electrode side shown in FIG.

  Here, since the neutral point Np of the DC input terminals Tp and Tn and the three-phase load are connected to the ground by a stray capacitance, the potential of the neutral point Np of the three-phase load 3 varies. Becomes a source of radiation noise and conduction noise. In order to suppress this radiation noise and conduction noise, the potential fluctuation width of the neutral point Np of the three-phase load 3 with reference to both DC input terminals Tp and Tn may be suppressed.

  In the inverter driving method of the present embodiment, the switching frequency reduction process 63 shown in FIG. 6 and the gate pulse setting process 65 shown in FIG. As a result, the PWM pulse waveform and the neutral point potential Np waveform of the three-phase load shown in FIG. 8 are obtained, and the semiconductor switch state at that time is the state shown in FIG.

  In this case, the U-phase motor current waveform is not different between the conventional and the present embodiment, and the PWM pulse waveform, the switching state, and the potential waveform at the neutral point Np of the three-phase load 3 are different.

  For comparison, the prior art will describe the PWM pulse waveform during the DC driving period and the neutral point potential waveform of the three-phase load in the conventional inverter driving method shown in FIG. . The value taking into account the sign of 1/4 the carrier frequency is [-(A)], and the U-phase, V-phase, and W-phase voltage command time data are (B), (C), and (D), respectively. . Next, let (E) be the difference between the value that takes into account the sign of the size of 1/4 of the carrier frequency and the U-phase voltage command time data. Furthermore, the sum of the magnitude of the U-phase voltage command time data and the magnitude of the V-phase voltage command time data is (F), and the sum of the magnitude of the U-phase voltage command time data and the magnitude of the W-phase voltage command time data is (G ).

  What should be noted here is that all the semiconductor switches are controlled to be turned on and off along the period of the PWM carrier, and the neutral point of the synchronous motor 3 based on the positive and negative DC input terminals Tp and Tn. The potential fluctuation width of Np is equal to the DC voltage source voltage Ed. As apparent from the switching waveform, there is a period in which the positive and negative semiconductor switches of all three phases are turned on or off simultaneously. Therefore, although only the potential at the neutral point Np with respect to the negative terminal Tn is illustrated, the potential at the neutral point Np of the synchronous motor 3 with respect to the positive terminal Tp also varies from zero to Ed. Again, the fluctuation range is equal to the DC voltage source voltage Ed. For this reason, not only does the power loss of the semiconductor switch and the peripheral circuit increase and the efficiency decreases, but also a sudden potential change at the three-phase output neutral point Np causes a source of conduction noise and radiation noise, resulting in malfunction of the peripheral circuit. This causes the occurrence of communication interruption with the host and radio noise.

  FIG. 6 is a process flow diagram of the switching number reduction process 63 according to the first embodiment of the present invention. In FIG. 6, during the DC drive period, the instruction signal from the valid / invalid selection 66 indicates that the switching frequency reduction process is valid. During the DC drive period, first, the above-mentioned ¼ value of the carrier frequency [− (A)] and each phase voltage command time data (B), (C), (D) are called to the register, and the next calculation is performed. I do. The difference in time data for fixing the switch 232 of the U-phase lower arm on (E), the sum of the magnitude of the U-phase voltage command time data and the magnitude of the V-phase voltage command time data (F), The sum (G) of the magnitudes of the phase voltage command time data and the W phase voltage command time data is obtained. Using the (E), (F), and (G), each phase voltage command time data after the switching number reduction processing is obtained.

  The U-phase voltage command time data 631 after the number of times of switching is reduced by adding (E) to the U-phase voltage command time data 621 so as not to perform the switching operation. The V-phase voltage command time data 632 after the switching frequency is reduced is obtained by adding the (E) and (G) to the V-phase voltage command time data 622 to obtain V-phase voltage command time data. The W-phase voltage command time data 633 after the number of times of switching is obtained by adding the (E) and (F) to the W-phase voltage command time data 623 to obtain W-phase voltage command time data.

  Here, (E) is a time difference for fixing the U-phase lower arm semiconductor switch 232 to ON, and in order to make the three-phase voltage applied to the synchronous motor equivalent to the conventional one, the same value is added to all three phases. ing. Further, (F) and (G) are fixed on in order to fix the lower arm semiconductor switch of either one of the V phase and the W phase in the PWM valley cycle in the process of FIG. 7 described later. The phase undervoltage is added to compensate for the switching frequency reduction process.

  FIG. 7 is a process flow diagram of the gate pulse setting process 65 according to the first embodiment of the present invention. In FIG. 7, during the DC drive period, the instruction signal from the valid / invalid selection 66 is valid for the switching frequency reduction process. During the DC drive period, any one of the combinations of the U phase and the V phase or the U phase and the W phase according to the instruction from the on / off fixed phase selection 67 with respect to the gate pulse set value after the carrier amplitude addition. Set the gate pulse setting value to 0. By setting the gate pulse set value to 0, the designated semiconductor switch is fixed to ON and no switching operation is performed. Here, the semiconductor switch of any combination of the semiconductor switch 232 of the U-phase lower arm and the semiconductor switch 234 of the V-phase lower arm, or the semiconductor switch 232 of the U-phase lower arm and the semiconductor switch 236 of the W-phase lower arm is turned on. Fixed and does not switch.

  FIG. 8 is a PWM pulse waveform and a neutral point potential waveform diagram of a three-phase load when the processes shown in FIGS. 6 and 7 are performed according to the first embodiment of the present invention. In FIG. 8, the semiconductor switch patterns (1) and (2) are alternately repeated in the PWM valley period, and the number of switching operations is reduced by the pattern. Here, in addition to the switching of the U-phase semiconductor switch becoming zero, the switching frequency of the V-phase and W-phase semiconductor switches is also halved. The potential fluctuation width with respect to the DC negative electrode side terminal Tn of the neutral point Np of the three-phase load 3 is 1/3 of the DC voltage source voltage Ed, and the potential fluctuation width with reference to the positive electrode side terminal Tp (not shown). This is also the same, and it can be seen that it is greatly reduced to 1/3 compared with the conventional case.

  FIG. 9 is a circuit explanatory diagram showing a semiconductor switch pattern when the processing shown in FIGS. 6 and 7 is performed according to the first embodiment of the present invention. In FIG. 9, there are a pattern (1) in which the lower arm semiconductor switches of the U phase and the W phase are fixed on, and a pattern (2) in which the lower arm semiconductor switches of the U phase and the V phase are fixed on. ) And (2) are switched at the PWM valley cycle.

  In this embodiment, the other two-phase semiconductor switches are controlled to be turned on / off while the on / off state of the one-phase semiconductor switch is fixed. It is also possible to fix and control the other one-phase semiconductor switch on and off.

  In the first embodiment of the present invention described above, the on / off states of the one-phase (or two-phase) semiconductor switches 231 and 232 are fixed in the DC drive period Pd of the inverter 23, and the one-phase (or two-phase) The semiconductor switches 233 to 236 of other phases are controlled to be turned on / off.

  In other words, the semiconductor switch 234 or 236 on the negative (or positive) pole side of the second or third phase is simultaneously turned on while the semiconductor switch 232 on the negative (or positive) pole side of the first phase is fixed on. The semiconductor switch is ON / OFF controlled so as to include a fixed period.

  In other words, first, a first switch pattern is provided, in which the semiconductor switch 232 on the negative (or positive) pole side of the first phase and the semiconductor switch 234 on the negative (or positive) pole side of the second phase are simultaneously fixed on. ing. In addition, a second switch pattern is provided in which the semiconductor switch 232 on the negative (or positive) pole side of the first phase and the semiconductor switch 236 on the negative (or positive) pole side of the third phase are simultaneously fixed on. The first and second switch patterns are combined to control the semiconductor switches on and off.

  Thereby, the frequency | count of switching of an inverter and the neutral point electric potential fluctuation range of a three-phase load can be reduced significantly to 1/3 of the past. As a result, power loss, radiation noise, and conduction noise of the semiconductor switch and peripheral circuits can be greatly reduced. Further, by switching between two different switch patterns, the burden on a specific semiconductor switch can be reduced, the temperature rise of the semiconductor switch can be suppressed, and the life and reliability of the semiconductor switch can be improved.

Second embodiment:
FIG. 10 is a block diagram showing a circuit configuration of the inverter device according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in that the on-fixed switch is fixed to one and the arithmetic processing unit 6 has no on / off fixed phase selection. Accordingly, components having the same functions and configurations as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  When the valid / invalid selection 66 is selected as valid, each phase voltage command time data after the number of times of switching is reduced according to the processing flow of FIG. 11 using each phase voltage command time data calculated in the motor control process 62. Is output. The gate pulse setting process 69 sets only the U-phase gate pulse setting value to 0 among the time data obtained by adding the carrier amplitude to each phase voltage command time data after compensation for dead time distortion. As a result, the semiconductor switch 232 of the U-phase lower arm is fixed on and does not perform a switching operation, and drives the motor by switching between the V-phase and W-phase semiconductor switches. Specifically, during the DC drive period, the switching frequency reduction process 68 of FIG. 11 and the gate pulse setting process 69 of FIG. 12 are performed to obtain the PWM pulse waveform and the neutral point potential waveform of the three-phase load of FIG. Each semiconductor switch operates as shown in FIG.

  FIG. 11 is a process flow diagram of the switching number reduction process 68 according to the second embodiment of the present invention. In FIG. 11, during the DC drive period, the instruction signal from the valid / invalid selection 66 indicates that the switching frequency reduction process is valid. During the DC drive period, first, the above-mentioned ¼ value of the carrier frequency [− (A)] and each phase voltage command time data (B), (C), (D) are called to the register. Using the called value, (E) which is a time data difference for fixing the semiconductor switch 232 of the U-phase lower arm on is obtained. Using the obtained (E), each phase voltage command time data after the switching number reduction process is obtained. The U-phase voltage command time data 681 after the number of times of switching is reduced by adding (E) to the U-phase voltage command time data 621 so that the switching operation is not performed. The V-phase voltage command time data 682 after the number of times of switching is obtained by adding (E) to the V-phase voltage command time data 622 to obtain V-phase voltage command time data. The W-phase voltage command time data 683 after the number of times of switching is obtained by adding (E) to the W-phase voltage command time data 623 to obtain W-phase voltage command time data.

  Here, (E) is a time difference for fixing the semiconductor switch 232 of the U-phase lower arm on, and the same value is added to the three phases in order to make the voltage applied to the synchronous motor equivalent to the conventional voltage. .

  FIG. 12 is a process flowchart of the gate pulse setting process 69 according to the second embodiment of the present invention. In FIG. 12, during the DC drive period, the instruction signal from the valid / invalid selection 66 is valid for the switching frequency reduction process. During the DC drive period, the U-phase gate pulse setting value is set to 0 with respect to the gate pulse setting value after the carrier amplitude addition. By setting the gate pulse set value to 0, the U-phase lower arm semiconductor switch 232 is fixed on and does not perform the switching operation, and drives the motor by switching between the V phase and the W phase.

  FIG. 13 is a PWM pulse waveform and a neutral point potential waveform diagram of a three-phase load when the processing shown in FIGS. 11 and 12 is performed according to the second embodiment of the present invention.

  FIG. 14 is a circuit explanatory diagram showing the state of the semiconductor switch when the processes shown in FIGS. 11 and 12 are performed according to the second embodiment of the present invention.

  13 and 14, the semiconductor switch 232 of the U-phase lower arm is fixed on, the number of times of switching is reduced, and the potential fluctuation range of the neutral point Np of the three-phase load 3 is reduced to 2/3 compared to the conventional case. It is clear to do.

  As described above, in the inverter driving method according to the second embodiment of the present invention, the on / off states of the one-phase semiconductor switches 231 and 232 are fixed during the DC driving period, and the other two-phase semiconductor switches 233 to 236 are fixed. Are controlled on and off, respectively. In particular, the other two-phase two positive-side semiconductor switches 233 and 235 and the two negative-side semiconductor switches 234 and 236 are simultaneously turned on and off as a pair.

  As a result, the switching frequency of the inverter and the neutral point potential fluctuation range of the three-phase load can be reduced to 2/3 of the conventional one. As a result, power loss, radiation noise, and conduction noise of the semiconductor switch and peripheral circuits can be reduced.

Third embodiment:
FIG. 15 is a block diagram showing a circuit configuration of an inverter device according to the third embodiment of the present invention. The third embodiment differs from the first embodiment only in the configuration of the AC voltage source 7 and the main circuit 8. Accordingly, components having the same functions and configurations as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  The main circuit 8 includes the AC voltage source 7, the rectifier circuit 25, the DC reactor 21, and the smoothing capacitor 22 to configure the DC voltage source 1 in the previous embodiment. The voltage Ed between both ends of the smoothing capacitor 22 is converted into a three-phase AC voltage having a variable voltage and a variable frequency by the inverter circuit 23, supplied to the synchronous motor 3, and the compressor 4 is driven.

  The configuration after the DC voltage source that outputs the DC voltage Ed is the same as that of the first embodiment. Therefore, also in the third embodiment, as in the first embodiment, the semiconductor switch between the two-phase output terminal and the negative terminal Tn among the three-phase output terminals is fixed on and fixed on during the DC drive period. It is possible to switch the combination of the two phases in the PWM valley cycle.

  From the above, it is apparent that the third embodiment also exhibits the same effect as that of the first embodiment.

The circuit block diagram of the inverter apparatus by the 1st Embodiment of this invention. The U-phase current waveform diagram of a synchronous motor. The PWM pulse waveform in the DC drive period by the conventional inverter drive method, and the neutral point potential waveform figure of the three-phase load on the basis of the negative electrode side terminal of the DC voltage source. The semiconductor switch state figure in the DC drive period by the conventional inverter drive method. The neutral point supplementary figure of the negative electrode side terminal of the DC input terminal shown in FIG. 3, and a three-phase load. The processing flowchart of the switching frequency reduction process 63 of the inverter drive method by the 1st Embodiment of this invention. The processing flowchart of the gate pulse setting process 65 of the inverter drive method by the 1st Embodiment of this invention. FIG. 4 is a neutral point potential waveform diagram of a three-phase load based on a PWM pulse waveform and a negative terminal of a DC voltage source when the inverter driving method according to the first embodiment of the present invention is implemented. The semiconductor switch state figure when the inverter drive method by the 1st Embodiment of this invention is implemented. The circuit block diagram of the inverter apparatus by the 2nd Embodiment of this invention. The processing flowchart of the switching frequency reduction process 68 of the inverter drive method by the 2nd Embodiment of this invention. The processing flowchart of the gate pulse setting process 69 of the inverter drive method by the 2nd Embodiment of this invention. FIG. 6 is a neutral point potential waveform diagram of a three-phase load based on a PWM pulse waveform and a negative terminal of a DC voltage source when an inverter driving method according to a second embodiment of the present invention is implemented. The semiconductor switch state figure when the inverter drive method by the 2nd Embodiment of this invention is implemented. The circuit block diagram of the inverter apparatus by the 3rd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... DC voltage source, 2 ... Main circuit, 3 ... Synchronous motor, 4 ... Compressor, 5 ... Intermediate power part, 6 ... Arithmetic processing part, 7 ... AC voltage source, 8 ... Main circuit, 9 ... Arithmetic processing part, 21 DESCRIPTION OF SYMBOLS ... DC reactor, 22 ... Smoothing capacitor, 23 ... Inverter circuit, 25 ... Rectifier circuit, 51 ... Drive voltage source, 52 ... Control voltage source, 53 ... Drive circuit, 61 ... Current detection process, 62 ... Motor control process, 63 ... Switching frequency reduction processing, 64 ... Dead time distortion compensation processing, 65 ... Gate pulse setting processing, 66 ... Valid / invalid selection of switching frequency reduction processing, 67 ... On / off stationary phase selection, 68 ... Switching frequency reduction processing, 69 ... Gate pulse setting processing, 231 to 236... Semiconductor switch in the inverter.

Claims (10)

Two semiconductor switches for each phase are connected in series between the positive and negative DC input terminals, and the series connection point of these semiconductor switches for each phase is a three-phase AC output terminal, and the six semiconductors in this inverter A control device for controlling on / off of the switch, including a DC drive period that is set at the time of starting the three-phase synchronous motor connected to the three-phase AC output terminal and fixes a current path flowing through the three-phase synchronous motor ; In the inverter driving method for converting a DC input voltage into a three-phase AC voltage, the on / off state of the one-phase or two-phase semiconductor switch is fixed to the same state over the entire period of the DC driving period. Alternatively, an inverter driving method characterized in that on / off control of the semiconductor switch of a phase other than two phases is performed. Two semiconductor switches for each phase are connected in series between the positive and negative DC input terminals, and the series connection point of these semiconductor switches for each phase is a three-phase AC output terminal, and the six semiconductors in this inverter A control device for controlling on / off of the switch, including a DC drive period that is set at the time of starting the three-phase synchronous motor connected to the three-phase AC output terminal and fixes a current path flowing through the three-phase synchronous motor ; In the inverter driving method for converting a DC input voltage into a three-phase AC voltage, the first phase negative (or positive) side semiconductor switch is fixed on over the entire DC driving period. A method for driving an inverter, wherein the semiconductor switch is controlled to be turned on and off so as to include a period in which the semiconductor switch on the negative (or positive) pole side of the second or third phase is simultaneously turned on. Two semiconductor switches for each phase are connected in series between the positive and negative DC input terminals, and the series connection point of these semiconductor switches for each phase is a three-phase AC output terminal, and the six semiconductors in this inverter A control device for controlling on / off of the switch, including a DC drive period that is set at the time of starting the three-phase synchronous motor connected to the three-phase AC output terminal and fixes a current path flowing through the three-phase synchronous motor ; In the inverter driving method for converting a DC input voltage into a three-phase AC voltage, the semiconductor switches on the negative (or positive) pole side of the first phase and the second phase are fixed on throughout the DC driving period. A combination of the first switch pattern and the second switch pattern in which the semiconductor switch on the negative (or positive) pole side of the first phase and the third phase is fixed on, the semiconductor switch is turned on and off. The driving method of an inverter and controlling.   4. The method for driving an inverter according to claim 3, wherein the first and second switch patterns are switched at an arbitrary cycle. Two semiconductor switches for each phase are connected in series between the positive and negative DC input terminals, and a series connection point of the semiconductor switches for each phase is used as a three-phase AC output terminal. And a control device that controls on / off of the semiconductor switches in opposite phases with each other, and the current path that flows through the three-phase synchronous motor that is set when the three-phase synchronous motor connected to the three-phase AC output terminal is started is fixed. In the method of driving an inverter including a DC drive period for converting a DC input voltage into a three-phase AC voltage, the on / off state of the one-phase semiconductor switch is fixed to the same state over the entire period of the DC drive period. And driving the other two-phase semiconductor switches in an on-off state.   6. The method of driving an inverter according to claim 5, wherein the two other two-phase positive-side semiconductor switches and the two other two-phase negative-side semiconductor switches are simultaneously turned on and off as a pair. . Two semiconductor switches for each phase are connected in series between the positive and negative DC input terminals, and the series connection point of these semiconductor switches for each phase is connected to the three-phase AC output terminal and to the three-phase AC output terminal The six semiconductors in the inverter include a DC drive period that is set when the three-phase synchronous motor is started and fixes the path of the current flowing through the three-phase synchronous motor , and converts the DC input voltage into a three-phase AC voltage. In an inverter device comprising a control device for controlling on / off of the switch, the control device makes the on / off state of the one-phase or two-phase semiconductor switch the same over the entire DC drive period. An inverter device comprising: a DC drive control unit that fixes and controls on / off of the semiconductor switch of a phase other than the one-phase or two-phase. Two semiconductor switches for each phase are connected in series between the positive and negative DC input terminals, and the series connection point of these semiconductor switches for each phase is connected to the three-phase AC output terminal and to the three-phase AC output terminal The six semiconductors in the inverter include a DC drive period that is set when the three-phase synchronous motor is started and fixes the path of the current flowing through the three-phase synchronous motor , and converts the DC input voltage into a three-phase AC voltage. In an inverter device including a control device that controls on / off of the switch, the control device fixes the negative (or positive) pole-side semiconductor switch of the first phase on during the entire DC drive period. In this state, the semiconductor switch is provided with means for controlling on / off of the semiconductor switch so as to include a period in which the semiconductor switch on the negative (or positive) side of the second or third phase is simultaneously turned on. That the inverter device. Two semiconductor switches for each phase are connected in series between the positive and negative DC input terminals, and the series connection point of these semiconductor switches for each phase is connected to the three-phase AC output terminal and to the three-phase AC output terminal The six semiconductors in the inverter include a DC drive period that is set when the three-phase synchronous motor is started and fixes the path of the current flowing through the three-phase synchronous motor , and converts the DC input voltage into a three-phase AC voltage. An inverter device comprising a control device for controlling on / off of the switch, wherein the control device is a semiconductor switch on the negative (or positive) pole side of the first phase and the second phase over the entire period of the DC drive period. The semiconductor switch is a combination of a first switch pattern in which the semiconductor switch on the negative (or positive) pole side of the first phase and the third phase is fixed on. On the pitch, the inverter apparatus comprising the direct-current drive means for turning off control. A DC voltage source, an inverter for converting the voltage of the DC voltage source into a three-phase AC voltage, a three-phase synchronous motor supplied with the output three-phase AC of the inverter, a compressor driven by the three-phase synchronous motor, A control device for controlling the inverter including a DC drive period which is set at the time of starting the three-phase synchronous motor connected to the three-phase output terminal of the inverter and fixes a current path flowing through the three-phase synchronous motor ; An inverter device for driving an electric compressor, comprising the inverter device according to any one of claims 7 to 9 as the inverter and the control device.

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