CN105391328A - Hysteresis loop control method for three-level inverter - Google Patents
Hysteresis loop control method for three-level inverter Download PDFInfo
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- CN105391328A CN105391328A CN201510727169.1A CN201510727169A CN105391328A CN 105391328 A CN105391328 A CN 105391328A CN 201510727169 A CN201510727169 A CN 201510727169A CN 105391328 A CN105391328 A CN 105391328A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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Abstract
The invention discloses a hysteresis loop control method for a three-level inverter. Through calculating the actual output current change rate, the instruction current change rate, and the limited minimum switching frequency of an inverter bridge and through comparative judgment, the level state which needs to be outputted by the three-level inverter bridge is directly calculated. Reliable current hysteresis loop tracking control on the three-level inverter is realized, the minimum switching frequency for three-level inverter hysteresis loop control is limited, the current tracking effects of the three-level inverter are ensured, the inverter performance is improved, and the problem of output current distortion caused as the switching frequency, near an output voltage zero crossing point, of the traditional hysteresis loop control three-level inverter is solved.
Description
Technical field
The present invention relates to three-level inverter control technology field, particularly relate to a kind of hysteresis control method thereof of three-level inverter.
Background technology
Hysteresis control is a kind of control method based on current temporary state, and its dynamic response is fast, robustness good, hardware circuit is simple, real-time is good, control precision is higher, has a wide range of applications in field of inserter control.The operation principle of Hysteresis control as shown in Figure 1, by the current i of actual for inverter bridge output
lwith instruction current i
refdifference input hysteresis comparator, produce through hysteresis comparator the break-make that pwm pulse drive singal controls main circuit breaker in middle device, thus realize the object of inverter bridge output current follow current command signal change.
Three-level inverter has that efficiency is high, output ripple is little, switching frequency high, and three-level inverter structural representation is as Fig. 2.When hysteretic loop current control is applied to three-level inverter control, the common tracking and controlling method of tradition is the output level by the polarity of outlet side voltage to be determined three-level inverters as additional conditions, when output voltage is positive polarity, inverter bridge is selected to export positive level and zero level, when outlet side voltage is negative polarity, inverter bridge is selected to export negative level and zero level.When Hysteresis control selects fixing ring width to control, the switching frequency of converter bridge switching parts device can in very large range change, and this will have influence on the filter effect of output filter to switching harmonics, causes inverter outlet side to there is harmonic wave.Particularly at line voltage at zero crossings, switching frequency can be very often low, can cause output current produce distortion, cause the advantage of hysteresis control method thereof not give full play in three-level inverter.
Summary of the invention
The object of the invention is to the hysteresis control method thereof by a kind of three-level inverter, solve the problem that above background technology part is mentioned.
For reaching this object, the present invention by the following technical solutions:
A hysteresis control method thereof for three-level inverter, it specifically comprises:
S101, current i when the actual output of inverter bridge
lwith instruction current i
refdifference DELTA i when being less than negative sense ring width (-H), calculate inverter bridge actual output current i
lrate of change, instruction current i
refrate of change, setting binding hours T
lmt, by multilevel iudge, select three-level inverters to need to export positive level U
+or zero level state, make the current i of the actual output of inverter bridge
lrise;
S102, current i when the actual output of inverter bridge
lwith instruction current i
refdifference DELTA i when being greater than forward ring width (H), calculate inverter bridge actual output current i
lrate of change, instruction current i
refrate of change, setting binding hours T
lmt, by multilevel iudge, select three-level inverters to need to export negative level U
-or zero level state, make the current i of the actual output of inverter bridge
ldecline.
Especially, described step S101 specifically comprises: if at t
0position, the current i of the actual output of inverter bridge
lwith instruction current i
refdifference DELTA i be less than negative sense ring width (-H), then change the output state of inverter bridge, make the current i of the actual output of inverter bridge
lrise; For ensureing the tracking accuracy of inverter, need Limited Current i
lrise time t
on, t
onbinding hours T can not be greater than
lmt;
Instruction current i
refrate of change be
at rise time t
onin time, i
refvariation delta i
reffor
at rise time t
onin, due to instruction current i
refsize has changed Δ i
ref, the pressed on ring i of stagnant ring
upwith lower ring i
downsize changed Δ i respectively
ref; Inverter bridge actual output current i
lrate of change be
it is at t
onin time, i
lvariation delta i
lbe respectively
at rise time t
onin, if current i
lcan from stagnant ring lower limit i
downchange to upper limit i
up, Δ i
lneed change 2 × H+ Δ i
ref, namely
For making the current i of the actual output of inverter bridge
lrise, optional inverter bridge output state has positive level U
+or zero level two states:
When selected inverter bridge exports positive level state, current i
lrate of change be
wherein u
ofor three-level inverter output voltage, L is series inductance after three-level inverters; When selected inverter bridge exports zero level state, current i
lrate of change be
current i during selected inverter bridge output positive level
lclimbing be greater than selected inverter bridge export zero level time current i
lclimbing;
If current i during inverter bridge selected output zero level
lcan at binding hours T
lmtin can reach pressed on ring, then selected inverter bridge exports the lowermost switch frequency that zero level state just can ensure converter bridge switching parts pipe, and then ensures the tracking accuracy of inverter, otherwise selected inverter bridge output positive level state, namely when
time, selected inverter bridge exports zero level state, otherwise selected inverter bridge exports positive level state.
Especially, described step S102 specifically comprises: if at t
1position, the current i of the actual output of inverter bridge
lwith instruction current i
refdifference DELTA i be greater than forward ring width (H), then change the output state of inverter bridge, make the current i of the actual output of inverter bridge
ldecline; For ensureing the tracking accuracy of inverter, need Limited Current i
lt fall time
off, t
offbinding hours T can not be greater than
lmt;
Instruction current i
refrate of change be
at t fall time
offin time, i
refvariation delta i
reffor
at t fall time
offin, due to instruction current i
refsize has changed Δ i
ref, the pressed on ring i of stagnant ring
upwith lower ring i
downsize changed Δ i respectively
ref; Inverter bridge output current i
lrate of change be
it is at t
offin time, i
lvariation delta i
lbe respectively
at t fall time
offin, if current i
lcan from stagnant ring upper limit i
upchange to lower limit i
down, Δ i
lneed change-2 × H+ Δ i
ref, namely
For making the current i of the actual output of inverter bridge
ldecline, optional inverter bridge output state has negative level U
-or zero level two states:
When selected inverter bridge exports negative level state, current i
lrate of change be
current i during selected zero level
lrate of change be
current i during selected inverter bridge output negative level
lrate of descent be greater than selected inverter bridge and export zero level current i
lrate of descent;
If current i during inverter bridge selected output zero level
lcan at binding hours T
lmtin can reach lower ring, then selected inverter bridge exports the lowermost switch frequency that zero level just can ensure converter bridge switching parts pipe, and then the tracking accuracy of guarantee inverter; If at binding hours T
lmtinterior current i
lcan not reach lower ring, then selected inverter bridge exports negative level state; Namely when
time, selected inverter bridge exports zero level state, otherwise selected inverter bridge exports negative level state.
The hysteresis control method thereof of the three-level inverter that the present invention proposes achieves and controls the reliable current hysteresis loop tracking of three-level inverter, limit the lowermost switch frequency of three-level inverter Hysteresis control, ensure that three-level inverter current tracking effect, improve inverter performance; Solve traditional Hysteresis control three-level inverter too low at output voltage near zero-crossing point switching frequency, cause the problem that output current distorts.
Accompanying drawing explanation
Fig. 1 is the fundamental diagram of Hysteresis control;
The three-phase tri-level inverter structure schematic diagram that Fig. 2 provides for the embodiment of the present invention;
The hysteresis control method thereof schematic diagram of the three-level inverter that Fig. 3 provides for the embodiment of the present invention;
The curent change schematic diagram of the Hysteresis control that Fig. 4 provides for the embodiment of the present invention.
The control of the hysteresis control method thereof of the three-level inverter that Fig. 5-1 and Fig. 5-2 provides for the embodiment of the present invention
Effect waveform processed;
The single-phase H bridge three-level inverter structural representation that Fig. 6 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not full content.
Please refer to shown in Fig. 3, the hysteresis control method thereof schematic diagram of the three-level inverter that Fig. 3 provides for the embodiment of the present invention.In the present embodiment, the hysteresis control method thereof of three-level inverter specifically comprises:
The output of three-level inverters has positive level U
+, negative level U
-with zero level three kinds of states.After inverter bridge exports positive level, inverter bridge output current i
lbe in propradation.After inverter bridge exports negative level, inverter bridge output current i
lbe in decline state.After inverter bridge exports zero level, inverter bridge output current i
lchange direction may rise and also may decline, and actual change direction is relevant to the polarity of line voltage.
S101, current i when the actual output of inverter bridge
lwith instruction current i
refdifference DELTA i be less than negative sense ring width (-H), calculate inverter bridge actual output current i
lrate of change, instruction current i
refrate of change, setting binding hours T
lmt, by multilevel iudge, select three-level inverters to need to export positive level U
+or zero level state, make the current i of the actual output of inverter bridge
lrise.
As shown in Figure 4, if at t
0position, the current i of the actual output of inverter bridge
lwith instruction current i
refdifference DELTA i be less than negative sense ring width (-H), then change the output state of inverter bridge, make the current i of the actual output of inverter bridge
lrise; For ensureing the lowermost switch frequency of converter bridge switching parts pipe, need Limited Current i
lrise time t
on, t
onbinding hours T can not be greater than
lmt;
Instruction current i
refrate of change be
at rise time t
onin time, i
refvariation delta i
reffor
at rise time t
onin, due to instruction current i
refsize has changed Δ i
ref, the pressed on ring i of stagnant ring
upwith lower ring i
downsize changed Δ i respectively
ref; Inverter bridge actual output current i
lrate of change be
it is at t
onin time, i
lvariation delta i
lbe respectively
at rise time t
onin, if current i
lcan from stagnant ring lower limit i
downchange to upper limit i
up, Δ i
lneed change 2 × H+ Δ i
ref, namely
For making the current i of the actual output of inverter bridge
lrise, optional inverter bridge output state has positive level U
+or zero level two states:
When selected inverter bridge exports positive level state, current i
lrate of change be
wherein u
ofor three-level inverter output voltage, L is series inductance after three-level inverters; When selected inverter bridge exports zero level state, current i
lrate of change be
current i during selected inverter bridge output positive level
lclimbing be greater than selected inverter bridge export zero level time current i
lclimbing;
If current i during inverter bridge selected output zero level
lcan at binding hours T
lmtin can reach pressed on ring, then selected inverter bridge exports the lowermost switch frequency that zero level state just can ensure converter bridge switching parts pipe, and then ensures the tracking accuracy of inverter, otherwise selected inverter bridge output positive level state, namely when
time, selected inverter bridge exports zero level state, otherwise selected inverter bridge exports positive level state.
S102, current i when the actual output of inverter bridge
lwith instruction current i
refdifference DELTA i when being greater than forward ring width (H), calculate inverter bridge actual output current i
lrate of change, instruction current i
refrate of change, setting binding hours T
lmt, by multilevel iudge, select three-level inverters to need to export negative level U
-or zero level state, make the current i of the actual output of inverter bridge
ldecline.
As shown in Figure 4, if at t
1position, the current i of the actual output of inverter bridge
lwith instruction current i
refdifference DELTA i be greater than forward ring width (H), then change the output state of inverter bridge, make the current i of the actual output of inverter bridge
ldecline; For ensureing the tracking accuracy of inverter, need Limited Current i
lt fall time
off, t
offbinding hours T can not be greater than
lmt;
Instruction current i
refrate of change be
at t fall time
offin time, i
refvariation delta i
reffor
at t fall time
offin, due to instruction current i
refsize has changed Δ i
ref, the pressed on ring i of stagnant ring
upwith lower ring i
downsize changed Δ i respectively
ref; Inverter bridge output current i
lrate of change be
it is at t
offin time, i
lvariation delta i
lbe respectively
at t fall time
offin, if current i
lcan from stagnant ring upper limit i
upchange to lower limit i
down, Δ i
lneed change-2 × H+ Δ i
ref, namely
For making the current i of the actual output of inverter bridge
ldecline, optional inverter bridge output state has negative level U
-or zero level two states:
When selected inverter bridge exports negative level state, current i
lrate of change be
current i during selected zero level
lrate of change be
current i during selected inverter bridge output negative level
lrate of descent be greater than selected inverter bridge and export zero level current i
lrate of descent;
If current i during inverter bridge selected output zero level
lcan at binding hours T
lmtin can reach lower ring, then selected inverter bridge exports the lowermost switch frequency that zero level just can ensure converter bridge switching parts pipe, and then the tracking accuracy of guarantee inverter; If at binding hours T
lmtinterior current i
lcan not reach lower ring, then selected inverter bridge exports negative level state; Namely when
time, selected inverter bridge exports zero level state, otherwise selected inverter bridge exports negative level state.
In the present embodiment, the control effects waveform of the hysteresis control method thereof of three-level inverter is as shown in Fig. 5-1 and 5-2.
For three-phase tri-level inverter, detailed process of the present invention is described in detail below: as shown in Figure 2, a kind of three level current hysteresis-band control device comprises three-level inverters, output filter, current sensor, voltage sensor, driving control unit etc., and wherein stagnant ring comparing unit is positioned at driving control unit.Can, by the driving of change inverter bridge breaker in middle pipe, inverter bridge be made to export U
+, U
-with 0 three kinds of level, and then control current i on inverter bridge outputting inductance
lsize and Orientation, to ensure i
lall the time within stagnant ring ring width.In the present embodiment, the hysteresis control method thereof detailed process of three-level inverter is as follows:
1) when any one occurs i mutually
l-i
ref<-H, now needs the output state changing inverter bridge, makes i
lrise.Optional inverter bridge output level has U
+or 0 two kinds.After selected zero level, the rate of change of inductive current
the rate of change of instruction current
go out by instruction change calculations.
The ring width H that selected stagnant cyclization is suitable.The time T that the selected lowermost switch frequency limited is corresponding
lmt.
When
time, open Q2 and Q3 pipe, turn off Q1 and Q4 pipe, make inverter bridge export zero level.
When
time, open Q1 and Q2 pipe, turn off Q3 and Q4 pipe, make inverter bridge export U
+level.
2) when any one occurs i mutually
l-i
ref> H, now needs the output state changing inverter bridge, makes i
ldecline.Optional inverter bridge output level has U
-or 0 two kinds.
After selected zero level, the rate of change of inductive current
the rate of change of instruction current
go out by instruction change calculations.
The ring width H that selected stagnant cyclization is suitable.The time T that the selected lowermost switch frequency limited is corresponding
lmt.
When
open Q2 and Q3 pipe, turn off Q1 and Q4 pipe, make inverter bridge export zero level.
When
time, open Q4 and Q3 pipe, turn off Q1 and Q2 pipe, make inverter bridge export U
-level.
The three-phase output state of three-level inverter calculates respectively by the present invention.In the present embodiment, the those of ordinary skill in the art such as three phase inverter bridge, output filter, current sensor, voltage sensor, driving control unit can be realized by existing known technology.The present invention is equally applicable to the three-phase three-line system that bus capacitor mid point does not connect.
It should be noted that, single-phase inverter is equally applicable to the present invention, only need calculating one phase inverter bridge actual output current rate of change, instruction current rate of change, limit lowermost switch frequency, and pass through multilevel iudge, calculate the level state that three-level inverters needs to export, realize hysteretic loop current control, detailed process is the same, does not repeat them here.As shown in Figure 6, be single-phase H bridge inverter, in this inverter, have employed known H bridge three-level inverters, the those of ordinary skill in the art such as output filter, current sensor, voltage sensor, driving control unit can be realized by existing known technology.
Technical scheme of the present invention achieves and controls the reliable current hysteresis loop tracking of three-level inverter, limits the lowermost switch frequency of three-level inverter Hysteresis control, ensure that three-level inverter current tracking effect, improve inverter performance; Solve traditional Hysteresis control three-level inverter too low at output voltage near zero-crossing point switching frequency, cause the problem that output current distorts.
Below know-why of the present invention is described in conjunction with specific embodiments.These describe just in order to explain principle of the present invention, and can not be interpreted as limiting the scope of the invention by any way.Based on explanation herein, those skilled in the art does not need to pay performing creative labour can associate other embodiment of the present invention, and these modes all will fall within protection scope of the present invention.
Claims (3)
1. a hysteresis control method thereof for three-level inverter, is characterized in that, specifically comprises:
S101, current i when the actual output of inverter bridge
lwith instruction current i
refdifference DELTA i when being less than negative sense ring width (-H), calculate inverter bridge actual output current i
lrate of change, instruction current i
refrate of change, setting binding hours T
lmt, by multilevel iudge, select three-level inverters to need to export positive level U
+or zero level state, make the current i of the actual output of inverter bridge
lrise;
S102, current i when the actual output of inverter bridge
lwith instruction current i
refdifference DELTA i when being greater than forward ring width (H), calculate inverter bridge actual output current i
lrate of change, instruction current i
refrate of change, setting binding hours T
lmt, by multilevel iudge, select three-level inverters to need to export negative level U
-or zero level state, make the current i of the actual output of inverter bridge
ldecline.
2. the hysteresis control method thereof of three-level inverter according to claim 1, is characterized in that, described step S101 specifically comprises: if at t
0position, the current i of the actual output of inverter bridge
lwith instruction current i
refdifference DELTA i be less than negative sense ring width (-H), then change the output state of inverter bridge, make the current i of the actual output of inverter bridge
lrise; For ensureing the tracking accuracy of inverter, need Limited Current i
lrise time t
on, t
onbinding hours T can not be greater than
lmt;
Instruction current i
refrate of change be
at rise time t
onin time, i
refvariation delta i
reffor
at rise time t
onin, due to instruction current i
refsize has changed Δ i
ref, the pressed on ring i of stagnant ring
upwith lower ring i
downsize changed Δ i respectively
ref; Inverter bridge actual output current i
lrate of change be
it is at t
onin time, i
lvariation delta i
lbe respectively
at rise time t
onin, if current i
lcan from stagnant ring lower limit i
downchange to upper limit i
up, Δ i
lneed change 2 × H+ Δ i
ref, namely
For making the current i of the actual output of inverter bridge
lrise, optional inverter bridge output state has positive level U
+or zero level two states:
When selected inverter bridge exports positive level state, current i
lrate of change be
wherein u
ofor three-level inverter output voltage, L is series inductance after three-level inverters; When selected inverter bridge exports zero level state, current i
lrate of change be
current i during selected inverter bridge output positive level
lclimbing be greater than selected inverter bridge export zero level time current i
lclimbing;
If current i during inverter bridge selected output zero level
lcan at binding hours T
lmtin can reach pressed on ring, then selected inverter bridge exports the lowermost switch frequency that zero level state just can ensure converter bridge switching parts pipe, and then ensures the tracking accuracy of inverter, otherwise selected inverter bridge output positive level state, namely when
time, selected inverter bridge exports zero level state, otherwise selected inverter bridge exports positive level state.
3. the hysteresis control method thereof of three-level inverter according to claim 1, is characterized in that, described step S102 specifically comprises: if at t
1position, the current i of the actual output of inverter bridge
lwith instruction current i
refdifference DELTA i be greater than forward ring width (H), then change the output state of inverter bridge, make the current i of the actual output of inverter bridge
ldecline; For ensureing the tracking accuracy of inverter, need Limited Current i
lt fall time
off, t
offbinding hours T can not be greater than
lmt;
Instruction current i
refrate of change be
at t fall time
offin time, i
refvariation delta i
reffor
at t fall time
offin, due to instruction current i
refsize has changed Δ i
ref, the pressed on ring i of stagnant ring
upwith lower ring i
downsize changed Δ i respectively
ref; Inverter bridge output current i
lrate of change be
it is at t
offin time, i
lvariation delta i
lbe respectively
at t fall time
offin, if current i
lcan from stagnant ring upper limit i
upchange to lower limit i
down, Δ i
lneed change-2 × H+ Δ i
ref, namely
For making the current i of the actual output of inverter bridge
ldecline, optional inverter bridge output state has negative level U
-or zero level two states:
When selected inverter bridge exports negative level state, current i
lrate of change be
current i during selected zero level
lrate of change be
current i during selected inverter bridge output negative level
lrate of descent be greater than selected inverter bridge and export zero level current i
lrate of descent;
If current i during inverter bridge selected output zero level
lcan at binding hours T
lmtin can reach lower ring, then selected inverter bridge exports the lowermost switch frequency that zero level just can ensure converter bridge switching parts pipe, and then the tracking accuracy of guarantee inverter; If at binding hours T
lmtinterior current i
lcan not reach lower ring, then selected inverter bridge exports negative level state; Namely when
time, selected inverter bridge exports zero level state, otherwise selected inverter bridge exports negative level state.
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| CN105656309A (en) * | 2016-03-14 | 2016-06-08 | 广东明阳龙源电力电子有限公司 | Hardware hysteresis current control method used for wind power converter |
| CN106253727A (en) * | 2016-08-23 | 2016-12-21 | 重庆大学 | Many level hysteresis control method thereof based on error change amount |
| CN110932586A (en) * | 2019-12-12 | 2020-03-27 | 北京自动化控制设备研究所 | Method and device for reducing switching frequency of current hysteresis loop control full-bridge inverter |
| CN113093083A (en) * | 2021-03-24 | 2021-07-09 | 中国电力科学研究院有限公司 | Method and system for testing transient performance of current transformer for direct-current engineering direct-current field |
| CN113472232A (en) * | 2021-07-12 | 2021-10-01 | 北京国科翼达电力节能科技有限公司 | Five-level hysteresis comparison inverter |
| CN113725854A (en) * | 2021-09-01 | 2021-11-30 | 青岛鼎信通讯股份有限公司 | Seamless switching control method applied to flexible direct current comprehensive voltage regulating device |
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| CN105656309A (en) * | 2016-03-14 | 2016-06-08 | 广东明阳龙源电力电子有限公司 | Hardware hysteresis current control method used for wind power converter |
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| CN106253727B (en) * | 2016-08-23 | 2019-01-29 | 重庆大学 | More level hysteresis control method thereofs based on error change amount |
| CN110932586A (en) * | 2019-12-12 | 2020-03-27 | 北京自动化控制设备研究所 | Method and device for reducing switching frequency of current hysteresis loop control full-bridge inverter |
| CN113093083A (en) * | 2021-03-24 | 2021-07-09 | 中国电力科学研究院有限公司 | Method and system for testing transient performance of current transformer for direct-current engineering direct-current field |
| CN113472232A (en) * | 2021-07-12 | 2021-10-01 | 北京国科翼达电力节能科技有限公司 | Five-level hysteresis comparison inverter |
| CN113725854A (en) * | 2021-09-01 | 2021-11-30 | 青岛鼎信通讯股份有限公司 | Seamless switching control method applied to flexible direct current comprehensive voltage regulating device |
| CN113725854B (en) * | 2021-09-01 | 2023-08-08 | 青岛鼎信通讯股份有限公司 | Seamless switching control method applied to flexible direct-current comprehensive voltage regulating device |
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